Sony BVH-2000, Operation And Maintenance Manual

Page: 346 / 505

(5-7-8. SV-43 Board)
and
The 8-byte interface memories (IC3P,3Q,3R4P,4Q,4R) are used
between the SY-80's CPU and the SV-43' s CPU so that the servo
system should
be controlled in accordance with the VTR's
operating mode that is specified by the system control of the
machine. These interface memories can bewritten-down and
read-out four output of
bytes are used for interface from the servo to the system control
(where addresses
are "lOOOH to l003H") while the other four
are used for interface from the system control to the servo
(where addresses are "F400H to F403H"). The SV-43's CPU and
the SY-80's CPU are judged whether they are ready to accept
commands
or not by looking at the SV READY (pin No.
24 output) and at the SY READY (input from the pin No.
SV-43:SY-80
IC3P,3Q
I
AO
t
A1
I
4-BYTE
I
SVS>SY
I
INTERFACE
I
MEMORY
I
I
IC4P,4Q
I
I
4-BYTE
I
I
- SV¢::JSY
!--
I
.............
INTERFACE
.........
I
I
MEMORY
I
55 WR
00-07
55 RO
55
AO
t
A1
RO
BVH-2000(U/C)/PS/PM
BVH-2180(U/C)/PS/PM
The SV-43 board controls all the rest of circuit board that are
used
servo Control is made from the SV-43
other servo boards mainly through the HARD CPU's bus, but
partly through the I/O port
The servo related boards have the specific
addresses
shown as follows. The data are directed to
certain circuit board specified by the address decoder IC2-0,
and
are output. The IC6P is the data bus's buffer that
determines direction of data flow, the IOREQ
signal and the RD signal from the CPU.
DO
I HARD CPU DATA BUS
AO
I
A7
¢
--It---------~
12.5MHzl
~ C>--
~_}~E/CD!SR
---------d..:~
5000..-----------...-----5'00
SERVO I/O
5100 504
53FF 508
soc
50FF
rv
v
RL I/O
0
CD,SR I/O
o --
0
SV I/O
EXT I/O
5-7-23
SERVO SYSTEM
z
o
i=
«
a:
w
0..
o
LL
o
>-
a:
o
w
I
r-
LO