(5-7-8. SV-43 Board)
8. I/O
Port of
the
HOST
CPU
PORT
The
port of the HOST CPU consists of
and IC4I,
that are addressed
as "1200H
. This
port is
used to read the setting position
of various
switches
and
operating
status of the various circuits inside the board
A part of the input port is connected to the output port (IC6-0-
7:HARD OUT) of the HARD CPU for monitoring
whether the
HARD CPU is operating
normally.
Address 1200H
S1-3 (always
Reserved for spare.
"1"
is
Sl-2:HARD
ACCESS
Reading the switch's
data and
them into
the memory.
The S1-2 is normally set to "OFF'
so that the D6 is set to
""1".
z
o
I-
«
a:::
w
0...
o
u..
o
>-
a:::
o
w
I
I-
LO
When S1-2 is set to ""ON", the D6 will be "0" so that the
HARD CPU's memory I/O cannot be accessed(inhibited)
even though the HOST CPU designates
the address.
HARD ABN (ABNORMAL)
When
CPU s program error detector detects
an error, ""1" is read.
HOST
When the
CPU's overcount detector counts "0 to
3", "0" is read When it counts "4 to 7", "1" is read
D3:
HOST ABN (ABNORMAL)
When the HOST CPU's program error detector detects an
error, "1" is read
D2:
SY READY
When the SY-80's CPU operates normally, ""l" is read
HARD
This data is detected by
CPU's program error
detector. When
HARD
operates
"1" is
read
DO:
REF V
The REF V. signal having
the duty 50% cycle, with
negative going edge of vertical timing, is read
SERVO SYSTEM
OUTPUT
The output port of the
CPU consists of IC5I, that is
addressed
as "1200H (WR mode)". This output port is mainly
used to inform the HOST CPU's operating
conditions
to the
HARD CPU.
Address
1200H
D5:
DATA TRANSFER
ENEBLE
This is the signal enabling to transfer the HOST CPU's
data to the HARD CPU. Data are transfered when the D5
is set to "1".
04:
BUS
"~lL_"""J"_"
When
is set to "1", the
CPU releases the buses
such as data bus, address bus and control bus. The HOST
CPU occupies these buses.
D3:
SV 01
This signal is output to the SY-80 board's input port, but
is not used
D2:
HARD RESET
This signal inhibits opration of the mechanism
such as
motor and solenoid
when the system is initializing
This
This
CPU s
conditions
to the
CPU. As
as the HOST CPU operates
normally, ""
1"
is oputput
DO:
INT (INTERRUPT)
TIME
During when the HOST CPU is processing the interrupt
routine, DO is set to
"I",
The time required for interrupt
routine can be measured
at TP8.
5-7-24
BVH-2000(U/C)/PS/PM
BVH-2180( U/C)/PS/PM
Summary of Contents for BVH-2000
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