Sony BVH-2000, Operation And Maintenance Manual

Page: 317 / 505

(5-6-7. Common Memory)
The LG board control panel, servo system, time code reader!
generator and REMOTE-3 data are and
stored in this area. Addresses A200H A27FH are used as
the port data area of the SY-79 board while addresses A280H
through A2FFH are used as the port data area of the SY-80
board.
MEMORY MAP
A200
AlIO
A218
PARALLEL I/O
... Parallel I/O Data
Switch
LED/LAMP/CLUTCH ... LED, Lamp, Clutch
ON/OFF
COMMON MEMORY
SY-80
OATA 8US
SY -79 AORS BUS
--+--fiI--+---O
SY- 80 AORS BUS -.;. ............. .-...0
SYSTEM CONTROL SYSTEM
This area is composed of 64 counters. Four bytes are allocated
to each counter and these are used
to handle the time
data.
In order to be accessed from two CPUs, the common memory
exercises control
a to one while
the other is accessing.
For instance,
when the SY-80 board CPU is accessing the
common memory, the gate IC I G-2 set high by the
..~COMMON from the address
decoder IC2E-ll. The common memory is not accessed from
the SY-79 board CPU and so the pin-37B "~SY COM" signal is
made inactive
and is set the
flip-flop ICI G-6 is set high and ICI G-8 is set low.
The high-level output of the flip-flop IC IG-6 is input through
the inverter IC2G-IO into the common memory address selector
IC 1
I L and I and the SY-80 board address bus is selected.
Furthermore, the ICI G-6 output disables the bus buffer IC2M
through the inverter IC5 E-8, and the SY-79 board data bus is
isolated from the data bus of
common
rYlCl.rYlr,t'"'lT
In addition, the low-level output of the flip-flop IC IG-8 enables
the bus buffer JC2L and it connects the SY-80 board data bus to
the common
memory.
When the SY-80 board CPU is accessing the common memory,
the "~SY COM"
is input from the SY-79 board to pin-
where the board CPU has to
access the common memory. The '''~SY COM" signal sets
IC3G-12 high through the inverter IC3M-IO but since the flip-
lG-6 is IC3G-l set low, the is returned
from pin-25A to the SY-79 board as the "~SY WAIT' signal,
and the CPU on the SY-79 board is set to the wait condition.
When the SY-80 CPU has finished the common
memory, "'COMMON of the
address decoder IC2E-Il is set high and the status of the flip-
flop ICIG is inverted. When the "~SY COM" signal from the
SY-79 board
active at time, the common is
accessed the SY-79 board CPU.
8 SY-79
-"OATA BUS
5-6-12
BVH-2000(U/C)/PS/PM
BVH-2180(U/C)/PS/PM