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Si5345-44-42-D-RM

66

Rev. 1.0

11.3. Recommended Oscillators

Table 39 lists recommended TCXO suppliers.

11.4. Register Settings to Control External XTAL Reference

The following registers can be used to control and make adjustments for the external reference source used.

11.4.1. XAXB_FREQ_OFFSET Frequency Offset Register

The VCO locks to the XO that is formed by the crystal or XO and the XAXB pins. XAXB_FREQ_OFFSET provides
a static frequency offset to the VCO frequency. It is a 32-bit 2's complement number. This register can be used to
adjust the frequency of the VCO when it is locked to the XAXB frequency. The Default value is 0.

11.4.2. XAXB_EXTCLK_EN Reference Clock Selection Register

This bit selects between XTAL or external REFCLK on the XA/XB pins. Set this bit to use the external REFCLK.

Table 39. Recommended Oscillator Suppliers

Supplier

Part Number

TCXO/

OCXO

Frequency

Case

Size (mm x mm x mm)

Epson

TG-5500CA-68N-
49.1520000MHz

TCXO

49.152 MHz

5x7

Epson

TG-5500-67N-40.00000MHz

TCXO

40 MHz

5x7

Rakon

513872 (40MHz RTX7050A
HCMOS)

TCXO

40.000

5x7

NDK

NT7050BB-40.000M-
ENA4199B

TCXO

40.000

5x7

Vectron

VT-803-EAH-2870-40M0000

TCXO

40.000

5x3.2

Vectron

VT-803-EAH-2870-49M1520

TCXO

49.152

5x3.2

Vectron

VT-803-EAH-2870-50M0000

TCXO

50.000

5x3.2

Table 40. XAXB Frequency Offset Register

Register Name

Hex

Address

[Bit Field]

Function

XAXB_FREQ_OFFSET

0202[7:0]-

0205[7:0]

32-bit number which allows adjustment to the center frequency of the
XTAL in the range of ±1000 ppm.

Table 41. XAXB External Clock Selection Register

Register Name

Hex

Address

[Bit Field]

Function

XAXB_EXTCLK_EN

090E[0]

This bit selects between the XTAL or external REFCLK on the XA/XB pins.
The default is XTAL = 0

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Summary of Contents for Si5342

Page 1: ...Rev 1 0 7 16 Copyright 2016 by Silicon Laboratories Si5345 44 42 D RM ANY FREQUENCY ANY OUTPUT JITTER ATTENUATORS CLOCK MULTIPLIERS Si5345 Si5344 Si5342 REV D FAMILY REFERENCE MANUAL ...

Page 2: ... IN1 IN2 IN3 21 5 1 1 Manual Input Switching 21 5 1 2 Automatic Input Selection 22 5 2 Types of Inputs 23 5 2 1 Unused Inputs 24 5 2 2 Hitless Input Switching with Phase Buildout 24 5 2 3 Ramped Input Switching 25 5 2 4 Glitchless Input Switching 25 5 2 5 Synchronizing to Gapped Input Clocks 26 5 3 Fault Monitoring 26 5 3 1 Input Loss of Signal LOS Fault Detection 27 5 3 2 Out of Frequency OOF Fau...

Page 3: ...lock Selection Register 66 11 4 3 PXAXB Pre scale Divide Ratio for Reference Clock Register 67 12 Crystal and Device Circuit Layout Recommendations 68 12 1 64 Pin QFN Si5345 Layout Recommendations 68 12 1 1 Si5345 Applications without a Crystal 68 12 1 2 Si5345 Crystal Guidelines 68 12 1 3 Output Clocks 72 12 2 44 Pin QFN Si5344 42 Layout Recommendations 73 12 2 1 Si5342 44 Applications without a ...

Page 4: ...age 9 Registers Si5344 170 14 4 8 Page A Registers Si5344 172 14 4 9 Page B Registers Si5344 173 14 5 Si5342 Register Definitions 174 14 5 1 Page 0 Registers Si5342 174 14 5 2 Page 1 Registers Si5342 191 14 5 3 Page 2 Registers Si5342 195 14 5 4 Page 3 Registers Si5342 202 14 5 5 Page 4 Registers Si5342 205 14 5 6 Page 5 Registers Si5342 206 14 5 7 Page 9 Registers Si5342 215 14 5 8 Page A Registe...

Page 5: ...Example of Independently Configurable Path Delays 45 Figure 21 Si5345 Zero Delay Mode Set up 47 Figure 22 DCO with FINC FDEC Pins or Bits 50 Figure 23 I2C SPI Device Connectivity Configurations 52 Figure 24 I2C Configuration 53 Figure 25 7 bit I2C Slave Address Bit Configuration 53 Figure 26 I2C Write Operation 54 Figure 27 I2C Read Operation 54 Figure 28 SPI Interface Connections 55 Figure 29 Exa...

Page 6: ...ayer 8 72 Figure 48 Device Layer Layer 1 73 Figure 49 Crystal Shield Layer 2 74 Figure 50 Ground Plane Layer 3 74 Figure 51 Power Plane and Clock Output Power Supply Traces Layer 4 75 Figure 52 Clock Input Traces Layer 5 75 Figure 53 Low Speed CMOS Control and Status Signal Layer 6 Bottom Layer 76 Figure 54 FINC FDEC Logic Diagram 87 Figure 55 Logic Diagram of the FINC FDEC Masks 113 Figure 56 Log...

Page 7: ... Choice 35 Table 19 Output Signal Format Control Registers 36 Table 20 Differential Output Voltage Swing Control Registers 38 Table 21 Differential Output Common Mode Voltage Control Registers 38 Table 22 Output Impedance and Drive Strength Selections 39 Table 23 LVCMOS Drive Strength Control Registers 40 Table 24 LVCMOS Output Polarity Control Registers 41 Table 25 Output Polarity of OUTx and OUT...

Page 8: ... Definitions Above 147 Table 52 Registers that Follow the P0_NUM and P0_DEN 151 Table 53 Registers that Follow the R0_REG 154 Table 54 Registers that Follow the N0_NUM and N0_DEN Definitions 157 Table 55 Registers that Follow the N0_FSTEPW Definition 158 Table 56 Registers that Follow the Same Definition as Above 193 Table 57 Registers that Follow the P0_NUM and P0_DEN Definitions 196 Table 58 Reg...

Page 9: ...important to understand that the intent is for customers to use the ClockBuilder Pro software to provide the initial configuration for the device Although the register map is documented all the details of the algorithms to implement a valid frequency plan are fairly complex and are beyond the scope of this document Real time changes to the frequency plan and other operating settings are supported ...

Page 10: ...is all done with one software tool ClockBuilder Pro integrates all the data sheets application notes and information that might be helpful in one environment It is intended that customers will use the software tool for the proper configuration of the device Register map descriptions given in the document should not be the only source of information for programming the device The complexity of the ...

Page 11: ...Synth generated frequencies to any of the outputs A single MultiSynth output can connect to two or more output drivers Additional integer division R determines the final output frequency as shown in Figure 2 Figure 2 Si5342 DSPLL and Multisynth System Flow Diagram The frequency configuration of the DSPLL is programmable through the SPI or I2 C serial interface and can also be stored in non volatil...

Page 12: ...wly written divider value to take effect Output R divider Only even integer divide values Min value is 2 Maximum value is 225 2 3 2 DSPLL Loop Bandwidth The DSPLL loop bandwidth determines the amount of input clock jitter attenuation and wander filtering Register configurable DSPLL loop bandwidth settings in the range of 0 1 Hz to 4 kHz are available for selection Since the loop bandwidth is contr...

Page 13: ...p Fastlock and Holdover bandwidths simultaneously The loss of lock LOL feature is a fault monitoring mechanism Details of the LOL feature can be found in 5 3 3 Loss of Lock Fault Monitoring on page 29 3 2 2 Holdover Exit Bandwidth In addition to the operating loop and fastlock bandwidths there is also a user selectable bandwidth when exiting holdover and locking or relocking to an input clock avai...

Page 14: ...iod is complete No clocks will be generated until initialization is complete There are two types of resets available A hard reset is functionally similar to a device power up All registers are restored to the values stored in NVM and all circuits including the serial interface are restored to their initial state A hard reset is initiated using the RST pin or by asserting the hard reset bit A soft ...

Page 15: ...e specific clock frequencies at power up Writing default values to NVM is in circuit programmable with normal operating power supply voltages applied to its VDD 1 8V and VDDA 3 3 V pins Table 5 Reset Registers Register Name Hex Address Bit Field Function HARD_RST 0x001E 1 Performs the same function as power cycling the device All registers will be restored to their default values SOFT_RST 0x001C 0...

Page 16: ... 2 2 Revision D The revision D preamble and postamble values for updating certain registers during device operation have changed after revision B Either the new or old values below may be written to revision D or later devices without issue No system software changes are necessary for legacy systems When writing old values note that reading back these registers will not give the written old values...

Page 17: ...ft of the crystal frequency will be tracked at the output clock frequencies A TCXO or OCXO is recommended for applications that need better frequency accuracy and stability while in freerun or holdover modes Because there is little or no jitter attenuation from the XAXB pins to the clock outputs a low jitter XAXB source will be needed for low jitter clock outputs 4 5 Acquisition Mode The device mo...

Page 18: ...ed new output frequency is measured It is quite possible even likely that the new output clock frequency will not be the same as the holdover output frequency because the new input clock frequency might have changed and the holdover history circuit may have changed the holdover output frequency The ramp logic calculates the difference in frequency between the holdover frequency and the new desired...

Page 19: ... Mask ignore Holdover Freerun for interrupt HOLD_HIST_VALID 0x053F 1 Holdover historical frequency data valid 0 Incomplete Holdover history Freerun mode available 1 Valid Holdover history Holdover mode available Holdover Control and Settings HOLD_HIST_LEN 0x052E 4 0 Window Length time for historical average frequency used in Holdover mode Window Length in seconds s Window Length 2HOLD_HIST_LEN 1 x...

Page 20: ...11 Use Normal Loop bandwidth on Holdover exit HOLDEXIT_BW_SEL1 0x052C 4 Select the exit bandwidth from Holdover when ramped exit is not selected HOLD_RAMP_BYP 1 00 Use Fastlock bandwidth on Holdover exit 01 Use Holdover Exit bandwidth on Holdover exit default 10 11 Use Normal Loop bandwidth on Holdover exit RAMP_STEP_INTERVAL 0x052C 7 5 Time Interval of the frequency ramp steps when ramping betwee...

Page 21: ...t selection on the pins Note that when Zero Delay Mode is enabled the FB_IN pins will become the feedback input and IN3 therefore is not available as a clock input Also in Zero Delay Mode ZDM_EN must be set and register based input clock selection must be done with ZDM_IN_SEL If there is no clock signal on the selected input the device will automatically enter free run or holdover mode Table 8 Inp...

Page 22: ... switching or else the IO delay can change on each input switch Manual control of the input clock selection is by either pin or register and also depends upon the device being in zero delay mode or not See Table 11 Table 10 Registers for Automatic Input Selection Register Name Hex Address Bit Field Function CLK_SWITCH_MODE 0x0536 1 0 Selects manual or automatic switching modes Automatic mode can b...

Page 23: ...ls are DC coupled and use the Pulsed CMOS Input Buffer selection In all cases the inputs should be terminated near the device input pins as shown in Figure 7 The resistor divider values given below will work with up to 1 MHz pulsed inputs Figure 7 Input Termination for Standard and Pulsed CMOS Inputs Pulsed CMOS DC Coupled Single Ended Standard AC Coupled Single Ended 100 3 3V 2 5V 1 8V LVCMOS Sta...

Page 24: ...g between two clock inputs with the exact same frequency and a fixed phase relationship i e they are phase frequency locked but with a non zero phase difference When phase buildout is enabled the DSPLL absorbs the phase difference between the two input clocks during a clock switch When phase buildout is disabled the phase difference between the two inputs is propagated to the output at a rate dete...

Page 25: ...quency transients and overshoot when switching between clocks that are not the same frequency CBPro defaults to ramped clock switching The same ramp rate settings are used for both exit from holdover and clock switching For more information on ramped exit from holdover including the ramp rate see 4 7 Holdover Mode 5 2 4 Glitchless Input Switching The DSPLL has the ability to switch between two inp...

Page 26: ...ecification of up to 1 5 ns for a maximum phase transient when the switch occurs during a gap in either input clocks Figure 8 shows a 100 MHz clock with one cycle removed every 10 cycles which results in a 90 MHz periodic non gapped output clock Figure 8 Generating an Averaged Non Gapped Output Frequency from a Gapped Input 5 3 Fault Monitoring The four clocks IN0 IN1 IN2 IN3 FB_IN are monitored f...

Page 27: ...n correctly The table below lists the loss of signal status indicators and fault monitoring control registers Table 14 Loss of Signal Status Monitoring and Control Registers Register Name Hex Address Bit Field Function LOS 0x000D 3 0 LOS status monitor for IN3 bit3 IN2 bit2 IN1 bit1 IN0 bit0 indicates if a valid clock is detected A set bit indicates the input is LOS SYSINCAL 0x000C 0 Asserted when...

Page 28: ...ure boundary An example is shown in the figure below In this case the OOF monitor is configured with a valid frequency range of 6 ppm and with 2 ppm of hysteresis An option to use one of the input pins IN0 IN3 as the 0 ppm OOF reference instead of the XAXB pins is available These options are all register configurable Figure 12 Example of Precise OOF Monitor Assertion and De assertion Triggers LOS_...

Page 29: ...l assert the LOL 3 De assert to clear the LOL a User sets the threshold in ppm in CBPro Table 15 Out of Frequency Status Monitoring and Control Registers Register Name Hex Address Bit Field Function OOF 0x000D 7 4 OOF status monitor for IN3 IN2 IN1 IN0 Indicates if a valid clock is detected or if a OOF condition is detected OOF_FLG 0x0012 7 4 OOF status monitor sticky bits for IN3 IN2 IN1 IN0 Stic...

Page 30: ...revent chattering of LOL status An example configuration of the LOL set and clear thresholds is shown in Figure 14 Figure 14 LOL Set and Clear Thresholds Table 16 Loss of Lock Status Monitor and Control Registers Register Name Hex Address Bit Field Function LOL 0x000E 1 Status bit that indicates if the DSPLL is locked to an input clock LOL_FLG 0x0013 1 Sticky bits for LOL register Writing 0 to a s...

Page 31: ... timer sets the delay value for the LOL clear delay timer Set by CBPro FASTLOCK_EXTEND_EN 0x00E5 5 Enables FASTLOCK_EXTEND FASTLOCK_EXTEND 0x00ED 4 0 0x00EC 7 0 0x00EB 7 0 0x00EA 7 0 Set by CBPro to minimize phase transients when switching the PLL bandwidth FASTLOCK_EXTEND_SCL 0x0294 7 4 Set by CBPro LOL_SLW_VALWIN_SELX 0x0296 1 Set by CBPro FASTLOCK_DLY_ONSW_EN 0x0297 1 Set by CBPro FASTLOCK_DLY_...

Page 32: ...high and its corresponding alarm bit is low the _FLG bit can be cleared During run time the source of an interrupt can be determined by reading the _FLG register values and logically ANDing them with the corresponding _MSK register bits after inverting the _MSK bit values If the result is a logic one then the _FLG bit will cause an interrupt For example if LOS_FLG 0 is high and LOS_INTR_MSK 0 is l...

Page 33: ... crosspoint switch allows any of the output drivers to connect with any of the MultiSynths as shown in Figure 16 The crosspoint configuration is programmable and can be stored in NVM so that the desired output configuration is ready at power up Any MultiSynth output can connect to multiple output drivers Figure 16 MultiSynth to Output Driver Crosspoint OUT2 VDDO2 OUT2 VDDO3 VDDO0 OUT0 OUT0 R2 OUT3...

Page 34: ...345 Si5344 Si5342 OUT0_MUX_SEL 0x010B 2 0 0x0115 2 0 0x0115 2 0 Connects the output drivers to one of the N dividers Selections are N0 N1 N2 N3 N4 for each output divider OUT1_MUX_SEL 0x0110 2 0 0x011A 2 0 0x011A 2 0 OUT2_MUX_SEL 0x0115 2 0 0x0129 2 0 OUT3_MUX_SEL 0x011A 2 0 0x012E 2 0 OUT4_MUX_SEL 0x011F 2 0 OUT5_MUX_SEL 0x0124 2 0 OUT6_MUX_SEL 0x0129 2 0 OUT7_MUX_SEL 0x012E 2 0 OUT8_MUX_SEL 0x01...

Page 35: ...multiples of one another are okay and these outputs should be grouped accordingly Noting that because 155 52 x 4 622 08 and 156 25 x 4 625 it is okay to place these frequency values close to one another 3 Unused outputs can be used to separate clock outputs that might otherwise interfere with one another In this case see OUT3 and OUT7 If some outputs have tight jitter requirements while others are...

Page 36: ...outputs can be configured as LVCMOS 3 3 2 5 or 1 8 V drivers providing up to 20 single ended outputs or any combination of differential and single ended outputs Note also that CMOS output can create much more crosstalk than differential outputs so extra care must be taken in their pin replacement so that other clocks that need the lowest jitter are not on nearby pins See AN862 Optimizing Si534x Ji...

Page 37: ... 17 are supported in this mode Differential High Swing Mode When an output driver is configured in high swing mode its output swing is configurable as one of 7 settings ranging from 400 mVpp_se to 1600 mVpp_se in increments of 200 mV The output driver is in high impedance mode and supports standard 50 PCB traces Any of the terminations shown in Figure 17 are supported The use of High Swing mode wi...

Page 38: ...Sets the voltage swing for the differ ential output drivers for both normal and high swing modes OUT1_ AMPL 0x010F 6 4 0x0119 6 4 0x0119 6 4 OUT2_ AMPL 0x0114 6 4 0x0128 6 4 OUT3_ AMPL 0x0119 6 4 0x012D 6 4 OUT4_ AMPL 0x011E 6 4 OUT5_ AMPL 0x0123 6 4 OUT6_ AMPL 0x0128 6 4 OUT7_ AMPL 0x012D 6 4 OUT8_ AMPL 0x0132 6 4 OUT9_ AMPL 0x013C 6 4 Table 21 Differential Output Common Mode Voltage Control Regi...

Page 39: ... selected output impedance to the trace impedance There are three programmable output impedance selections for each VDDO option as shown in Table 22 The value for the OUTx_CMOS_DRIVE bits are given Table 22 Output Impedance and Drive Strength Selections VDDO OUTx_CMOS_DRV Source Impedance Rs Drive Strength Iol Ioh 3 3 V 0x01 38 10 mA 0x02 30 12 mA 0x03 22 17 mA 2 5 V 0x01 43 6 mA 0x02 35 8 mA 0x03...

Page 40: ...he VDDO pin to properly determine the correct output voltage Table 23 LVCMOS Drive Strength Control Registers Register Name Hex Address Bit Field Function Si5345 Si5344 Si5342 OUT0_CMOS_DRV 0x0109 7 6 0x0113 7 6 0x0113 7 6 LVCMOS output impedance OUT1_ CMOS_DRV 0x010E 7 6 0x0118 7 6 0x0118 7 6 OUT2_ CMOS_DRV 0x0113 7 6 0x0127 7 6 OUT3_ CMOS_DRV 0x0118 7 6 0x012C 7 6 OUT4_ CMOS_DRV 0x011D 7 6 OUT5_...

Page 41: ...Register Name Hex Address Bit Field Function Si5345 Si5344 Si5342 OUT0_INV 0x010B 7 6 0x0115 7 6 0x0115 7 6 Controls the output polarity of the OUTx and OUTx pins when in LVCMOS mode Selections are below in Table 25 OUT1_ INV 0x0110 7 6 0x011A 7 6 0x011A 7 6 OUT2_ INV 0x0115 7 6 0x0129 7 6 OUT3_ INV 0x011A 7 6 0x012E 7 6 OUT4_ INV 0x011F 7 6 OUT5_ INV 0x0124 7 6 OUT6_ INV 0x0129 7 6 OUT7_ INV 0x01...

Page 42: ...t driver is disabled the plus output will be low and the minus output will be high The Format Amplitude and Common Mode settings for the various supported standards are shown in Table 26 The output differential driver can produce a wide range of output amplitudes that includes CML amplitudes See Appendix A for additional information Table 26 Settings for LVDS LVPECL and HCSL OUTx_FORMAT Standard V...

Page 43: ... Bit Field Function Si5345 Si5344 Si5342 OUTALL_ DISABLE_LOW 0x0102 0 0x0102 0 0x0102 0 Disables all output drivers 0 all out puts disabled 1 all outputs enabled This bit essentially has the same function as the OE pin if the OE pin is held low If the OE pin is held high then all outputs will be disabled regardless of the state of this register bit OUT0_OE 0x0108 1 0x0112 1 0x0112 1 Allows enablin...

Page 44: ...river when disabled Selectable as Disable logic low Disable logic high OUT1_ DIS_STATE 0x010E 5 4 0x0118 5 4 0x0118 5 4 OUT2_ DIS_STATE 0x0113 5 4 0x0127 5 4 OUT3_ DIS_STATE 0x0118 5 4 0x012C 5 4 OUT4_ DIS_STATE 0x011D 5 4 OUT5_ DIS_STATE 0x0122 5 4 OUT6_ DIS_STATE 0x0127 5 4 OUT7_ DIS_STATE 0x012C 5 4 OUT8_ DIS_STATE 0x0131 5 4 OUT9_ DIS_STATE 0x013B 5 4 Table 29 Synchronous Disable Control Regis...

Page 45: ... mismatch compensation or for applications that require quadrature clock generation The resolution of the phase adjustment is approximately 1 ps per step definable in a range of 8 32 ns Phase adjustments are register configurable An example of generating two frequencies with unique configurable path delays is shown in Figure 20 Figure 20 Example of Independently Configurable Path Delays N0 t0 N1 t...

Page 46: ...Si5342 N0_DELAY 0x0359 7 0 0x035A 7 0 0x0359 7 0 0x035A 7 0 0x0359 7 0 0x035A 7 0 Configures path delay values for each N divider Each 16 bit number is 2s comple ment The output delay is Nx_DELAY 256 x Fvco where Fvco is the frequency of the VCO in Hz and the delay is in seconds Register values determined using Clock Builder Pro N1_DELAY 0x035B 7 0 0x035C 7 0 0x035B 7 0 0x035C 7 0 0x035B 7 0 0x035...

Page 47: ...ll help to minimize the input to output delay The OUT9 and FB_IN pins are recommended for the external feedback connection in the Si5345 OUT3 and FB_IN pins are recommended for the external feedback in the Si5344 OUT1 or OUT2 are recommended with FB_IN in the Si5342 The FB_IN input pins must be terminated and ac coupled when zero delay mode is used A differential external feedback path connection ...

Page 48: ...SW_EN 0x0487 4 0 Automatic switching disabled for zero delay mode 1 Automatic input switching enabled and input clock selection governed by automatic input switching engine Table 33 Input Clock Selection in Zero Delay Mode ZDM_AUTO_SW_EN ZDM_EN IN_SEL_REGCTRL Input Clock Selection Governed by 0 0 0 IN_SEL 1 0 Pins 0 0 1 IN_SEL Register 0 1 0 IN_SEL 1 0 Pins 0 1 0 ZDM_IN_SEL Register 1 X X Input cl...

Page 49: ...that is used to change the value of the Nx_NUM word Whenever an FINC or FDEC is asserted the Nx_FSTEPW will automatically add or subtract from the Nx_NUM word so that the output frequency will respectively increment FINC or decrement FDEC Each of the N dividers can be independently stepped up or down in numerical predefined steps with a maximum resolution that varies from 0 05 ppb to a 0 004 ppb d...

Page 50: ... Si5345 Multi Synth Nn0 Nd0 t0 0x0339 N1_FSTEP_MASK Frequency Step Word 0x0341 0x0346 Multi Synth Nn1 Nd1 t1 FDEC FINC 0x001D FDEC FINC 0x0339 N2_FSTEP_MASK Frequency Step Word 0x0347 0x034C Multi Synth Nn2 Nd2 t2 0x0339 N3_FSTEP_MASK Frequency Step Word 0x034D 0x0352 Multi Synth Nn3 Nd3 t3 Frequency Step Word 0x0339 N4_FSTEP_MASK 0x0353 0x0358 Multi Synth Nn4 Nd4 t4 ...

Page 51: ...vider denominator contact Silicon Labs at https www silabs com support pages contacttechnicalsupport aspx for support Table 34 Frequency Increment Decrement Control Registers Register Name Hex Address Bit Field Function Si5345 Si5344 Si5342 FINC 0x001D 0 0x001D 0 0x001D 0 Asserting this bit will increase the DSPLL output frequency by the frequency step word FDEC 0x001D 1 0x001D 1 0x001D 1 Assertin...

Page 52: ...supply voltage is used for the serial port control pins and status pins voltage references See the register map description of this bit for additional details SPI_3WIRE 0x002B 3 The SPI_3WIRE configuration bit selects the option of 4 wire or 3 wire SPI communication By default the SPI_3WIRE configuration bit is set to the 4 wire option In this mode the Si5345 44 42 will accept write commands from ...

Page 53: ...his also allows four choices in the I2C address for systems that may have other overlapping addresses for other I2C devices Figure 24 I2 C Configuration The 7 bit slave device address of the Si5345 44 42 consists of a 5 bit fixed address plus 2 pins which are selectable for the last two bits as shown in Figure 25 Figure 25 7 bit I2C Slave Address Bit Configuration Data is transferred MSB first in ...

Page 54: ...te A Acknowledge SDA LOW N Not Acknowledge SDA HIGH S START condition P STOP condition Write Operation Single Byte S 0 A Reg Addr 7 0 Slv Addr 6 0 A Data 7 0 P A Write Operation Burst Auto Address Increment Reg Addr 1 S 0 A Reg Addr 7 0 Slv Addr 6 0 A Data 7 0 A Data 7 0 P A Host Si5345 44 42 Host Si5345 44 42 1 Read 0 Write A Acknowledge SDA LOW N Not Acknowledge SDA HIGH S START condition P STOP...

Page 55: ... Silicon Labs SMBUS_TIMEOUT_FLG 0x0011 5 1 if there is a SMBus timeout error Contact Silicon Labs Table 37 SPI Command Format Instruction Ist Byte1 2nd Byte 3rd Byte Nth Byte2 3 Set Address 000x xxxx 8 bit Address Write Data 010x xxxx 8 bit Data Read Data 100x xxxx 8 bit Data Write Data Address Increment 011x xxxx 8 bit Data Read Data Address Increment 101x xxxx 8 bit Data Burst Write Data 1110 00...

Page 56: ...g the write commands This demonstrates that the Write Burst Data command is the most efficient method for writing data to sequential address locations Figure 30 provides a similar comparison for reading data with the read commands Note that there is no burst read only read increment Figure 29 Example Writing Three Data Bytes Using the Write Commands Set Address and Write Data Address Increment Bur...

Page 57: ... Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Set Addr Addr 7 0 Read Data Data 7 0 Read Data Addr Inc Data 7 0 Read Data Addr Inc Data 7 0 Set Addr Addr 7 0 Read Data Addr Inc Data 7 0 Si5345 44 42 Host Si5345 44 42 Host Set Address Instruction Base Address CS SCLK SDI SDO SDIO 4 Wire 3 Wire Set Address Command 2 SCLK Periods Previous Command Next Command 2 0 SCLK Periods 1 0 0 1 2 3 4 5 6 7 0 1 ...

Page 58: ...ruction Data byte base address 1 CS SCLK SDI SDO SDIO 4 Wire 3 Wire Write Data or Write Data Address Increment Command 2 SCLK Periods Previous Command Next Command 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 6 7 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 6 7 Si5345 44 42 Host Si5345 44 42 Host Don t Care High Impedance 2 0 SCLK Periods ...

Page 59: ... 2 3 4 5 6 7 Si5345 44 42 Host Si5345 44 42 Host Don t Care High Impedance Read Data instruction Read byte base address 1 2 0 SCLK Periods 2 0 SCLK Periods Burst Write Instruction Base address CS SCLK SDO SDIO 4 Wire nth data byte base address n 3 Wire Burst Data Write Command Previous Command SDI 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 0 1...

Page 60: ...tems using the Si5345 44 42 a field programmer is available The ClockBuilder Pro Field Programmer supports both in system programming for devices already mounted on a PCB as well as in socket programming of Si5345 44 42 sample devices Refer to www silabs com CBProgrammer for information about this kit ...

Page 61: ...ed method of connecting a clipped sine wave TCXO to the Si5345 44 42 Because the Si5345 44 42 provides dc bias at the XA and XB pins the 800 mV peak peak swing can be input directly into the XA interface of the Si5345 44 42 once it has been ac coupled Because the signal is single ended the XB input is ac coupled to ground Note that when using a single ended XO the XO signal must be driven on XA If...

Page 62: ...abled when an external clock source is selected A PXAXB prescale divider is available to accommodate external clock frequencies higher than 125 MHz as shown in Table 38 For best jitter performance keep the REFCLK frequency above 40 MHz For applications with loop BW values less than 10 Hz that require low wander output clocks using a TCXO as the XAXB reference source should be considered to avoid t...

Page 63: ...endors can also supply crystals that meet the specs in Figures 38 and 39 Table 38 Recommended Crystals Supplier Part Number Frequency Initial Tolerance in ppm Accuracy over 40 C to 85 C in ppm C0 Max pF ESR Max W CL pF Tested over Temp for Activity Dips Drive Level µW Case Size mm x mm Connor Winfield CS 043 48 MHz 15 25 2 0 20 8 No 200 3 2 x 2 5 Connor Winfield CS 044 54 MHz 15 25 2 0 20 8 No 200...

Page 64: ... No 200 3 2 x 2 5 NDK NX3225SA 54 000M CS07551 54 MHz 20 30 1 8 23 8 No 200 3 2 x 2 5 Siward XTL571500 S315 006 54 MHz 50 50 2 0 20 8 No 200 3 2 x 2 5 Siward XTL571500 S315 007 54 MHz 50 50 2 0 20 8 No 200 2 5 x 2 0 Taitien S0242 X 001 3 54 MHz 20 20 2 0 23 8 No 200 3 2 x 2 5 Taitien S0242 X 002 3 48 MHz 20 20 2 0 23 8 No 200 3 2 x 2 5 TXC 7M48070012 48 MHz 10 15 2 0 22 8 No 200 3 2 x 2 5 TXC 7M54...

Page 65: ...Hz Crystal Figure 39 Maximum ESR vs C0 for 48 54 MHz Crystal 30 40 50 60 70 80 90 100 0 0 5 1 1 5 2 2 5 3 3 5 ESR ohms C0 pf Maximum ESR vs C0 for 25 MHz Crystal 15 17 19 21 23 25 27 29 31 0 0 5 1 1 5 2 2 5 3 3 5 ESR ohms C0 pf Maximum ESR vs C0 for 48Ͳ54 MHz Crystal ...

Page 66: ...n the XA XB pins Set this bit to use the external REFCLK Table 39 Recommended Oscillator Suppliers Supplier Part Number TCXO OCXO Frequency Case Size mm x mm x mm Epson TG 5500CA 68N 49 1520000MHz TCXO 49 152 MHz 5x7 Epson TG 5500 67N 40 00000MHz TCXO 40 MHz 5x7 Rakon 513872 40MHz RTX7050A HCMOS TCXO 40 000 5x7 NDK NT7050BB 40 000M ENA4199B TCXO 40 000 5x7 Vectron VT 803 EAH 2870 40M0000 TCXO 40 0...

Page 67: ...the input values for the two bit field and the corresponding divider values Table 42 Pre Scale Divide Ratio Register Register Name Hex Address Bit Field Function PXAXB 0206 1 0 This is a two bit value that sets the divider value Table 43 Pre Scale Divide Values Value Decimal PXAXB Divider Value 0 1 1 2 2 4 3 8 ...

Page 68: ... of the Si5345 device mounted on the top PCB layer This particular layout was designed to implement either a crystal or an external oscillator as the XAXB reference The crystal oscillator area is outlined with the white box around it In this case the top layer is flooded with ground Note that this layout has a resistor in series with each pin of the crystal In typical applications these resistors ...

Page 69: ...i5345 should have all layers underneath the ground shield removed Figure 40 64 pin Si5345 Crystal Layout Recommendations Top Layer Layer 1 Figure 41 Zoom View Crystal Shield Layer Below the Top Layer Layer 2 Figure 41 shows the layer that implements the shield underneath the crystal The shield extends underneath the entire crystal and the X1 and X2 pins This layer also has the clock input pins The...

Page 70: ...und plane and shows a void underneath the crystal shield Figure 43 is a power plane and shows the clock output power supply traces The void underneath the crystal shield is continued Figure 42 Crystal Ground Plane Layer 3 Figure 43 Power Plane Layer 4 ...

Page 71: ...e 44 shows layer 5 which is the power plane with the power routed to the clock output power pins Figure 44 Layer 5 Power Routing on Power Plane Layer 5 Figure 45 is another ground plane similar to layer 3 Figure 45 Ground Plane Layer 6 ...

Page 72: ...round flooded bottom layer There is a ground flooding between the clock output pairs to avoid crosstalk There should be a line of vias through the ground flood on either side of the output clocks to ensure that the ground flood immediately next to the differential pairs has a low inductance path to the ground plane on layers 3 and 6 Figure 46 Output Clock Layer Layer 7 Figure 47 Bottom Layer Groun...

Page 73: ...is a ground shield above below and on all sides for protection Output clocks should always be routed on an internal layer with ground reference planes directly above and below The plane that has the routing for the output clocks should have ground flooded near the clock traces to further isolate the clocks from noise and other signals 12 2 1 Si5342 44 Applications without a Crystal If the applicat...

Page 74: ...l and the X1 and X2 pins There should be no less than 12 vias to connect the X1 and X2 planes on layers 1 and 2 These vias are not shown in any other figures All traces with signals that are not static must be kept well away from the crystal and the X1 and X2 plane Figure 49 Crystal Shield Layer 2 Figure 50 is the ground plane and shows a void underneath the crystal shield Figure 50 Ground Plane L...

Page 75: ... underneath the crystal shield is continued Figure 51 Power Plane and Clock Output Power Supply Traces Layer 4 Figure 52 shows layer 5 and the clock input traces Similar to the clock output traces they are routed to an inner layer and surrounded by ground to avoid crosstalk Figure 52 Clock Input Traces Layer 5 ...

Page 76: ...an be placed under the XTAL Ground shield X1 X2 as long as the PCB ground is at least 0 05 inches below it Figure 53 Low Speed CMOS Control and Status Signal Layer 6 Bottom Layer For any high speed low jitter application the clock signal runs should be impedance controlled to 100 differential or 50 single ended Differential signaling is preferred because of its increased immunity to common mode no...

Page 77: ...0x001E 0 0x001E 0 This bit allows the device to be powered down The serial interface remains pow ered OUT0_PDN 0x0108 0 0x0112 0 0x0112 0 Powers down all unused clock outputs OUT1_PDN 0x010D 0 0x0117 0 0x0117 0 OUT2_PDN 0x0112 0 0x0126 0 OUT3_PDN 0x0117 0 0x012B 0 OUT4_PDN 0x011C 0 OUT5_PDN 0x0121 0 OUT6_PDN 0x0126 0 OUT7_PDN 0x012B 0 OUT8_PDN 0x0130 0 OUT9_PDN 0x0135 0 OUT_PDN_ALL 0x0145 0 0x0145...

Page 78: ...not possible to properly sequence the power supplies then the output clocks can be aligned by asserting the SOFT_RST 0x001C 0 or Hard Reset 0x001E 1 register bits or driving the RSTB pin Note that using a hard reset will reload the register with the contents of the NVM and any unsaved changes will be lost Note One may observe that when powering up the VDD 1 8 V rail first that the VDDA 3 3 V rail ...

Page 79: ...tomers must initiate custom OPN creation using the ClockBuilder Pro software Many customers prefer to order devices which are factory preprogrammed for a particular application that includes specifying the XAXB reference frequency type the clock input frequencies the clock output frequencies as well as the other options such as automatic clock selection loop BW etc The ClockBuilder software is req...

Page 80: ...alues of the regiister map settings by accessing the part number lookup utility at www silabs com products clocksoscillators clock generator Pages clockbuilder lookup aspx Register map settings values are listed in the datasheet addendum which can also be accessed by using the link above The register maps are broken out for the Si5345 Si5344 and Si5342 separately R Read Only R W Read Write S Self ...

Page 81: ...eg Address Bit Field Type Name Description 0x0000 3 0 R DIE_REV 4 bit Die Revision Number Register 0x0001 Page Reg Address Bit Field Type Name Description 0x0001 7 0 R W PAGE Selects one of 256 possible pages Register 0x0002 0x0003 Base Part Number Reg Address Bit Field Type Name Value Description 0x0002 7 0 R PN_BASE 0x45 Four digit base part number one nibble per digit Example Si5345A A GM The b...

Page 82: ...7 0 R DEVICE_REV One ASCII character indicating the device revision level 0 A 1 B etc Example Si5345C A12345 GM the device revision is A and stored as 0 Register 0x0006 0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 3 0 R W TOOL_VERSION 3 0 Special 0x0006 7 4 R W TOOL_VERSION 7 4 Revision 0x0007 7 0 R W TOOL_VERSION 15 8 Minor 7 0 0x0008 0 R W TOOL_VERSION 15 8 Minor 8 0x00...

Page 83: ...ss Reg Address Bit Field Type Setting Name Description 0x000B 6 2 R W I2C_ADDR The upper 5 bits of the 7 bit I2 C address The lower 2 bits are controlled by the A1 and A0 pins Register 0x000B I2 C Address Reg Address Bit Field Type Setting Name Description 0x000B 6 2 R W I2C_ADDR The upper 5 bits of the 7 bit I2 C address The lower 2 bits are controlled by the A1 and A0 pins Register 0x000C Intern...

Page 84: ...he DSPLL is in holdover or free run Register 0x000F Calibration Status Reg Address Bit Field Type Name Description 0x000F 5 R CAL_PLL 1 if the DSPLL internal calibration is busy Register 0x0011 Internal Error Flags Reg Address Bit Field Type Name Description 0x0011 0 R SYSINCAL_FLG Sticky version of SYSINCAL Write a 0 to this bit to clear 0x0011 1 R LOSXAXB_FLG Sticky version of LOSXAXB Write a 0 ...

Page 85: ...er 0x0011 If a mask bit is set the alarm will be blocked from causing an interrupt Note Bit 1 corresponds to XAXB LOS from asserting the interrupt INTR pin Register 0x0013 Sticky Holdover and LOL Flags Reg Address Bit Field Type Name Description 0x0013 1 R W LOL_FLG 1 if the DSPLL was unlocked 0x0013 5 R W HOLD_FLG 1 if the DSPLL was in holdover or free run Register 0x0014 Sticky PLL In Calibratio...

Page 86: ...These bits are of type S which is self clearing Register 0x0018 OOF and LOS Masks Reg Address Bit Field Type Name Description 0x0018 3 0 R W LOS_INTR_MSK 1 to mask the clock input LOS flag 0x0018 7 4 R W OOF_INTR_MSK 1 to mask the clock input OOF flag Register 0x0019 Holdover and LOL Masks Reg Address Bit Field Type Name Description 0x0019 1 R W LOL_INTR_MSK 1 to mask the clock input LOL flag 0x00...

Page 87: ...gister 0x001E Sync Power Down and Hard Reset Reg Address Bit Field Type Name Description 0x001E 0 R W PDN 1 to put the device into low power mode 0x001E 1 S HARD_RST 1 causes hard reset The same as power up except that the serial port access is not held at reset This does not self clear so after setting the bit it must be cleared 0 No reset 0x001E 2 S SYNC Logically equivalent to asserting the SYN...

Page 88: ... 0x002C 3 0 R W LOS_EN 1 to enable LOS for a clock input 0 for disable 0x002C 4 R W LOSXAXB_DIS Enable LOS detection on the XAXB inputs 0 Enable LOS Detection default 1 Disable LOS Detection Register 0x002D Loss of Signal Re Qualification Value Reg Address Bit Field Type Name Description 0x002D 1 0 R W LOS0_VAL_TIME Clock Input 0 0 for 2 msec 1 for 100 msec 2 for 200 msec 3 for one second 0x002D 3...

Page 89: ...it Field Type Name Description 0x0030 7 0 R W LOS1_TRG_THR 16 bit Threshold Value 0x0031 15 8 R W LOS1_TRG_THR Register 0x0032 0x0033 LOS2 Trigger Threshold Reg Address Bit Field Type Name Description 0x0032 7 0 R W LOS2_TRG_THR 16 bit Threshold Value 0x0033 15 8 R W LOS2_TRG_THR Register 0x0034 0x0035 LOS3 Trigger Threshold Reg Address Bit Field Type Name Description 0x0034 7 0 R W LOS3_TRG_THR 1...

Page 90: ...OF_EN 6 Input 3 corresponds to OOF_EN 3 FAST_OOF_EN 7 Register 0x003A 0x003B LOS2 Clear Threshold Reg Address Bit Field Type Name Description 0x003A 7 0 R W LOS2_CLR_THR 16 bit Threshold Value 0x003B 15 8 R W LOS2_CLR_THR Register 0x003C 0x003D LOS3 Clear Threshold Reg Address Bit Field Type Name Description 0x003C 7 0 R W LOS3_CLR_THR 16 bit Threshold Value 0x003D 15 8 R W LOS3_CLR_THR Register 0...

Page 91: ... in steps of 1 16 ppm 0x0047 7 0 R W OOF1_SET_THR OOF Set threshold Range is up to 500 ppm in steps of 1 16 ppm 0x0048 7 0 R W OOF2_SET_THR OOF Set threshold Range is up to 500 ppm in steps of 1 16 ppm 0x0049 7 0 R W OOF3_SET_THR OOF Set threshold Range is up to 500 ppm in steps of 1 16 ppm Register 0x004A 0x004D Out of Frequency Clear Threshold Reg Address Bit Field Type Name Description 0x004A 7...

Page 92: ...ro 0x004E 6 4 R W OOF1_DETWIN_SEL 0x004F 2 0 R W OOF2_DETWIN_SEL 0x004F 6 4 R W OOF3_DETWIN_SEL Register 0x0051 0x0054 Fast Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0051 3 0 R W FAST_OOF0_SET_THR 1 value x 1000 ppm 0x0052 3 0 R W FAST_OOF1_SET_THR 1 value x 1000 ppm 0x0053 3 0 R W FAST_OOF2_SET_THR 1 value x 1000 ppm 0x0054 3 0 R W FAST_OOF3_SET_THR 1 value x 10...

Page 93: ...W OOF1_RATIO_REF Register 0x0062 0x0065 OOF2 Ratio for Reference Reg Address Bit Field Type Name Description 0x0062 7 0 R W OOF2_RATIO_REF Values calculated by CBPro 0x0063 15 8 R W OOF2_RATIO_REF 0x0064 23 16 R W OOF2_RATIO_REF 0x0065 25 24 R W OOF2_RATIO_REF Register 0x0066 0x0069 OOF3 Ratio for Reference Reg Address Bit Field Type Name Description 0x0066 7 0 R W OOF3_RATIO_REF Values calculated...

Page 94: ...ield Type Name Description 0x0096 7 4 R W LOL_FST_SET_THR_SEL Values calculated by CBPro Register 0x0098 Fast LOL Clear Threshold Reg Address Bit Field Type Name Description 0x0098 7 4 R W LOL_FST_CLR_THR_SEL Values calculated by CBPro Register 0x009A LOL Enable Reg Address Bit Field Type Name Description 0x009A 1 R W LOL_SLOW_EN_PLL 1 to enable LOL 0 to disable LOL Register 0x009B Slow LOL Detect...

Page 95: ...s these values 0 0 1 ppm 1 0 3 ppm 2 1 ppm 3 3 ppm 4 10 ppm 5 30 ppm 6 100 ppm 7 300 ppm 8 1000 ppm 9 3000 ppm 10 10000 ppm Register 0x009E LOL Set Threshold Reg Address Bit Field Type Name Description 0x009E 7 4 R W LOL_SET_THR Configures the loss of lock set thresholds Select able as 0 1 0 3 1 3 10 30 100 300 1000 3000 10000 Values are in ppm Register 0x00A0 LOL Clear Threshold Reg Address Bit F...

Page 96: ...it value Sets the clear timer for LOL CBPro sets this value 0x00AA 15 8 R W LOL_CLR_DLY 0x00AB 23 16 R W LOL_CLR_DLY 0x00AC 28 24 R W LOL_CLR_DLY Register 0x00E2 Reg Address Bit Field Type Name Description 0x00E2 7 0 R ACTIVE_NVM_BANK Read only field indicating number of user bank writes carried out so far Value Description 0 zero 3 one 15 two 63 three Register 0x00E3 Reg Address Bit Field Type Se...

Page 97: ...r 0 Do not extend Fastlock period 1 Extend Fastlock period default Register 0x00EA 0x00ED LOL Detection Value Reg Address Bit Field Type Name Description 0x00EA 7 0 R W FASTLOCK_EXTEND 29 bit value Set by CBPro to minimize the phase transients when switching the PLL bandwidth See FASTLOCK_EXTEND_SCL 0x00EB 15 8 R W FASTLOCK_EXTEND 0x00EC 23 16 R W FASTLOCK_EXTEND 0x00ED 28 24 R W FASTLOCK_EXTEND ...

Page 98: ...e output 1 to enable the output 0x0108 2 R W OUT0_RDIV_FORCE2 0 R0 divider value is set by R0_REG 1 R0 divider value is forced into divide by 2 Register 0x0109 Output 0 Format Reg Address Bit Field Type Name Description 0x0109 2 0 R W OUT0_FORMAT 0 Reserved 1 swing mode normal swing differential 2 swing mode high swing differential 3 rail to rail swing mode differential 4 LVCMOS single ended 5 7 r...

Page 99: ...0_CM This field only applies when OUT0_FORMAT 1 or 2 See Table 26 Settings for LVDS LVPECL and HCSL on page 42 and Appendix A Setting the Dif ferential Output Driver to Non Standard Amplitudes on page 219 for details of the settings 0x010A 6 4 R W OUT0_AMPL This field only applies when OUT0_FORMAT 1 2 or 3 See Table 12 Hitless Switching Enable Bit on page 24 and Appendix A Setting the Differential...

Page 100: ...10B 0x011C Clock Output Driver 4 Config 0x0108 0x011D Clock Output Driver 4 Format Sync 0x010A 0x011E Clock Output Driver 4 Ampl CM 0x0105 0x011F OUT4_MUX_SEL OUT4_VDD_SEL_EN OUT4_VDD_SEL OUT4_INV 0x010B 0x0121 Clock Output Driver 5 Config 0x0108 0x0122 Clock Output Driver 5 Format Sync 0x0109 0x0123 Clock Output Driver 5 Ampl CM 0x010A 0x0124 OUT5_MUX_SEL OUT5_VDD_SEL_EN OUT5_VDD_SEL OUT5_INV 0x0...

Page 101: ...tput Disable Mask for LOS XAXB Reg Address Bit Field Type Setting Name Description 0x0141 1 R W OUT_DIS_MSK 0x0141 5 R W OUT_DIS_LOL_MSK 0x0141 6 R W OUT_DIS_MSK_LOSXAXB Determines if outputs are disabled during an LOSXAXB condition 0 All outputs disabled on LOSXAXB 1 All outputs remain enabled during LOSXAXB condition 0x0141 7 R W OUT_DIS_MSK_LOS_PFD Register 0x0142 Output Disable Loss of Lock PL...

Page 102: ...0145 Power Down All Reg Address Bit Field Type Name Description 0x0145 0 R W OUT_PDN_ALL 0 no effect 1 all drivers powered down Register 0x0146 0x0147 Reg Address Bit Field Type Setting Name Description 0x0146 7 0 R W DRV_RST 0x0147 11 8 R W DRV_RST ...

Page 103: ...ock sources not crystals This set of registers configures the P dividers which are located at the four input clocks seen in Figure 2 Si5342 DSPLL and Multisynth System Flow Diagram on page 11 ClockBuilder Pro calculates the correct values for the P dividers Register 0x0202 0x0205 XAXB Frequency Adjust Reg Address Bit Field Type Name Description 0x0202 7 0 R W XAXB_FREQ_OFFSET 32 bit offset adjustm...

Page 104: ...egister 0x020E 0x0211 P0 Divider Denominator Reg Address Bit Field Type Name Description 0x020E 7 0 R W P0_DEN 32 bit Integer Number 0x020F 15 8 R W P0_DEN 0x0210 23 16 R W P0_DEN 0x0211 31 24 R W P0_DEN Table 47 Registers that Follow the P0_NUM and P0_DEN Above Register Address Description Size Same as Address 0x0212 0x0217 P1 Divider Numerator 48 bit Integer Number 0x0208 0x020D 0x0218 0x021B P1...

Page 105: ...le Reg Address Bit Field Type Setting Name Description 0x0232 3 0 R W P1_FRACN_MODE P1 IN1 input divider fractional mode Must be set to 0xB for proper operation 0x0232 4 R W P1_FRAC_EN P1 IN1 input divider fractional enable 0 Integer only division 1 Fractional or Integer division Register 0x0233 P2 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0233 3 0 R W P2_FRAC...

Page 106: ...x0234 3 0 R W P3_FRACN_MODE P3 IN3 input divider fractional mode Must be set to 0xB for proper operation 0x0234 4 R W P3_FRAC_EN P3 IN3 input divider fractional enable 0 Integer only division 1 Fractional or Integer division Register 0x0235 0x023A MXAXB Divider Numerator Reg Address Bit Field Type Setting Name Description 0x0235 7 0 R W MXAXB_NUM 44 bit Integer Number 0x0236 15 8 R W MXAXB_NUM 0x0...

Page 107: ...e R0_REG 1 x 2 To set R0 2 set OUT0_RDIV_FORCE2 1 and then the R0_REG value is irrelevant 0x024B 15 8 R W R0_REG 0x024C 23 16 R W R0_REG Table 48 Registers that Follow the R0_REG Register Address Description Size Same as Address 0x024D 0x024F R1_REG 24 bit Integer Number 0x024A 0x024C 0x0250 0x0252 R2_REG 24 bit Integer Number 0x024A 0x024C 0x0253 0x0255 R3_REG 24 bit Integer Number 0x024A 0x024C ...

Page 108: ...racters A user will normally include a config uration ID revision ID For example ULT 1A with null character padding sets DESIGN_ID0 0x55 DESIGN_ID1 0x4C DESIGN_ID2 0x54 DESIGN_ID3 0x2E DESIGN_ID4 0x31 DESIGN_ID5 0x41 DESIGN_ID6 0x 00 DESIGN_ID7 0x00 0x026C 15 8 R W DESIGN_ID1 0x026D 23 16 R W DESIGN_ID2 0x026E 31 24 R W DESIGN_ID3 0x026F 39 32 R W DESIGN_ID4 0x0270 47 40 R W DESIGN_ID5 0x0271 55 4...

Page 109: ... characteristics selected in ClockBuilder Pro Register 0x0278 0x027C OPN Identifier Reg Address Bit Field Type Name Description 0x0278 7 0 R W OPN_ID0 OPN unique identifier ASCII encoded For example with OPN 5380C A12345 GM 12345 is the OPN unique identifier which sets OPN_ID0 0x31 OPN_ID1 0x32 OPN_ID2 0x33 OPN_ID3 0x34 OPN_ID4 0x35 0x0279 15 8 R W OPN_ID1 0x027A 23 16 R W OPN_ID2 0x027B 31 24 R W...

Page 110: ...Field Type Name Description 0x0299 1 R W FASTLOCK_DLY_ONLOL_EN Set by CBPro Register 0x029D Fastlock Delay on LOL Reg Address Bit Field Type Name Description 0x029D 1 R W FASTLOCK_DLY_ONLOL Set by CBPro Register 0x02A9 0x02AB Fastlock Delay on Input Switch Reg Address Bit Field Type Name Description 0x02A9 7 0 R W FASTLOCK_DLY_ONSW 20 bit value Set by CBPro 0x02AA 15 8 R W FASTLOCK_DLY_ONSW 0x02AB...

Page 111: ... new values to the divider then set the update bit Register 0x0302 0x0307 N0 Numerator Reg Address Bit Field Type Name Description 0x0302 7 0 R W N0_NUM 48 bit Integer Number 0x0303 15 8 R W N0_NUM 0x0304 23 16 R W N0_NUM 0x0305 31 24 R W N0_NUM 0x0306 39 32 R W N0_NUM 0x0307 43 40 R W N0_NUM Register 0x0308 0x030C N0 Denominator Reg Address Bit Field Type Name Description 0x0308 7 0 R W N0_DEN 32...

Page 112: ...umerator 44 bit Integer Number 0x0302 0x0307 0x0313 0x0316 N1 Denominator 32 bit Integer Number 0x0308 0x030B 0x0317 N1_UPDATE one bit 0x030C 0x0318 0x031D N2 Numerator 44 bit Integer Number 0x0302 0x0307 0x031E 0x0321 N2 Denominator 32 bit Integer Number 0x0308 0x030B 0x0322 N2_UPDATE one bit 0x030C 0x0323 0x0328 N3 Numerator 44 bit Integer Number 0x0302 0x0307 0x0329 0x032C N3 Denominator 32 bit...

Page 113: ...0340 N0 Frequency Step Word Reg Address Bit Field Type Name Description 0x033B 7 0 R W N0_FSTEPW 44 bit Integer Number 0x033C 15 8 R W N0_FSTEPW 0x033D 23 16 R W N0_FSTEPW 0x033E 31 24 R W N0_ FSTEPW 0x033F 39 32 R W N0_ FSTEPW 0x0340 43 40 R W N0_ FSTEPW Table 50 Registers that Follow the N0_FSTEPW Definitions Register Address Description Size Same as Address 0x0341 0x0346 N1 Frequency Step Word ...

Page 114: ...ELAY 15 0 Register 0x035D 0x035E Divider N2 Delay Control Reg Address Bit Field Type Name Description 0x035D 7 0 R W N2_DELAY 7 0 Lower byte of N2_DELAY 15 0 0x035E 15 8 R W N2_DELAY 15 8 Upper byte of N2_DELAY 15 0 Register 0x035F 0x0360 Divider N3 Delay Control Reg Address Bit Field Type Name Description 0x035F 7 0 R W N3_DELAY 7 0 Lower byte of N3_DELAY 15 0 0x0360 15 8 R W N3_DELAY 15 8 Upper ...

Page 115: ... addition the frequency of the clock selected by ZDM_IN_SEL must either be the same or have a simple integer relationship to the clock at the FB_IN pins Pin controlled clock selection is available in ZD mode see register 0x052A Register 0x0487 Zero Delay Mode Setup Reg Address Bit Field Type Name Description 0x0487 0 R W ZDM_EN 0 to disable ZD mode 1 to enable ZD mode 0x0487 2 1 R W ZDM_IN_SEL Clo...

Page 116: ... Field Type Name Description 0x0508 5 0 R W BW0_PLL PLL bandwidth parameter 0x0509 5 0 R W BW1_PLL PLL bandwidth parameter 0x050A 5 0 R W BW2_PLL PLL bandwidth parameter 0x050B 5 0 R W BW3_PLL PLL bandwidth parameter 0x050C 5 0 R W BW4_PLL PLL bandwidth parameter 0x050D 5 0 R W BW5_PLL PLL bandwidth parameter Register 0x050E 0x0514 Fast Lock Loop Bandwidth Reg Address Bit Field Type Name Descripti...

Page 117: ...5 48 R W M_NUM Register 0x051C 0x051F M Divider Denominator 32 bits Reg Address Bit Field Type Name Description 0x051C 7 0 R W M_DEN 32 bit Number 0x051E 15 8 R W M_DEN 0x051E 23 16 R W M_DEN 0x051F 31 24 R W M_DEN Register 0x0520 M Divider Update Bit Reg Address Bit Field Type Name Description 0x0520 0 R W M_UPDATE Set this bit to update the M divider Register 0x0521 DSPLL B M Divider Fractional ...

Page 118: ...tion 0x052B 0 R W FASTLOCK_AUTO_EN Applies only when FASTLOCK_MAN 0 see below 0 to disable auto fast lock when the DSPLL is out of lock 1 to enable auto fast lock 0x052B 1 R W FASTLOCK_MAN 0 for normal operation see above 1 to force fast lock Register 0x052C Holdover Exit Control Reg Address Bit Field Type Setting Name Description 0x052C 0 R W HOLD_EN Holdover enable 0 Holdover Disabled 1 Holdover...

Page 119: ... Average Length Reg Address Bit Field Type Name Description 0x052E 4 0 R W HOLD_HIST_LEN 5 bit value Register 0x052F Holdover History Delay Reg Address Bit Field Type Name Description 0x052F 4 0 R W HOLD_HIST_DELAY Register 0x0531 Reg Address Bit Field Type Setting Name Description 0x0531 4 0 R W HOLD_REF_COUNT_FRC_PLLB 5 bit value Register 0x0532 0x0534 Reg Address Bit Field Type Setting Name Des...

Page 120: ...ter 0x0537 Input Alarm Masks Reg Address Bit Field Type Name Description 0x0537 3 0 R W IN_LOS_MSK For each clock input LOS alarm 0 to use LOS in the clock selection logic 1 to mask LOS from the clock selection logic 0x0537 7 4 R W IN_OOF_MSK For each clock input OOF alarm 0 to use OOF in the clock selection logic 1 to mask OOF from the clock selection logic Register 0x0538 Clock Inputs 0 and 1 Pr...

Page 121: ...Address Bit Field Type Name Description 0x0539 2 0 R W IN2_PRIORITY The priority for clock input 2 is 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved 0x0539 6 4 R W IN3_PRIORITY The priority for clock input 3 is 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are res...

Page 122: ...rical fre quency data collected for valid holdover 0x053F 2 R O FASTLOCK_STATUS 1 PLL is in Fast Lock operation Register 0x0588 Hitless Switching Length Reg Address Bit Field Type Setting Name Description 0x0588 3 0 R W HSW_FINE_PM_LEN Set by CBPro Register 0x0589 0x058A PFD Enable Delay Reg Address Bit Field Type Setting Name Description 0x0589 7 0 R W CAP_SHORT_DELAY Set by CBPro 0x058A 12 8 R W...

Page 123: ...D_BW_SEL1 Register 0x059F Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x059F 5 0 R W HOLDEXIT_BW2 Set by CBPro to set the PLL bandwidth when exiting holdover works with HOL DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x05A0 Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x05A0 5 0 R W HOLDEXIT_BW3 Set by CBPro to set the PLL bandwidth when exiting holdove...

Page 124: ...dover works with HOL DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x05A6 Hitless Switching Control Reg Address Bit Field Type Setting Name Description 0x05A6 2 0 R W RAMP_STEP_SIZE Size of the frequency ramp steps when ramping between inputs or when exiting holdover Calculated by CBPro based on selection 0x05A6 3 R W RAMP_SWITCH_EN Ramp Switching Enable 0 Disable Ramp Switching 1 Enable Ramp Switching ...

Page 125: ...sponds to IN_SEL 0x0949 2 IN_PULSED_CMOS_EN 0x0949 6 Input 3 corresponds to IN_SEL 0x0949 3 IN_PULSED_CMOS_EN 0x0949 7 Register 0x090E XAXB Configuration Reg Address Bit Field Type Name Description 0x090E 0 R W XAXB_EXTCLK_EN 0 to use a crystal at the XAXB pins 1 to use an external clock source at the XAXB pins Register 0x0943 Control I O Voltage Select Reg Address Bit Field Type Name Description ...

Page 126: ...s Reg Address Bit Field Type Setting Name Description 0x094E 7 0 R W REFCLK_HYS_SEL Value calculated in CBPro 0x094F 3 0 R W REFCLK_HYS_SEL Register 0x095E MXAXB Fractional Mode Reg Address Bit Field Type Setting Name Description 0x094A 3 0 R W INX_TO_PFD_EN Set to 1 by CBPro Do not change ...

Page 127: ...ltisynth outputs to output driver muxes Register 0x0A04 Output Multisynth Integer Divide Mode Reg Address Bit Field Type Name Description 0x0A04 4 0 R W N_PIBYP Output Multisynth integer divide mode Bit 0 for ID0 Bit 1 for ID1 etc 0 Nx divider is fractional 1 Nx divider is integer Register 0x0A05 Output Multisynth Divider Power Down Reg Address Bit Field Type Name Description 0x0A05 4 0 R W N_PDNB...

Page 128: ...R W OOF_CLK_DIS Set to 0 for normal operation Register 0x0B48 OOF Divider Clock Disables Reg Address Bit Field Type Name Description 0x0B48 4 0 R W OOF_DIV_CLK_DIS Set to 0 for normal operation Digital OOF divider clock user disable Bits 3 0 are for IN3 2 1 0 Bit 4 is for OOF for the XAXB input Register 0x0B4A Divider Clock Disables Reg Address Bit Field Type Name Description 0x0B4A 4 0 R W N_CLK_...

Page 129: ... Address Bit Field Type Name Description 0x0001 7 0 R W PAGE Selects one of 256 possible pages Register 0x0002 0x0003 Base Part Number Reg Address Bit Field Type Name Value Description 0x0002 7 0 R PN_BASE 0x44 Four digit base part number one nibble per digit Example Si5344A A GM The base part number OPN is 5344 which is stored in this register 0x0003 15 8 R PN_BASE 0x53 Register 0x0004 Device Gra...

Page 130: ... defined operating characteristics selected in ClockBuilder Pro Register 0x0006 0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 3 0 R W TOOL_VERSION 3 0 Special 0x0006 7 4 R W TOOL_VERSION 7 4 Revision 0x0007 7 0 R W TOOL_VERSION 15 8 Minor 7 0 0x0008 0 R W TOOL_VERSION 15 8 Minor 8 0x0008 4 1 R W TOOL_VERSION 16 Major 0x0008 7 5 R W TOOL_VERSION 13 17 Tool 0 for ClockBuilde...

Page 131: ...C Internal Status Bits Reg Address Bit Field Type Name Description 0x000C 0 R SYSINCAL 1 if the device is calibrating 0x000C 1 R LOSXAXB 1 if there is no signal at the XAXB pins 0x000C 2 R 0x000C 3 R 0x000C 4 R 0x000C 5 R SMBUS_TIMEOUT 1 if there is an SMBus timeout error Register 0x000D Out of Frequency OOF and Loss of Signal LOS Alarms Reg Address Bit Field Type Name Description 0x000D 3 0 R LOS...

Page 132: ...g 0 to bit 5 Register 0x0011 Sticky versions of Internal Status Bits Reg Address Bit Field Type Name Description 0x0011 0 R SYSINCAL_FLG Sticky version of SYSINCAL 0x0011 1 R LOSXAXB_FLG Sticky version of LOSXAXB 0x0011 2 R 0x0011 3 R 0x0011 4 R 0x0011 5 R SMBUS_TIMEOUT_FLG Sticky version of SMBUS_TIMEOUT Register 0x0012 Sticky OOF and LOS Flags Reg Address Bit Field Type Name Description 0x0012 3...

Page 133: ...ds to register 0x0014 the error flags in register 0x0017 If a mask bit is set the alarm will be blocked from causing an interrupt Register 0x0017 Status Flag Masks Reg Address Bit Field Type Name Description 0x0017 0 R W SYSINCAL_INTR_MSK 1 to mask SYSINCAL_FLG from caus ing an interrupt 0x0017 1 R W LOSXAXB_FLG_MSK 1 to mask the LOSXAXB_FLG from causing an interrupt 0x0017 5 R W SMBUS_TIMEOUT_INT...

Page 134: ...er See registers 0x0339 0x0353 0x001D 1 S FDEC 1 a rising edge will cause the selected MultiSynth to decrement the output frequency by the Nx_FSTEPW parameter See registers 0x0339 0x0353 Register 0x001E Sync Power Down and Hard Reset Reg Address Bit Field Type Name Description 0x001E 0 R W PDN 1 to put the device into low power mode 0x001E 1 S HARD_RST 1 causes hard reset The same as power up exce...

Page 135: ... Type Name Description 0x002C 3 0 R W LOS_EN 1 to enable LOS for a clock input 0 for disable 0x002C 4 R W LOSXAXB_DIS Enable LOS detection on the XAXB inputs 0 Enable LOS Detection default 1 Disable LOS Detection Register 0x002D Loss of Signal Re Qualification Value Reg Address Bit Field Type Name Description 0x002D 1 0 R W LOS0_VAL_TIME Clock Input 0 0 for 2 msec 1 for 100 msec 2 for 200 msec 3 f...

Page 136: ...rrect LOS register clear threshold value for Input 0 given a particular frequency plan Register 0x0030 0x0031 LOS1 Trigger Threshold Reg Address Bit Field Type Name Description 0x0030 7 0 R W LOS1_TRG_THR 16 bit Threshold Value 0x0031 15 8 R W LOS1_TRG_THR Register 0x0032 0x0033 LOS2 Trigger Threshold Reg Address Bit Field Type Name Description 0x0032 7 0 R W LOS2_TRG_THR 16 bit Threshold Value 0x...

Page 137: ..._OOF_EN 6 Input 3 corresponds to OOF_EN 3 FAST_OOF_EN 7 Register 0x0038 0x0039 LOS1 Clear Threshold Reg Address Bit Field Type Name Description 0x0038 7 0 R W LOS1_CLR_THR 16 bit Threshold Value 0x0039 15 8 R W LOS1_CLR_THR Register 0x003A 0x003B LOS2 Clear Threshold Reg Address Bit Field Type Name Description 0x003A 7 0 R W LOS2_CLR_THR 16 bit Threshold Value 0x003B 15 8 R W LOS2_CLR_THR Register...

Page 138: ...2OOFx_DIV_SEL CBPro sets these divid ers 0x0042 4 0 R W OOF1_DIV_SEL 0x0043 4 0 R W OOF2_DIV_SEL 0x0044 4 0 R W OOF3_DIV_SEL 0x0045 4 0 R W OOFXO_DIV_SEL Register 0x0046 0x0049 Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0046 7 0 R W OOF0_SET_THR OOF Set threshold Range is up to 500 ppm in steps of 1 16 ppm 0x0047 7 0 R W OOF1_SET_THR OOF Set threshold Range is up ...

Page 139: ... up to 500 ppm in steps of 1 16 ppm Register 0x004E 0x04F OOF Detection Windows Reg Address Bit Field Type Setting Name Description 0x004E 2 0 R W OOF0_DETWIN_SEL Values calculated by CBPro 0x004E 6 4 R W OOF1_DETWIN_SEL 0x004F 2 0 R W OOF2_DETWIN_SEL 0x004F 6 4 R W OOF3_DETWIN_SEL Register 0x0051 0x0054 Fast Out of Frequency Set Threshold Reg Address Bit Field Type Name Description 0x0051 3 0 R W...

Page 140: ...FAST_OOF2_DETWIN_SEL 0x0059 7 6 R W FAST_OOF3_DETWIN_SEL Register 0x005A 0x005D OOF0 Ratio for Reference Reg Address Bit Field Type Name Description 0x005A 7 0 R W OOF0_RATIO_REF Values calculated by CBPro 0x005B 15 8 R W OOF0_RATIO_REF 0x005C 23 16 R W OOF0_RATIO_REF 0x005D 25 24 R W OOF0_RATIO_REF Register 0x005E 0x0061 OOF1 Ratio for Reference Reg Address Bit Field Type Name Description 0x005E ...

Page 141: ... error will quickly assert LOL when this is enabled Register 0x0093 Fast LOL Detection Window Reg Address Bit Field Type Name Description 0x0093 7 4 R W LOL_FST_DETWIN_SEL Values calculated by CBPro Register 0x0095 Fast LOL Detection Value Reg Address Bit Field Type Name Description 0x0095 3 2 R W LOL_FST_VALWIN_SEL Values calculated by CBPro Register 0x0096 Fast LOL Set Threshold Reg Address Bit ...

Page 142: ...iption 0x009A 1 R W LOL_SLOW_EN_PLL 1 to enable LOL 0 to disable LOL Register 0x009B Slow LOL Detection Window Reg Address Bit Field Type Name Description 0x009B 7 4 R W LOL_SLW_DETWIN_SEL Values calculated by CBPro Register 0x009D Slow LOL Detection Value Reg Address Bit Field Type Setting Name Description 0x009D 3 2 R W LOL_SLW_VALWIN_SEL Values calculated by CBPro Register 0x009E LOL Set Thresh...

Page 143: ...by ClockBuilder Pro Register 0x00A0 LOL Clear Threshold Reg Address Bit Field Type Name Description 0x00A0 7 4 R W LOL_CLR_THR Configures the loss of lock set thresholds Selectable as 0 1 0 3 1 3 10 30 100 300 1000 3000 10000 Values are in ppm Register 0x00A2 LOL Timer Enable Reg Address Bit Field Type Name Description 0x00A2 1 R W LOL_TIMER_EN 0 to disable 1 to enable Register 0x00A9 0x00AC LOL C...

Page 144: ...x00E4 0 S NVM_READ_BANK When set this bit will read the NVM down into the volatile memory Register 0x00E5 Fastlock Extend Enable Reg Address Bit Field Type Name Description 0x00E5 5 R W FASTLOCK_EXTEND_EN Extend Fastlock bandwidth period past LOL Clear 0 Do not extend Fastlock period 1 Extend Fastlock period default Register 0x00EA 0x00ED LOL Detection Value Reg Address Bit Field Type Name Descrip...

Page 145: ...akly pulled low 0x0112 1 R W OUT0_OE Output driver 0 0 to disable the output 1 to enable the output 0x0112 2 R W OUT0_RDIV_FORCE2 0 R0 divider value is set by R0_REG 1 R0 divider value is forced into divide by 2 Register 0x0113 Output 0 Format Reg Address Bit Field Type Name Description 0x0113 2 0 R W OUT0_FORMAT 0 Reserved 1 swing mode normal swing differential 2 swing mode high swing differentia...

Page 146: ...grammable swing mode with high0 swing configu ration Step size 100 mV Range 0 9 V to 2 3 V if VDDO 3 3 V Range 0 6 V to 1 5 V if VDDO 2 5 V Range 0 5 V to 0 9 V if VDDO 1 8 V Rail to rail swing Mode configuration No flexibility DRV0_CM 6 if VDDO 3 3 V Vcm 1 5 V DRV0_CM 10 if VDDO 2 5 V Vcm 1 1 V DRV0_CM 13 if VDDO 1 8 V Vcm 0 8 V LVCMOS mode Not supported No effect 0x0114 6 4 R W OUT0_AMPL Output ...

Page 147: ...UT0_VDD_SEL_EN 1 Enable OUT0_VDD_SEL 0x0115 5 4 R W OUT0_VDD_SEL Must be set to the VDD0 voltage 3 NA 2 3 3 V 1 2 5 V 0 1 8 V 0x0115 7 6 R W OUT0_INV CLK and CLK not inverted CLK inverted CLK and CLK inverted CLK inverted Table 51 Registers that Follow the Same Definitions Above Register Address Description Same as Address 0x0117 Clock Output Driver 1 Config 0x0112 0x0118 Clock Output Driver 1 For...

Page 148: ...B Determines if outputs are disabled during an LOSXAXB condition 0 All outputs disabled on LOSXAXB 1 All outputs remain enabled during LOSXAXB condition 0x0141 7 R W OUT_DIS_MSK_LOS_PFD Register 0x0142 Output Disable Loss of Lock PLL Reg Address Bit Field Type Setting Name Description 0x0142 1 R W OUT_DIS_MSK_LOL 0 LOL will disable all connected outputs 1 LOL does not disable any out puts 0x0142 5...

Page 149: ...er 0x0146 0x0147 Reg Address Bit Field Type Setting Name Description 0x0146 7 0 R W DRV_RST 0x0147 11 8 R W DRV_RST Register 0x0148 0x0149 Reg Address Bit Field Type Setting Name Description 0x0148 7 0 R W DRV_DIV_RST 0x0149 11 8 R W DRV_DIV_RST ...

Page 150: ... Si5342 DSPLL and Multisynth System Flow Diagram on page 11 ClockBuilder Pro calculates the correct values for the P dividers Register 0x0202 0x0205 XAXB Frequency Adjust Reg Address Bit Field Type Name Description 0x0202 7 0 R W XAXB_FREQ_OFFSET 32 bit offset adjustment 0x0203 15 8 R W XAXB_FREQ_OFFSET 0x0204 23 16 R W XAXB_FREQ_OFFSET 0x0205 31 24 R W XAXB_FREQ_OFFSET Register 0x0206 Pre scale R...

Page 151: ...ess Bit Field Type Name Description 0x020E 7 0 R W P0_DEN 32 bit Integer Number 0x020F 15 8 R W P0_DEN 0x0210 23 16 R W P0_DEN 0x0211 31 24 R W P0_DEN Table 52 Registers that Follow the P0_NUM and P0_DEN Register Address Description Size Same as Address 0x0212 0x0217 P1 Divider Numerator 48 bit Integer Number 0x0208 0x020D 0x0218 0x021B P1 Divider Denominator 32 bit Integer Number 0x020E 0x0211 0x...

Page 152: ...le Reg Address Bit Field Type Setting Name Description 0x0232 3 0 R W P1_FRACN_MODE P1 IN1 input divider fractional mode Must be set to 0xB for proper operation 0x0232 4 R W P1_FRAC_EN P1 IN1 input divider fractional enable 0 Integer only division 1 Fractional or Integer division Register 0x0233 P2 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0233 3 0 R W P2_FRAC...

Page 153: ...x0234 3 0 R W P3_FRACN_MODE P3 IN3 input divider fractional mode Must be set to 0xB for proper operation 0x0234 4 R W P3_FRAC_EN P3 IN3 input divider fractional enable 0 Integer only division 1 Fractional or Integer division Register 0x0235 0x023A MXAXB Divider Numerator Reg Address Bit Field Type Setting Name Description 0x0235 7 0 R W MXAXB_NUM 44 bit Integer Number 0x0236 15 8 R W MXAXB_NUM 0x0...

Page 154: ...that Follow the R0_REG Register Address Description Size Same as Address 0x0253 0x0255F R1_REG 24 bit Integer Number 0x0250 0x0252 0x025C 0x025E R2_REG 24 bit Integer Number 0x0250 0x0252 0x025F 0x0261 R3_REG 24 bit Integer Number 0x0250 0x0252 Register 0x026B 0x0272 User Scratch Pad Reg Address Bit Field Type Name Description 0x026B 7 0 R W DESIGN_ID0 ASCII encoded string defined by CBPro user wi...

Page 155: ...rating characteristics selected in ClockBuilder Pro Register 0x0278 0x027C OPN Identifier Reg Address Bit Field Type Name Description 0x0278 7 0 R W OPN_ID0 OPN unique identifier ASCII encoded For example with OPN 5344C A12345 GM 12345 is the OPN unique identifier which sets OPN_ID0 0x31 OPN_ID1 0x32 OPN_ID2 0x33 OPN_ID3 0x34 OPN_ID4 0x35 0x0279 15 8 R W OPN_ID1 0x027A 23 16 R W OPN_ID2 0x027B 31 ...

Page 156: ...Bit Field Type Name Description 0x0299 1 R W FASTLOCK_DLY_ONLOL_EN Set by CBPro Register 0x029D Fastlock Delay on LOL Reg Address Bit Field Type Name Description 0x029D 1 R W FASTLOCK_DLY_ONLOL Set by CBPro Register 0x02A9 Fastlock Delay on Input Switch Reg Address Bit Field Type Name Description 0x02A9 7 0 R W FASTLOCK_DLY_ONSW 20 bit value Set by CBPro 0x02AA 15 8 R W FASTLOCK_DLY_ONSW 0x02AB 19...

Page 157: ...ster 0x0308 0x030C N0 Denominator Reg Address Bit Field Type Name Description 0x0308 7 0 R W N0_DEN 32 bit Integer Number The N0 value is N0_NUM N0_DEN 0x0309 15 8 R W N0_DEN 0x030A 23 16 R W N0_DEN 0x030B 31 24 R W N0_DEN 0x030C 0 R W N0_UPDATE Set this bit to update the N0 divider Table 54 Registers that Follow the N0_NUM and N0_DEN Definitions Register Address Description Size Same as Address 0...

Page 158: ...0338 Global N Divider Update Reg Address Bit Field Type Name Description 0x0338 1 R W N_UPDATE Set this bit to update all five N dividers Register 0x0339 FINC FDEC Masks Reg Address Bit Field Type Name Description 0x0339 3 0 R W N_FSTEP_MSK 0 to enable FINC FDEC updates 1 to disable FINC FDEC updates Register 0x033B 0x0340 N0 Frequency Step Word Reg Address Bit Field Type Name Description 0x033B 7...

Page 159: ...ro calculates the correct value for this register Register 0x0359 0x35A N0 Delay Control Reg Address Bit Field Type Name Description 0x0359 7 0 R W N0_DELAY 7 0 Lower byte of N0_DELAY 15 0 0x035A 7 0 R W N0_DELAY 15 8 Upper byte of N0_DELAY 15 0 Register 0x035B 0x035C Divider N1 Delay Control Reg Address Bit Field Type Name Description 0x35B 7 0 R W N1_DELAY 7 0 Lower byte of N1_DELAY 15 0 0x35C 7...

Page 160: ... addition the frequency of the clock selected by ZDM_IN_SEL must either be the same or have a simple integer relationship to the clock at the FB_IN pins Pin controlled clock selection is available in ZD mode see register 0x052A Register 0x0487 Zero Delay Mode Setup Reg Address Bit Field Type Name Description 0x0487 0 R W ZDM_EN 0 to disable ZD mode 1 to enable ZD mode 0x0487 2 1 R W ZDM_IN_SEL Clo...

Page 161: ...Name Description 0x0508 5 0 R W BW0_PLL PLL bandwidth parameter 0x0509 5 0 R W BW1_PLL PLL bandwidth parameter 0x050A 5 0 R W BW2_PLL PLL bandwidth parameter 0x050B 5 0 R W BW3_PLL PLL bandwidth parameter 0x050C 5 0 R W BW4_PLL PLL bandwidth parameter 0x050D 5 0 R W BW5_PLL PLL bandwidth parameter Register 0x050E 0x0514 Fast Lock Loop Bandwidth Reg Address Bit Field Type Name Description 0x050E 5 ...

Page 162: ...Address Bit Field Type Name Description 0x051C 7 0 R W M_DEN 32 bit Number 0x051E 15 8 R W M_DEN 0x051E 23 16 R W M_DEN 0x051F 31 24 R W M_DEN Register 0x0520 M Divider Update Bit Reg Address Bit Field Type Name Description 0x0520 0 R W M_UPDATE Set this bit to update the M divider Register 0x0521 DSPLL B M Divider Fractional Enable Reg Address Bit Field Type Setting Name Description 0x0521 3 0 R ...

Page 163: ...ption 0x052B 0 R W FASTLOCK_AUTO_EN Applies only when FASTLOCK_MAN 0 see below 0 to disable auto fast lock when the DSPLL is out of lock 1 to enable auto fast lock 0x052B 1 R W FASTLOCK_MAN 0 for normal operation see above 1 to force fast lock Register 0x052C Holdover Exit Control Reg Address Bit Field Type Setting Name Description 0x052C 0 R W HOLD_EN Holdover enable 0 Holdover Disabled 1 Holdove...

Page 164: ... Average Length Reg Address Bit Field Type Name Description 0x052E 4 0 R W HOLD_HIST_LEN 5 bit value Register 0x052F Holdover History Delay Reg Address Bit Field Type Name Description 0x052F 4 0 R W HOLD_HIST_DELAY Register 0x0531 Reg Address Bit Field Type Setting Name Description 0x0531 4 0 R W HOLD_REF_COUNT_FRC_PLLB 5 bit value Register 0x0532 0x0534 Reg Address Bit Field Type Setting Name Des...

Page 165: ...ter 0x0537 Input Alarm Masks Reg Address Bit Field Type Name Description 0x0537 3 0 R W IN_LOS_MSK For each clock input LOS alarm 0 to use LOS in the clock selection logic 1 to mask LOS from the clock selection logic 0x0537 7 4 R W IN_OOF_MSK For each clock input OOF alarm 0 to use OOF in the clock selection logic 1 to mask OOF from the clock selection logic Register 0x0538 Clock Inputs 0 and 1 Pr...

Page 166: ...ess Bit Field Type Name Description 0x0539 2 0 R W IN2_PRIORITY The priority for clock input 2 is 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved 0x0539 6 4 R W IN3_PRIORITY The priority for clock input 3 is 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserve...

Page 167: ...storical fre quency data collected for valid holdover 0x053F 2 R O FASTLOCK_STATUS 1 PLL is in Fast Lock operation Register 0x0588 Hitless Switching Length Reg Address Bit Field Type Setting Name Description 0x0588 3 0 R W HSW_FINE_PM_LEN Set by CBPro Register 0x0589 0x058A PFD Enable Delay Reg Address Bit Field Type Setting Name Description 0x0589 7 0 R W PFD_EN_DELAY Set by CBPro 0x058A 12 8 R W...

Page 168: ...D_BW_SEL1 Register 0x059F Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x059F 5 0 R W HOLDEXIT_BW2 Set by CBPro to set the PLL bandwidth when exiting holdover works with HOL DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x05A0 Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x05A0 5 0 R W HOLDEXIT_BW3 Set by CBPro to set the PLL bandwidth when exiting holdove...

Page 169: ...dover works with HOL DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x05A6 Hitless Switching Control Reg Address Bit Field Type Setting Name Description 0x05A6 2 0 R W RAMP_STEP_SIZE Size of the frequency ramp steps when ramping between inputs or when exiting holdover Calculated by CBPro based on selection 0x05A6 3 R W RAMP_SWITCH_EN Ramp Switching Enable 0 Disable Ramp Switching 1 Enable Ramp Switching ...

Page 170: ...ponds to IN_SEL 0x0949 2 IN_PULSED_CMOS_EN 0x0949 6 Input 3 corresponds to IN_SEL 0x0949 3 IN_PULSED_CMOS_EN 0x0949 7 Register 0x090E XAXB Configuration Reg Address Bit Field Type Name Description 0x090E 0 R W XAXB_EXTCLK_EN 0 to use a crystal at the XAXB pins 1 to use an external clock source at the XAXB pins Register 0x0943 Control I O Voltage Select Reg Address Bit Field Type Name Description 0...

Page 171: ...s Reg Address Bit Field Type Setting Name Description 0x094E 7 0 R W REFCLK_HYS_SEL Value calculated in CBPro 0x094F 3 0 R W REFCLK_HYS_SEL Register 0x095E MXAXB Fractional Mode Reg Address Bit Field Type Setting Name Description 0x094A 3 0 R W INX_TO_PFD_EN Set to 1 by CBPro Do not change ...

Page 172: ...s Multisynth outputs to output driver muxes Register 0x0A04 Output Multisynth Integer Divide Mode Reg Address Bit Field Type Name Description 0x0A04 4 0 R W N_PIBYP Output Multisynth integer divide mode Bit 0 for ID0 Bit 1 for ID1 etc 0 Nx divider is fractional 1 Nx divider is integer Register 0x0A05 Output Multisynth Divider Power Down Reg Address Bit Field Type Name Description 0x0A05 4 0 R W N_...

Page 173: ...R W OOF_CLK_DIS Set to 0 for normal operation Register 0x0B48 OOF Divider Clock Disables Reg Address Bit Field Type Name Description 0x0B48 4 0 R W OOF_DIV_CLK_DIS Set to 0 for normal operation Digital OOF divider clock user disable Bits 3 0 are for IN3 2 1 0 Bit 4 is for OOF for the XAXB input Register 0x0B4A Divider Clock Disables Reg Address Bit Field Type Name Description 0x0B4A 4 0 R W N_CLK_...

Page 174: ...g Address Bit Field Type Name Description 0x0001 7 0 R W PAGE Selects one of 256 possible pages Register 0x0002 0x0003 Base Part Number Reg Address Bit Field Type Name Value Description 0x0002 7 0 R PN_BASE 0x42 Four digit base part number one nibble per digit Example Si5342A A GM The base part number OPN is 5342 which is stored in this register 0x0003 15 8 R PN_BASE 0x53 Register 0x0004 Device Gr...

Page 175: ...ed to a specific base part type e g Si5342 but exclude any user defined frequency plan or other user defined operating characteristics selected in ClockBuilder Pro Register 0x0006 0x0008 TOOL_VERSION Reg Address Bit Field Type Name Description 0x0006 3 0 R W TOOL_VERSION 3 0 Special 0x0006 7 4 R W TOOL_VERSION 7 4 Revision 0x0007 7 0 R W TOOL_VERSION 15 8 Minor 7 0 0x0008 0 R W TOOL_VERSION 15 8 M...

Page 176: ... R W I2C_ADDR The upper 5 bits of the 7 bit I2C address The lower 2 bits are controlled by the A1 and A0 pins Register 0x000C Internal Status Bits Reg Address Bit Field Type Name Description 0x000C 0 R SYSINCAL 1 if the device is calibrating 0x000C 1 R LOSXAXB 1 if there is no signal at the XAXB pins 0x000C 2 R 0x000C 3 R 0x000C 4 R 0x000C 5 R SMBUS_TIMEOUT 1 if there is an SMBus timeout error Reg...

Page 177: ...hese bits are cleared by writing 0 to the bits that have been set Register 0x000F Calibration Status Reg Address Bit Field Type Name Description 0x000F 5 R CAL_PLL 1 if the DSPLL internal calibration is busy Register 0x0011 Sticky versions of Internal Status Bits Reg Address Bit Field Type Name Description 0x0011 0 R SYSINCAL_FLG Sticky version of SYSINCAL 0x0011 1 R LOSXAXB_FLG Sticky version of ...

Page 178: ... 7 Register 0x0014 Sticky INCAL Flag Reg Address Bit Field Type Name Description 0x0014 5 R W CAL_FLG_PLL 1 if the internal calibration was busy Register 0x0017 Status Flag Masks Reg Address Bit Field Type Name Description 0x0017 0 R W SYSINCAL_INTR_MSK 1 to mask SYSINCAL_FLG from causing an interrupt 0x0017 1 R W LOSXAXB_INTR_MSK 1 to mask the LOSXAXB_FLG from caus ing an interrupt 0x0017 2 R W 0...

Page 179: ...bration busy flag Register 0x001C Soft Reset and Calibration Reg Address Bit Field Type Name Description 0x001C 0 S SOFT_RST_ALL 1 Initialize and calibrates the entire device 0 No effect 0x001C 2 SOFT_RST 0x001C 5 SOFTCAL Register 0x001D FINC FDEC Reg Address Bit Field Type Name Description 0x001D 0 S FINC 1 a rising edge will cause the selected MultiSynth to increment the output frequency by the ...

Page 180: ... not self clear so after setting the bit it must be cleared 0 No reset 0x001E 2 S SYNC Logically equivalent to asserting the SYNC pin Resets all R dividers to the same state Register 0x002B SPI 3 vs 4 Wire Reg Address Bit Field Type Name Description 0x002B 3 R W SPI_3WIRE 0 for 4 wire SPI 1 for 3 wire SPI 0x002B 5 R W AUTO_NDIV_UPDATE Register 0x002C LOS Enable Reg Address Bit Field Type Name Desc...

Page 181: ...nal Re Qualification Value Reg Address Bit Field Type Name Description 0x002D 1 0 R W LOS0_VAL_TIME Clock Input 0 0 for 2 msec 1 for 100 msec 2 for 200 msec 3 for one second 0x002D 3 2 R W LOS1_VAL_TIME Clock Input 1 same as above 0x002D 5 4 R W LOS2_VAL_TIME Clock Input 2 same as above 0x002D 7 6 R W LOS3_VAL_TIME Clock Input 3 same as above Register 0x002E 0x002F LOS0 Trigger Threshold Reg Addre...

Page 182: ...Bit Field Type Name Description 0x0034 7 0 R W LOS3_TRG_THR 16 bit Threshold Value 0x0035 15 8 R W LOS3_TRG_THR Register 0x0036 0x0037 LOS0 Clear Threshold Reg Address Bit Field Type Name Description 0x0036 7 0 R W LOS0_CLR_THR 16 bit Threshold Value 0x0037 15 8 R W LOS0_CLR_THR Register 0x0038 0x0039 LOS1 Clear Threshold Reg Address Bit Field Type Name Description 0x0038 7 0 R W LOS1_CLR_THR 16 b...

Page 183: ...F 3 0 R W OOF_EN 1 to enable 0 to disable 0x003F 7 4 R W FAST_OOF_EN 1 to enable 0 to disable Register 0x0040 OOF Reference Select Reg Address Bit Field Type Name Description 0x0040 2 0 R W OOF_REF_SEL 0 for CLKIN0 1 for CLKIN1 2 for CLKIN2 3 for CLKIN3 4 for XAXB Register 0x0041 0x0045 OOF Divider Select Reg Address Bit Field Type Name Description 0x0041 4 0 R W OOF0_DIV_SEL Sets a divider for th...

Page 184: ...00 ppm in steps of 1 16 ppm 0x004B 7 0 R W OOF1_CLR_THR OOF Clear threshold Range is up to 500 ppm in steps of 1 16 ppm 0x004C 7 0 R W OOF2_CLR_THR OOF Clear threshold Range is up to 500 ppm in steps of 1 16 ppm 0x004D 7 0 R W OOF3_CLR_THR OOF Clear threshold Range is up to 500 ppm in steps of 1 16 ppm Register 0x004E 0x04F OOF Detection Windows Reg Address Bit Field Type Setting Name Description ...

Page 185: ...R W FAST_OOF0_CLR_THR 1 value x 1000 ppm 0x0056 3 0 R W FAST_OOF1_CLR_THR 1 value x 1000 ppm 0x0057 3 0 R W FAST_OOF2_CLR_THR 1 value x 1000 ppm 0x0058 3 0 R W FAST_OOF3_CLR_THR 1 value x 1000 ppm Register 0x0059 Fast OOF Detection Window Reg Address Bit Field Type Name Description 0x0059 1 0 R W FAST_OOF0_DETWIN_SEL Values calculated by CBPro 0x0059 3 2 R W FAST_OOF1_DETWIN_SEL 0x0059 5 4 R W FAS...

Page 186: ...RATIO_REF 0x0069 25 24 R W OOF3_RATIO_REF Register 0x0092 Fast LOL Enable Reg Address Bit Field Type Name Description 0x0092 1 R W LOL_FST_EN Enables fast detection of LOL A large input frequency error will quickly assert LOL when this is enabled Register 0x0093 Fast LOL Detection Window Reg Address Bit Field Type Name Description 0x0093 7 4 R W LOL_FST_DETWIN_SEL Values calculated by CBPro Regist...

Page 187: ...PLL 1 to enable LOL 0 to disable LOL Register 0x009B Slow LOL Detection Window Reg Address Bit Field Type Name Description 0x009B 7 4 R W LOL_SLW_DETWIN_SEL Values calculated by CBPro Register 0x009D Slow LOL Detection Value Reg Address Bit Field Type Setting Name Description 0x009D 3 2 R W LOL_SLW_VALWIN_SEL Values calculated by CBPro Register 0x009E LOL Set Threshold Reg Address Bit Field Type N...

Page 188: ...ues 0 0 1 ppm 1 0 3 ppm 2 1 ppm 3 3 ppm 4 10 ppm 5 30 ppm 6 100 ppm 7 300 ppm 8 1000 ppm 9 3000 ppm 10 10000 ppm LOL_TIMER_EN extends the time after LOL negates that the clock outputs can be disabled by LOL_CLR_DELAY see below Register 0x00A0 LOL Clear Threshold Reg Address Bit Field Type Name Description 0x00A0 7 4 R W LOL_SLW_CLR_THR Configures the loss of lock set thresholds Selectable as 0 1 0...

Page 189: ... Read only field indicating number of user bank writes carried out so far Value Description 0 zero 3 one 15 two 63 three Register 0x00E3 Reg Address Bit Field Type Setting Name Description 0x00E3 7 0 R W NVM_WRITE Write 0xC7 to initiate an NVM bank burn Register 0x00E4 Reg Address Bit Field Type Setting Name Description 0x00E4 0 S NVM_READ_BANK When set this bit will read the NVM down into the vol...

Page 190: ... Address Bit Field Type Name Description 0x00EA 7 0 R W FASTLOCK_EXTEND 29 bit value Set by CBPro to minimize the phase transients when switching the PLL bandwidth See FASTLOCK_EXTEND_SCL 0x00EB 15 8 R W FASTLOCK_EXTEND 0x00EC 23 16 R W FASTLOCK_EXTEND 0x00ED 28 24 R W FASTLOCK_EXTEND ...

Page 191: ...he output 1 to enable the output 0x0112 2 R W OUT0_RDIV_FORCE2 0 R0 divider value is set by R0_REG 1 R0 divider value is forced into divide by 2 Register 0x0113 Output 0 Format Reg Address Bit Field Type Name Description 0x0113 2 0 R W OUT0_FORMAT 0 Reserved 1 swing mode normal swing differential 2 swing mode high swing differential 3 rail to rail swing mode differential 4 LVCMOS single ended 5 7 ...

Page 192: ...0 9V if VDDO 1 8 V Programmable swing mode with high0 swing configu ration Step size 100 mV Range 0 9 V to 2 3 V if VDDO 3 3 V Range 0 6 V to 1 5 V if VDDO 2 5 V Range 0 5 V to 0 9 V if VDDO 1 8 V Rail to rail swing Mode configuration No flexibility DRV0_CM 6 if VDDO 3 3 V Vcm 1 5 V DRV0_CM 10 if VDDO 2 5 V Vcm 1 1 V DRV0_CM 13 if VDDO 1 8 V Vcm 0 8 V LVCMOS mode Not supported No effect 0x0114 6 4...

Page 193: ...elect This selects the source of the multisynth 0 N0 1 N1 2 reserved 3 reserved 4 reserved 5 reserved 6 reserved 7 reserved 0x0115 3 R W OUT0_VDD_SEL_EN 1 Enable OUT0_VDD_SEL 0x0115 5 4 R W OUT0_VDD_SEL Must be set to the VDD0 voltage 3 NA 2 3 3V 1 2 5V 0 1 8 V 0x0115 7 6 R W OUT0_INV CLK and CLK not inverted CLK inverted CLK and CLK inverted CLK inverted Table 56 Registers that Follow the Same De...

Page 194: ... 0x0142 Output Disable Loss of Lock PLL Reg Address Bit Field Type Setting Name Description 0x0142 1 R W OUT_DIS_MSK_LOL 0 LOL will disable all connected outputs 1 LOL does not disable any out puts 0x0142 5 R W OUT_DIS_MSK_HOLD Register 0x0145 Power Down All Reg Address Bit Field Type Name Description 0x0145 0 R W OUT_PDN_ALL 0 no effect 1 all drivers powered down Register 0x0146 0x0147 Reg Addres...

Page 195: ...342 DSPLL and Multisynth System Flow Diagram on page 11 ClockBuilder Pro calculates the correct values for the P dividers Register 0x0202 0x0205 XAXB Frequency Adjust Reg Address Bit Field Type Name Description 0x0202 7 0 R W XAXB_FREQ_OFFSET 32 bit offset adjustment 0x0203 15 8 R W XAXB_FREQ_OFFSET 0x0204 23 16 R W XAXB_FREQ_OFFSET 0x0205 31 24 R W XAXB_FREQ_OFFSET Register 0x0206 Pre scale Refer...

Page 196: ...ription 0x020E 7 0 R W P0_DEN 32 bit Integer Number 0x020F 15 8 R W P0_DEN 0x0210 23 16 R W P0_DEN 0x0211 31 24 R W P0_DEN Table 57 Registers that Follow the P0_NUM and P0_DEN Definitions Register Address Description Size Same as Address 0x0212 0x0217 P1 Divider Numerator 48 bit Integer Number 0x0208 0x020D 0x0218 0x021B P1 Divider Denominator 32 bit Integer Number 0x020E 0x0211 0x021C 0x0221 P2 D...

Page 197: ...le Reg Address Bit Field Type Setting Name Description 0x0232 3 0 R W P1_FRACN_MODE P1 IN1 input divider fractional mode Must be set to 0xB for proper operation 0x0232 4 R W P1_FRAC_EN P1 IN1 input divider fractional enable 0 Integer only division 1 Fractional or Integer division Register 0x0233 P2 Factional Division Enable Reg Address Bit Field Type Setting Name Description 0x0233 3 0 R W P2_FRAC...

Page 198: ...x0234 3 0 R W P3_FRACN_MODE P3 IN3 input divider fractional mode Must be set to 0xB for proper operation 0x0234 4 R W P3_FRAC_EN P3 IN3 input divider fractional enable 0 Integer only division 1 Fractional or Integer division Register 0x0235 0x023A MXAXB Divider Numerator Reg Address Bit Field Type Setting Name Description 0x0235 7 0 R W MXAXB_NUM 44 bit Integer Number 0x0236 15 8 R W MXAXB_NUM 0x0...

Page 199: ... W R0_REG 0x0252 23 16 R W R0_REG Table 58 Registers that Follow the R0_REG Register Address Description Size Same as Address 0x0253 0x0255 R1_REG 24 bit Integer Number 0x0250 0x0252 Register 0x026B 0x0272 User Scratch Pad Reg Address Bit Field Type Name Description 0x026B 7 0 R W DESIGN_ID0 ASCII encoded string defined by CBPro user with user defined space or null padding of unused characters A u...

Page 200: ...rating characteristics selected in ClockBuilder Pro Register 0x0278 0x027C OPN Identifier Reg Address Bit Field Type Name Description 0x0278 7 0 R W OPN_ID0 OPN unique identifier ASCII encoded For example with OPN 5342C A12345 GM 12345 is the OPN unique identifier which sets OPN_ID0 0x31 OPN_ID1 0x32 OPN_ID2 0x33 OPN_ID3 0x34 OPN_ID4 0x35 0x0279 15 8 R W OPN_ID1 0x027A 23 16 R W OPN_ID2 0x027B 31 ...

Page 201: ...le Reg Address Bit Field Type Name Description 0x0299 1 R W FASTLOCK_DLY_ONLOL_EN Set by CBPro Register 0x029D Fastlock Delay on LOL Reg Address Bit Field Type Name Description 0x029D 1 R W FASTLOCK_DLY_ONLOL Set by CBPro Register 0x02A9 Fastlock Delay on Input Switch Reg Address Bit Field Type Name Description 0x02A9 7 0 R W FASTLOCK_DLY_ONSW 20 bit value Set by CBPro 0x02AA 15 8 R W FASTLOCK_DLY...

Page 202: ... 44 bit Integer Number 0x0303 15 8 R W N0_NUM 0x0304 23 16 R W N0_NUM 0x0305 31 24 R W N0_NUM 0x0306 39 32 R W N0_NUM 0x0307 43 40 R W N0_NUM Register 0x0308 0x030B N0 Denominator Reg Address Bit Field Type Name Description 0x0308 7 0 R W N0_DEN 32 bit Integer Number 0x0309 15 8 R W N0_DEN 0x030A 23 16 R W N0_DEN 0x030B 31 24 R W N0_DEN Register 0x0338 Reg Address Bit Field Type Name Description 0...

Page 203: ...es requires a SOFT_RST a HARD_RST or a power up sequence Register 0x0317 Reg Address Bit Field Type Name Description 0x0317 0 R W N1_UPDATE Set this bit to update the N1 divider Register 0x0338 Global N Divider Update Reg Address Bit Field Type Name Description 0x0338 1 R W N_UPDATE Set this bit to update both N dividers Register 0x0339 FINC FDEC Masks Reg Address Bit Field Type Name Description 0...

Page 204: ... this register Changing any of the Nx_DELAY values requires a SOFT_RST a HARD_RST or a power up sequence Register 0x0359 0x035A N0 Delay Control Reg Address Bit Field Type Name Description 0x0359 7 0 R W N0_DELAY 7 0 8 bit Integer delay portion 0x035A 7 0 R W N0_DELAY 7 0 Upper byte of N0_DELAY 15 0 Table 61 Registers that Follow the N0_DELAY Definition Register Address Description Size Same as Ad...

Page 205: ... addition the frequency of the clock selected by ZDM_IN_SEL must either be the same or have a simple integer relationship to the clock at the FB_IN pins Pin controlled clock selection is available in ZD mode see register 0x052A Register 0x0487 Zero Delay Mode Setup Reg Address Bit Field Type Name Description 0x0487 0 R W ZDM_EN 0 to disable ZD mode 1 to enable ZD mode 0x0487 2 1 R W ZDM_IN_SEL Clo...

Page 206: ... Field Type Name Description 0x0508 5 0 R W BW0_PLL PLL bandwidth parameter 0x0509 5 0 R W BW1_PLL PLL bandwidth parameter 0x050A 5 0 R W BW2_PLL PLL bandwidth parameter 0x050B 5 0 R W BW3_PLL PLL bandwidth parameter 0x050C 5 0 R W BW4_PLL PLL bandwidth parameter 0x050D 5 0 R W BW5_PLL PLL bandwidth parameter Register 0x050E 0x0514 Fast Lock Loop Bandwidth Reg Address Bit Field Type Name Descripti...

Page 207: ...Address Bit Field Type Name Description 0x051C 7 0 R W M_DEN 32 bit Number 0x051E 15 8 R W M_DEN 0x051E 23 16 R W M_DEN 0x051F 31 24 R W M_DEN Register 0x0520 M Divider Update Bit Reg Address Bit Field Type Name Description 0x0520 0 R W M_UPDATE Set this bit to update the M divider Register 0x0521 DSPLL B M Divider Fractional Enable Reg Address Bit Field Type Setting Name Description 0x0521 3 0 R ...

Page 208: ...ption 0x052B 0 R W FASTLOCK_AUTO_EN Applies only when FASTLOCK_MAN 0 see below 0 to disable auto fast lock when the DSPLL is out of lock 1 to enable auto fast lock 0x052B 1 R W FASTLOCK_MAN 0 for normal operation see above 1 to force fast lock Register 0x052C Holdover Exit Control Reg Address Bit Field Type Setting Name Description 0x052C 0 R W HOLD_EN Holdover enable 0 Holdover Disabled 1 Holdove...

Page 209: ...ory Average Length Reg Address Bit Field Type Name Description 0x052E 4 0 R W HOLD_HIST_LEN 5 bit value Register 0x0531 Reg Address Bit Field Type Setting Name Description 0x0531 4 0 R W HOLD_REF_COUNT_FRC_PLLB 5 bit value Register 0x0532 Reg Address Bit Field Type Setting Name Description 0x0532 7 0 R W HOLD_15M_CYC_COUNT_PLLB Value calculated by CBPro 0x0533 15 8 R W HOLD_15M_CYC_COUNT_PLLB 0x05...

Page 210: ...ter 0x0537 Input Alarm Masks Reg Address Bit Field Type Name Description 0x0537 3 0 R W IN_LOS_MSK For each clock input LOS alarm 0 to use LOS in the clock selection logic 1 to mask LOS from the clock selection logic 0x0537 7 4 R W IN_OOF_MSK For each clock input OOF alarm 0 to use OOF in the clock selection logic 1 to mask OOF from the clock selection logic Register 0x0538 Clock Inputs 0 and 1 Pr...

Page 211: ... Address Bit Field Type Name Description 0x0539 2 0 R W IN2_PRIORITY The priority for clock input 2 is 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are reserved 0x0539 6 4 R W IN3_PRIORITY The priority for clock input 3 is 0 for clock input not selectable 1 for priority 1 2 for priority 2 3 for priority 3 4 for priority 4 5 to 7 are re...

Page 212: ...storical fre quency data collected for valid holdover 0x053F 2 R O FASTLOCK_STATUS 1 PLL is in Fast Lock operation Register 0x0588 Hitless Switching Length Reg Address Bit Field Type Setting Name Description 0x0588 3 0 R W HSW_FINE_PM_LEN Set by CBPro Register 0x0589 0x058A PFD Enable Delay Reg Address Bit Field Type Setting Name Description 0x0589 7 0 R W PFD_EN_DELAY Set by CBPro 0x058A 12 8 R W...

Page 213: ...D_BW_SEL1 Register 0x059F Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x059F 5 0 R W HOLDEXIT_BW2 Set by CBPro to set the PLL bandwidth when exiting holdover works with HOL DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x05A0 Holdover Exit BW Reg Address Bit Field Type Setting Name Description 0x05A0 5 0 R W HOLDEXIT_BW3 Set by CBPro to set the PLL bandwidth when exiting holdove...

Page 214: ...dover works with HOL DEXIT_BW_SEL0 and HOLD_BW_SEL1 Register 0x05A6 Hitless Switching Control Reg Address Bit Field Type Setting Name Description 0x05A6 2 0 R W RAMP_STEP_SIZE Size of the frequency ramp steps when ramping between inputs or when exiting holdover Calculated by CBPro based on selection 0x05A6 3 R W RAMP_SWITCH_EN Ramp Switching Enable 0 Disable Ramp Switching 1 Enable Ramp Switching ...

Page 215: ...t 1 corresponds to IN_SEL 0x0949 1 IN_PULSED_CMOS_EN 0x0949 5 Input 2 corresponds to IN_SEL 0x0949 2 IN_PULSED_CMOS_EN 0x0949 6 Input 3 corresponds to IN_SEL 0x0949 3 IN_PULSED_CMOS_EN 0x0949 7 Register 0x090E XAXB Configuration Reg Address Bit Field Type Name Description 0x090E 0 R W XAXB_EXTCLK_EN 0 to use a crystal at the XAXB pins 1 to use an external clock source at the XAXB pins Register 0x0...

Page 216: ...lue calculated in CBPro Register 0x094E 0x094F Input Clock Buffer Hysteresis Reg Address Bit Field Type Setting Name Description 0x094E 7 0 R W REFCLK_HYS_SEL Value calculated in CBPro 0x094F 3 0 R W REFCLK_HYS_SEL Register 0x095E MXAXB Fractional Mode Reg Address Bit Field Type Setting Name Description 0x094A 3 0 R W INX_TO_PFD_EN Set to 1 by CBPro Do not change ...

Page 217: ...s Multisynth outputs to output driver muxes Register 0x0A04 Output Multisynth Integer Divide Mode Reg Address Bit Field Type Name Description 0x0A04 4 0 R W N_PIBYP Output Multisynth integer divide mode Bit 0 for ID0 Bit 1 for ID1 etc 0 Nx divider is fractional 1 Nx divider is integer Register 0x0A05 Output Multisynth Divider Power Down Reg Address Bit Field Type Name Description 0x0A05 4 0 R W N_...

Page 218: ...R W OOF_CLK_DIS Set to 0 for normal operation Register 0x0B48 OOF Divider Clock Disables Reg Address Bit Field Type Name Description 0x0B48 4 0 R W OOF_DIV_CLK_DIS Set to 0 for normal operation Digital OOF divider clock user disable Bits 3 0 are for IN3 2 1 0 Bit 4 is for OOF for the XAXB input Register 0x0B4A Divider Clock Disables Reg Address Bit Field Type Name Description 0x0B4A 4 0 R W N_CLK_...

Page 219: ...l Format See the Si5345 44 42 data sheet for the rise fall time specifications If the standard LVDS or LVPECL compatible output amplitudes will not work for a particular application the variable amplitude capability can be used to achieve higher or lower amplitudes For example a CML format is sometimes desired for an application However CML is not a defined standard and hence the amplitude of a CM...

Page 220: ...ort aspx if you require a factory programmed device to be configured for any of the output driver settings in this appendix Table 63 Typical Differential Amplitudes OUTx_AMPL Normal Differential Format Vpp SE mV Typical Low Power Differential Format Vpp SE mV Typical 0 130 200 1 230 400 2 350 620 3 450 820 4 575 1010 5 700 1200 6 810 13501 7 920 16001 Notes 1 In low power mode and VDDOx 1 8V OUTx_...

Page 221: ...Si5345 44 42 D RM Rev 1 0 221 DOCUMENT CHANGE LIST Revision 1 0 July 28 2016 Initial release ...

Page 222: ...ricate any integrated circuits The products are not designed or authorized to be used within any Life Support System without the specific written consent of Silicon Laboratories A Life Support System is any product or system intended to support or sustain life and or health which if it fails can be reasonably expected to result in significant personal injury or death Silicon Laboratories products ...

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