Si5345-44-42-D-RM
Rev. 1.0
17
4.3. NVM Programming
The NVM is two time writable. Because it can only be written two times, it is important to configure the registers
correctly before beginning the NVM programming process. Once a new configuration has been written to NVM, the
old configuration is no longer accessible. Note: In-circuit programming is only supported over a temperature range
of 0° to 80°C.
The procedure for writing registers into NVM is as follows:
1. Write all registers as needed.
2. You may write to the user scratch space (registers 0x026B to 0x0272) to identify the content of NVM bank.
3. Write 0xC7 to NVM_WRITE register.
4. Wait until DEVICE_READY = 0x0F
WARNING! Any attempt to read or write any register other than DEVICE_READY before DEVICE_READY reads
as 0x0F may corrupt the register contents or NVM programming. Note that this includes writes to the PAGE
register.
5. Set NVM_READ_BANK 0x00E4[0] = “1”.
6. Wait until DEVICE_READY = 0x0F.
7. Steps 5 and 6 can be replaced by simply powering down and then powering up the device.
4.4. Free Run Mode
The DSPLL will automatically enter freerun mode once power is applied to the device and initialization is complete.
The frequency accuracy of the generated output clocks in freerun mode is entirely dependent on the frequency
accuracy of the external crystal or reference clock on the XA/XB pins. For example, if the crystal frequency is
±100 ppm, then all the output clocks will be generated at their configured frequency ±100 ppm in freerun mode.
Any drift of the crystal frequency will be tracked at the output clock frequencies. A TCXO or OCXO is
recommended for applications that need better frequency accuracy and stability while in freerun or holdover
modes. Because there is little or no jitter attenuation from the XAXB pins to the clock outputs, a low-jitter XAXB
source will be needed for low-jitter clock outputs.
4.5. Acquisition Mode
The device monitors all inputs for a valid clock. If at least one valid clock is available for synchronization, the
DSPLL will automatically start the lock acquisition process. If the fast lock feature is enabled, the DSPLL will
acquire lock using the Fastlock Loop Bandwidth setting and then transition to the DSPLL Loop Bandwidth setting
when lock acquisition is complete. During lock acquisition the outputs will generate a clock that follows the VCO
frequency change as it pulls-in to the input clock frequency.
4.6. Locked Mode
Once locked, the DSPLL will generate output clocks that are both frequency and phase locked to its selected input
clock. At this point any XTAL frequency drift will typically not affect the output frequency. A loss of lock pin (LOL)
and status bit indicate when lock is achieved. See “5.3.3. Loss of Lock Fault Monitoring” for more details on the
operation of the loss of lock circuit.
Table 6. NVM Programming Registers
Register Name
Hex Address
[Bit Field]
Function
ACTIVE_NVM_BANK
0x00E2[7:0]
Indicates number of user bank writes carried out so far.A
NVM_WRITE
0x00E3[7:0]
Initiates an NVM write when written with 0xC7
NVM_READ_BANK
0x00E4[0]
Download register values with content stored in NVM
DEVICE_READY
0x00FE[7:0]
Indicates that the device serial interface is ready to accept commands.
