UP-5900VS
CIRCUIT DESCRIPTION
5 – 20
IOCHRDY
I/O
I/O CHANNEL READY. Resources on the ISA Bus negate IOCHRDY to indicate that wait states are required to
complete the cycle. This signal is normally high.
IOCHRDY is an input when PIIX4E owns the ISA Bus and the CPU or a PCI agent is accessing an ISA slave, or dur-
ing DMA transfers. IOCHRDY is output when an external ISA Bus Master owns the ISA Bus and is accessing DRAM
or a PIIX4E register. As a PIIX4E output, IOCHRDY is driven inactive (low) from the falling edge of the ISA com-
mands. After data is available for an ISA master read or PIIX4E latches the data for a write cycle, IOCHRDY is
asserted for 70 ns. After 70 ns, PIIX4E floats IOCHRDY. The 70 ns includes both the drive time and the time it takes
PIIX4E to float IOCHRDY. PIIX4E does not drive this signal when an ISA Bus master is accessing an ISA Bus slave.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
IOCS16#
I
16-BIT I/O CHIP SELECT. This signal is driven by I/O devices on the ISA Bus to indicate support for 16-bit I/O bus
cycles.
IOR#
I/O
I/O READ. IOR# is the command to an ISA I/O slave device that the slave may drive data on to the ISA data bus
(SD[15:0]). The I/O slave device must hold the data valid until after IOR# is negated. IOR# is an output when PIIX4E
owns the ISA Bus. IOR# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z
After Reset: High
During POS: High
IOW#
I/O
I/O WRITE. IOW# is the command to an ISA I/O slave device that the slave may latch data from the ISA data bus
(SD[15:0]). IOW# is an output when PIIX4E owns the ISA Bus. IOW# is an input when an external ISA master owns
the ISA Bus.
During Reset: High-Z
After Reset: High
During POS: High
LA[23:17]/
GPO[7:1]
I/O
ISA LA[23:17]. LA[23:17] address lines allow accesses to physical memory on the ISA Bus up to 16 Mbytes.
LA[23:17] are outputs when PIIX4E owns the ISA Bus.
The LA[23:17] lines become inputs whenever an ISA master owns the ISA Bus. If the EIO bus is used, these signals
become a general purpose output.
During Reset: High-Z
After Reset: Undefined
During POS: Last LA/GPO
MEMCS16#
I/O
MEMORY CHIP SELECT 16. MEMCS16# is a decode of LA[23:17] without any qualification of the command signal
lines. ISA slaves that are 16-bit memory devices drive this signal low. PIIX4E ignores MEMCS16# during I/O access
cycles and refresh cycles. MEMCS16# is an input when PIIX4E owns the ISA Bus. PIIX4E drives this signal low dur-
ing ISA master to PCI memory cycles.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
MEMR#
I/O
MEMORY READ. MEMR# is the command to a memory slave that it may drive data onto the ISA data bus. MEMR#
is an output when PIIX4E is a master on the ISA Bus. MEMR# is an input when an ISA master, other than PIIX4E,
owns the ISA Bus. This signal is also driven by PIIX4E during refresh cycles. For DMA cycles, PIIX4E, as a master,
asserts MEMR#.
During Reset: High-Z
After Reset: High
During POS: High
MEMW#
I/O
MEMORY WRITE. MEMW# is the command to a memory slave that it may latch data from the ISA data bus.
MEMW# is an output when PIIX4E owns the ISA Bus.
MEMW# is an input when an ISA master, other than PIIX4E, owns the ISA Bus. For DMA cycles, PIIX4E, as a mas-
ter, asserts MEMW#.
During Reset: High-Z
After Reset: High
During POS: High
REFRESH#
I/O
REFRESH. As an output, REFRESH# is used by PIIX4E to indicate when a refresh cycle is in progress. It should be
used to enable the SA[7:0] address to the row address inputs of all banks of dynamic memory on the ISA Bus. Thus,
when MEMR# is asserted, the entire expansion bus dynamic memory is refreshed.
Memory slaves must not drive any data onto the bus during refresh. As an output, this signal is driven directly onto
the ISA Bus. This signal is an output only when PIIX4E DMA refresh controller is a master on the bus responding to
an internally generated request for refresh.
As an input, REFRESH# is driven by 16-bit ISA Bus masters to initiate refresh cycles.
During Reset: High-Z
After Reset: High
During POS: High
RSTDRV
O
RESET DRIVE. PIIX4E asserts RSTDRV to reset devices that reside on the ISA/EIO Bus. PIIX4E asserts this signal
during a hard reset and during power-up.
RSTDRV is asserted during power-up and negated after PWROK is driven active.
RSTDRV is also driven active for a minimum of 1 ms if a hard reset has been programmed in the RC register.
During Reset: High
After Reset: Low
During POS: Low
SA[19:0]
I/O
SYSTEM ADDRESS[19:0]. These bi-directional address lines define the selection with the granularity of 1 byte
within the 1-Megabyte section of memory defined by the LA[23:17] address lines. The address lines SA[19:17] that
are coincident with LA[19:17] are defined to have the same values as LA[19:17] for all memory cycles.
For I/O accesses, only SA[15:0] are used, and SA[19:16] are undefined. SA[19:0] are outputs when PIIX4E owns
the ISA Bus. SA[19:0] are inputs when an external ISA Master owns the ISA Bus.
During Reset: High-Z
After Reset: Undefined
During POS: Last SA
SBHE#
I/O
SYSTEM BYTE HIGH ENABLE. SBHE# indicates, when asserted, that a byte is being transferred on the upper byte
(SD[15:8]) of the data bus. SBHE# is negated during refresh cycles. SBHE# is an output when PIIX4E owns the ISA
Bus. SBHE# is an input when an external ISA master owns the ISA Bus.
During Reset: High-Z
After Reset: Undefined
During POS: High
SD[15:0]
I/O
SYSTEM DATA. SD[15:0] provide the 16-bit data path for devices residing on the ISA Bus. SD[15:8] correspond to
the high order byte and SD[7:0] correspond to the low order byte. SD[15:0] are undefined during refresh.
During Reset: High-Z
After Reset: Undefined
During POS: High-Z
Name
Type
Description
