UP-5900VS
CIRCUIT DESCRIPTION
5 – 16
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AGP Interface Signals
Name
Type
Description
AGP Sideband Addressing Signals
1
PIPE#
I
AGP
Pipelined Read: This signal is asserted by the current master to indicate a full width address is to be queued by the
target. The master queues one request each rising clock edge while PIPE# is asserted. When PIPE# is deasserted
no new requests are queued across the AD bus. PIPE# is a sustained tri-state signal from masters (graphics con-
troller) and is an input to the 82443BX. Note that initial AGP designs may not use PIPE#.
SBA[7:0]
I
AGP
Sideband Address: This bus provides an additional bus to pass address and command to the 82443BX from the
AGP master. Note that, when sideband addressing is disabled, these signals are isolated (no external/internal pull-
ups are required).
AGP Flow Control Signals
RBF#
I
AGP
Read Buffer Full. This signal indicates if the master is ready to accept previously requested low priority read data.
When RBF# is asserted the 82443BX is not allowed to return low priority read data to the AGP master on the first
block. RBF# is only sampled at the beginning of a cycle.
If the AGP master is always ready to accept return read data then it is not required to implement this signal.
AGP Status Signals
ST[2:0]
O
AGP
Status Bus: This bus provides information from the arbiter to a AGP Master on what it may do. ST[2:0] only have
meaning to the master when its GGNT# is asserted.
When GGNT# is deasserted these signals have no meaning and must be ignored.
000 Indicates that previously requested low priority read data is being returned to the master.
001 Indicates that previously requested high priority read data is being returned to the master.
010 Indicates that the master is to provide low priority write data for a previously queued write command.
011 Indicates that the master is to provide high priority write data for a previously queued write command.
100 Reserved
101 Reserved
110 Reserved
111 Indicates that the master has been given permission to start a bus transaction.
The master may queue AGP requests by asserting PIPE# or start a PCI transaction by asserting FRAME#.
ST[2:0] are always an output from the 82443BX and an input to the master.
AGP Clocking Signals - Strobes
ADSTB_A
I/O
AGP
AD Bus Strobe A: This signal provides timing for double clocked data on the AD bus.
The agent that is providing data drives this signal. This signal requires an 8.2K ohm external pull-up resistor.
ADSTB_B
I/O
AGP
AD Bus Strobe B: This signal is an additional copy of the AD_STBA signal. This signal requires an 8.2K ohm exter-
nal pull-up resistor.
SBSTB
I
AGP
Sideband Strobe: THis signal provides timing for a side-band bus. This signal requires an 8.2K ohm external pull-
up resistor.
AGP FRAME# Protocol SIgnals (similar to PCI)
2
GFRAME#
I/O
AGP
Graphics Frame: Same as PCI. Not used by AGP. GFRAME# remains deasserted by its own pull up resistor.
GIRDY#
I/O
AGP
Graphics Initiator Ready: New meaning. GIRDY# indicates the AGP compliant master is ready to provide all write
data for the current transaction. Once IRDY# is asserted for a write operation, the master is not allowed to insert
wait states. The assertion of IRDY# for reads indicates that the master is ready to transfer to a subsequent block
(32 bytes) of read data. The master is never allowed to insert wait states during the initial data transfer (32 bytes) of
a read transaction. However, it may insert wait states after each 32 byte block is transferred.
(There is no GFRAME# -- GIRDY# relationship for AGP transactions.)
GTRDY#
I/O
AGP
Graphics Target Ready: New meaning. GTRDY# indicates the AGP compliant target is ready to provide read data
for the entire transaction (when the transfer size is less than or equal to 32 bytes) or is ready to transfer the initial or
subsequent block (32 bytes) of data when the transfer size is greater than 32 bytes. The target is allowed to insert
wait states after each block (32 bytes) is transferred on both read and write transactions.
GSTOP#
I/O
AGP
Graphics Stop: Same as PCI. Not used by AGP.
GDEVSEL#
I/O
AGP
Graphics Device Select: Same as PCI. Not used by AGP.
GREQ#
I
AGP
Graphics Request: Same as PCI. (Used to request access to the bus to initiate a PCI or AGP request.)
GGNT#
O
AGP
Graphics Grant: Same meaning as PCI but additional information is provided on ST[2:0]. The additional informa-
tion indicates that the selected master is the recipient of previously requested read data (high or normal priority), it
is to provide write data (high or normal priority), for a previously queued write command or has been given permis-
sion to start a bus transaction (AGP or PCI).
GAD[31:0]
I/O
AGP
Graphics Address/Data: Same as PCI.
GC/BE[3:0]#
I/O
AGP
Graphics Command/Byte Enables: Slightly different meaning. Provides command information (different commands
than PCI) when requests are being queued when using PIPE#. Provide valid byte information during AGP write
transactions and are not used during the return of read data.
GPAR
I/O
AGP
Graphics Parity: Same as PCI. Not used on AGP transactions, but used during PCI transactions as defined by the
PCI specification.
