UP-5900VS
CIRCUIT DESCRIPTION
5 – 24
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CLOCKING SIGNALS
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IDE SIGNALS
SMI#
OD
SYSTEM MANAGEMENT INTERRUPT. SMI# is an active low synchronous output that is asserted by PIIX4E in
response to one of many enabled hardware or software events. The CPU recognizes the falling edge of SMI# as the
highest priority interrupt in the system, with the exception of INIT, CPURST, and FLUSH.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
STPCLK#
OD
STOP CLOCK. STPCLK# is an active low synchronous output that is asserted by PIIX4E in response to one of
many hardware or software events. STPCLK# connects directly to the CPU and is synchronous to PCICLK.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
Name
Type
Description
CLK48
I
48-MHZ CLOCK. 48-MHz clock used by the internal USB host controller. This signal may be stopped during sus-
pend modes.
PCICLK
I
FREE-RUNNING PCI CLOCK. A clock signal running at 30 or 33 MHz, PCICLK provides timing for all transactions
on the PCI Bus. All other PCI signals are sampled on the rising edge of PCICLK, and all timing parameters are
defined with respect to this edge. Because many of the circuits in PIIX4E run off the PCI clock, this signal MUST be
kept active, even if the PCI bus clock is not active.
OSC
I
14.31818-MHZ CLOCK. Clock signal used by the internal 8254 timer. This clock signal may be stopped during sus-
pend modes.
RTCX1,
RTCX2
I/O
RTC CRYSTAL INPUTS: These connected directly to a 32.768-kHz crystal. External capacitors are required. These
clock inputs are required even if the internal RTC is not being used.
SUSCLK
O
SUSPEND CLOCK. 32.768-kHz output clock provided to the Host-to-PCI bridge used for maintenance of DRAM
refresh. This signal is stopped during Suspend-to-Disk and Soft Off modes. For values During Reset, After Reset,
and During POS, see the Suspend/Resume and Resume Control Signaling section.
SYSCLK
O
ISA SYSTEM CLOCK. SYSCLK is the reference clock for the ISA bus. It drives the ISA bus directly. The SYSCLK is
generated by dividing PCICLK by 4. The SYSCLK frequencies supported are 7.5 MHz and 8.33 MHz. For PCI
accesses to the ISA bus, SYSCLK may be stretched low to synchronize BALE falling to the rising edge of SYSCLK.
During Reset: Running
After Reset: Running
During POS: Low
Name
Type
Description
PDA[2:0]
O
PRIMARY DISK ADDRESS[2:0]. These signals indicate which byte in either the ATA command block or control
block is being addressed.
If the IDE signals are configured for Primary and Secondary, these signals are connected to the corresponding sig-
nals on the Primary IDE connector.
If the IDE signals are configured for Primary 0 and Primary 1, these signals are used for the Primary 0 connector.
During Reset: High-Z
After Reset: Undefined
1
During POS: PDA
PDCS1#
O
PRIMARY DISK CHIP SELECT FOR 1F0H-1F7H RANGE. For ATA command register block. If the IDE signals are
configured for Primary and Secondary, this output signal is connected to the corresponding signal on the Primary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
During POS: High
PDCS3#
O
PRIMARY DISK CHIP SELECT FOR 3F0-3F7 RANGE. For ATA control register block. If the IDE signals are config-
ured for Primary and Secondary, this output signal is connected to the corresponding signal on the Primary IDE con-
nector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
During POS: High
PDD[15:0]
I/O
PRIMARY DISK DATA[15:0]. These signals are used to transfer data to or from the IDE device. If the IDE signals
are configured for Primary and Secondary, these signals are connected to the corresponding signals on the Primary
IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High-Z
After Reset: Undefined
1
During POS: PDD
PDDACK#
O
PRIMARY DMA ACKNOWLEDGE. This signal directly drives the IDE device DMACK# signal. It is asserted by
PIIX4E to indicate to IDE DMA slave devices that a given data transfer cycle (assertion of PDIOR# or PDIOW#) is a
DMA data transfer cycle. This signal is used in conjunction with the PCI bus master IDE function. It is not associated
with any AT compatible DMA channel.
If the IDE signals are configured for Primary and Secondary, this signal is connected to the corresponding signal on
the Primary IDE connector.
If the IDE signals are configured for Primary Master and Primary Slave, this signal is used for the Primary Master
connector.
During Reset: High
After Reset: High
During POS: High
Name
Type
Description
