UP-5900VS
CIRCUIT DESCRIPTION
5 – 18
11. CHIPSET (SOUTH BRIDGE)
Intel’s PIIX4E is used.
11-1. PIN ASSIGHMENTS
11-2. PIN DISCRIPTION
1) PIIX4E Signals
■
■
■
■
PCI BUS INTERFACE
M
N
P
R
T
U
V
W
Y
K
L
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
A
B
C
D
E
F
G
H
J
PCIR-
ST#
AD1
PCIR-
EQB#
PHLD-
A#
SDD6 SDD4 SDD13 SDDR-
EQ
SDD-
ACK#
SDA2 PDD8 PDD7
AD27 IDSEL AD19
FRA-
ME #
SERR# AD13
AD9
AD5
AD31
AD0
PCIR-
EQC#
PHO-
LD#
SDD9
SDD-
11
SDD1
SDI-
OW#
SDA1
SDC-
S1#
PDD9
AD26
AD23
PDD6
AD18 IRDY#
PAR
AD12
AD8
AD4
AD30 AD25
CLK-
RUN#
PCIR-
EQD#
SDD7 SDD5 SDD3 SDD14
SDI-
OR#
SDA0
SDC-
S3#
PDD10 PDD5
AD22
AD17 TRDY#
C/-
BE1#
AD11
C/-
BE0#
AD3
AD28
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
PCI-
CLK
SDD8
SDD2 SDD15
SIO-
RDY
PDD-
12
PDD3 PDD-
11
PDD4
C/-
BE3#
AD20
C/-
BE2#
STOP# AD14
AD10
AD6
AD2
AD29
AD24
AD21
PCIR-
EQA#
VCC
SDD12 SDD0
VCC PDD14 PDD1 PDD13 PDD2
AD16
DEV-
SEL#
AD15
VSS
AD7
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
USB-
P1+
GPO-
28
PDI-
OW#
PDI-
OR#
PDD-
REQ
PDD15 PDD0
IRQ9-
OUT
GPO-
30
PIR-
QD#
USB-
P0+
PIO-
RDY
PDA0 PDA2 PDA1
PDD-
ACK#
GP1-
21
GPO-
0
GPO-
27
GPI-
18
USB
P1-
USB
PO-
GPI-
19
GPI-
20
PDC-
S3#
PDC-
S1#
API-
CCS#
THRM# IRQ0
OC0# OC1#
GPI-
14
NC
NC
NC
NC
NC
VSS
(USB)
KBC-
CS#
RTC-
CS#
GPI-
16
GPI-
17
VCC
(USB)
VREF
APIC-
ACK#
STP-
CLK#
SER-
IRQ
IRQ1
ZZ
SPKR APIC-
REQ#
FERR# SLP#
RTC-
ALE
VCC
(RTC)
IGN-
NE#
INIT
INTR
NMI
GPI-
13
PCS0#
CLK-
48
GPI-
15
REQ-
A#
BIOS-
CS#
XDIR# XOE#
NC
RSM-
RST#
PWR
OK
CPU-
RST
A20-
M#
GNTA# REQ-
B#
MCCS# PCS1#
VCC
(SUS)
SMBAL-
ERT#
RTCX1 RCIN#
A20-
GATE
GNT-
B#
REQ-
C#
GNT-
C#
PIR-
QC#
LID
SUS-
CLK
RI#
GPI-
1
SMI#
CPU_-
STP#
PCI_-
STP#
PIR-
QA#
PIR-
QB#
VCC
(SUS)
CON-
FIG1
CON-
FIG2
SMB-
CLK
RTC-
X2
SD6
SD3
IOCH-
RDY
IOW#
SA16
SYS-
CLK
SA9
IRQ3
SA4
SA1
LA23
IRQ-
12/M
LA18 DACK-
5#
SD9
SUS_
STAT1#
SUS_
STAT2#
GPO-
8
SMB-
DATA
IRQ9
BALE
SA0
IRQ10 LA20 DACK-
0#
MEM-
W#
DRE-
Q6
DRE-
Q7
SUSC# BAT-
LOW#
PWR-
BTN#
SD2
SME-
MW#
SA18
DRE-
Q3
DRE-
Q1
SA11
IRQ5
SA6
SD7
DRE-
Q2
SD0
SA19 DACK-
3#
SA14
SA12
IRQ6
SA7
TC
OSC
IOCS-
16#
LA21
IRQ14 MEM-
R#
DACK-
6#
SD11 TEST# SUSB# EXT-
SMI#
RST-
DRV
SD4
SD1
SME-
MR#
SA17 DACK-
1#
REFR-
ESH#
SA10
IRQ4
SA5
SA2
SBH-
E#
IRQ11 LA19
DRE-
Q0
SD8
DACK-
7#
SD13
SD15 SUSA#
IOCHK# SD5
ZERO-
WS#
AEN
IOR#
SA15
SA13
IRQ7
SA8
DACK-
2#
SA3
MEM-
CS16#
LA22
IRQ15 LA17
DRE-
Q5
SD10
SD12
SD14 IRQ8#
SDD10
pix4_pin
NOTE:
For multiplexed pins, only one of the two signal names is shown in this figure. For example, the name
for “Y20” only lists IRQ8#(instead of IRQ8#/GPI6). The pin list in Table 69 includes both signal names
for the multiplexed pins.
Name
Type
Description
AD[31:0]
I/O
PCI ADDRESS/DATA. AD[31:0] is a multiplexed address and data bus. During the first clock of a transaction,
AD[31:0] contain a physical byte address (32 bits). During subsequent clocks, AD[31:0] contain data.
A PIIX4E Bus transaction consists of an address phase followed by one or more data phases. Little-endian byte
ordering is used. AD[7:0] define the least significant byte (LSB) and AD[31:24] the most significant byte (MSB).
When PIIX4E is a Target, AD[31:0] are inputs during the address phase of a transaction. During the following data
phase(s), PIIX4E may be asked to supply data on AD[31:0] for a PCI read, or accept data for a PCI write.
As an Initiator, PIIX4E drives a valid address on AD[31:2] and 0 on AD[1:0] during the address phase, and drives
write or latches read data on AD[31:0] during the data phase.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
C/BE#[3:0]
I/O
BUS COMMAND AND BYTE ENABLES. The command and byte enable signals are multiplexed on the same PCI
pins. During the address phase of a transaction, C/BE[3:0]# define the bus command. During the data phase C/
BE[3:0]# are used as Byte Enables. The Byte Enables determine which byte lanes carry meaningful data.
C/BE0# applies to byte 0, C/BE1# to byte 1, etc. PIIX4E drives C/BE[3:0]# as an Initiator and monitors C/BE[3:0]#
as a Target.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
CLKRUN#
I/O
CLOCK RUN#. This signal is used to communicate to PCI peripherals that the PCI clock will be stopped. Peripher-
als can assert CLKRUN# to request that the PCI clock be restarted or to keep it from stopping. This function follows
the protocol described in the PCI Mobile Design Guide, Revision 1.0.
During Reset: Low
After Reset: Low
During POS: High
DEVSEL#
I/O
DEVICE SELECT. PIIX4E asserts DEVSEL# to claim a PCI transaction through positive decoding or subtractive
decoding (if enabled). As an output, PIIX4E asserts DEVSEL# when it samples IDSEL active in configuration cycles
to PIIX4E configuration registers. PIIX4E also asserts DEVSEL# when an internal PIIX4E address is decoded or
when PIIX4E subtractively or positively decodes a cycle for the ISA/EIO bus or IDE device. As an input, DEVSEL#
indicates the response to a PIIX4E initiated transaction and is also sampled when deciding whether to subtractively
decode the cycle. DEVSEL# is tri-stated from the leading edge of PCIRST#. DEVSEL# remains tri-stated until
driven by PIIX4E as a target.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
FRAME#
I/O
CYCLE FRAME. FRAME# is driven by the current Initiator to indicate the beginning and duration of an access.
While FRAME# is asserted data transfers continue. When FRAME# is negated the transaction is in the final data
phase. FRAME# is an input to PIIX4E when it is the Target. FRAME# is an output when PIIX4E is the initiator.
FRAME# remains tri-stated until driven by PIIX4E as an Initiator.
During Reset: High-Z
After Reset: High-Z
During POS: High-Z
