UP-5900VS
CIRCUIT DESCRIPTION
5 – 17
Note:
1.
AGP Sideband Addressing Signals. The above table contains two mechanisms to queue requests by the AGP master. Note that the master can
only use one mechanism. When PIPE# is used to queue addresses the master is not allowed to queue addresses using the SBA bus. For exam-
ple, during configuration time, if the master indicates that it can use either mechanism, the configuration software will indicate which mechanism
the master will use. Once this choice has been made, the master will continue to use the mechanism selected until the master is reset (and repro-
grammed) to use the other mode. This change of modes is not a dynamic mechanism but rather a static decision when the device is first being
configured after reset.
2.
PCI signals are redefined when used in AGP transactions carried using AGP protocol extension. For transactions on the AGP interface carried
using PCI protocol these signals completely preserve PCI semantics. The exact role of all PCI signals during AGP transactions is in Table 2-6.
3.
The LOCK# signal is not supported on the AGP interface (even for PCI operations).
4.
PCI signals described in Table 2-4 behave according to PCI 2.1 specifications when used to perform PCI transactions on the AGP Interface.
6) Clocks, Reset, and Miscellaneous
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Clocks, Reset, and Miscellaneous
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Power Management Interface
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Reference Pins
Name
Type
Description
HCLKIN
I
CMOS
Host Clock In: This pin receives a buffered host clock. This clock is used by all of the 82443BX logic that is in the
Host clock domain.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
PCLKIN
I
CMOS
PCI Clock In: This is a buffered PCI clock reference that is synchronously derived by an external clock synthesizer
component from the host clock. This clock is used by all of the 82443BX logic that is in the PCI clock domain.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
DCLKO
O
CMOS
SDRAM Clock Out: 66 or 100 MHz SDRAM clock reference. It feeds an external buffer clock device that produces
multiple copies for the DIMMs.
DCLKWR
I
CMOS
SDRAM Write Clock: Feedback reference from the external SDRAM clock buffer.
This clock is used by the 82443BX when writing data to the SDRAM array.
PCIRST#
I
CMOS
PCI Reset: When asserted, this signal will reset the 82443BX logic. All PCI output and bi-directional signals will also
tri-state compliant to PCI Rev 2.0 and 2.1 specifications.
When SUSTAT# is active, there is an internal 100K ohm pull down on this signal.
GCLKIN
I
CMOS
AGP Clock In: The GCLKIN input is a feedback reference from the GCLKOUT signal.
GCLKO
O
CMOS
AGP Clock Out: The frequency is 66 MHz. The GCLKOUT output is used to feed both the reference input pin on the
82443BX and the AGP compliant device.
CRESET#
O
CMOS
Delayed CPU Reset: CRESET# is a delayed copy of CPURST#. This signal is used to control the multiplexer for the
CPU strap signals. CRESET# is delayed from CPURST# by two host clocks.
Note: This pin requires an external pull-up resistor. If not used, no pull up is required.
TESTIN#
I
CMOS
Test Input: This pin is used for manufacturing, and board level test purposes.
Note: This pin has an internal 50K ohm pull-up.
Name
Type
Description
CLKRUN#
I/OD
CMOS
Primary PCI Clock Run: The 82443BX requests the central resource (PIIX4E) to start or maintain the PCI clock by
the assertion of CLKRUN#. The 82443BX tristates CLKRUN# upon deassertion of PCIRST# (since CLK is running
upon deassertion of reset). If connected to PIIX4E an external 2.7K Ohm pull-up is required for Desktop, Mobile
requires (8.2k 10K) pull-up. Otherwise, a 100 Ohm pull down is required.
SUSTAT#
I
CMOS
Suspend Status (from PIIX): SUSTAT# signals the system suspend state transition from the PIIX4E. It is used to iso-
late the suspend voltage well and enter/exit DRAM self-refresh mode. During POS/STR SUSTAT# is active.
BXPWROK
I
CMOS
BX Power OK: BXPWROK input must be connected to the PWROK signal that indicates valid power is applied to
the 82443BX.
Name
Description
GTLREF[B:A]
GTL Buffer voltage reference input
VTT[B:A]
GTL Threshold voltage for early clamps
VCC
Power pin @ 3.3V
VSS
Ground
REF5V
PCI 5V reference voltage (for 5V tolerant buffers)
AGPREF
External Input Reference
