UP-5900VS
CIRCUIT DESCRIPTION
5 – 22
■
■
■
■
DMA SIGNALS
■
■
■
■
INTERRUPT CONTROLLER/APIC SIGNALS
Name
Type
Description
DACK[0,1,2,3]#
DACK[5,6,7]#
O
DMA ACKNOWLEDGE. The DACK# output lines indicate that a request for DMA service has been granted by
PIIX4E or that a 16-bit master has been granted the bus. The active level (high or low) is programmed via the DMA
Command Register. These lines should be used to decode the DMA slave device with the IOR# or IOW# line to indi-
cate selection. If used to signal acceptance of a bus master request, this signal indicates when it is legal to assert
MASTER#. If the DREQ goes inactive prior to DACK# being asserted, the DACK# signal will not be asserted.
During Reset: High
After Reset: High
During POS: High
DREQ[0,1,2,3]
DREQ[5,6,7]
I
DMA REQUEST. The DREQ lines are used to request DMA service from PIIX4Efs DMA controller or for a 16-bit
master to gain control of the ISA expansion bus. The active level (high or low) is programmed via the DMA Com-
mand Register. All inactive to active edges of DREQ are assumed to be asynchronous. The request must remain
active until the appropriate DACKx# signal is asserted.
REQ[A:C]#/
GPI[2:4]
I
PC/PCI DMA REQUEST. These signals are the DMA requests for PC/PCI protocol. They are used by a PCI agent
to request DMA services and follow the PCI Expansion Channel Passing protocol as defined in the PCI DMA sec-
tion.
If the PC/PCI request is not needed, these pins can be used as general-purpose inputs.
GNT[A:C]#/
GPO[9:11]
O
PC/PCI DMA ACKNOWLEDGE. These signals are the DMA grants for PC/PCI protocol. They are used by a PIIX4E
to acknowledge DMA services and follow the PCI Expansion Channel Passing protocol as defined in the PCI DMA
section.
If the PC/PCI request is not needed, these pins can be used as general-purpose outputs.
During Reset: High
After Reset: High
During POS: High/GPO
TC
O
TERMINAL COUNT. PIIX4E asserts TC to DMA slaves as a terminal count indicator. PIIX4E asserts TC after a new
address has been output, if the byte count expires with that transfer. TC remains asserted until AEN is negated,
unless AEN is negated during an autoinitialization. TC is negated before AEN is negated during an autoinitialization.
During Reset: Low
After Reset: Low
During POS: Low
Name
Type
Description
APICACK#/
GPO12
O
APIC ACKNOWLEDGE. This active low output signal is asserted by PIIX4E after its internal buffers are flushed in
response to the APICREQ# signal. When the I/O APIC samples this signal asserted it knows that PIIX4Efs buffers
are flushed and that it can proceed to send the APIC interrupt. The APICACK# output is synchronous to PCICLK.
If the external APIC is not used, then this is a general-purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
APICCS#/
GPO13
O
APIC CHIP SELECT. This active low output signal is asserted when the APIC Chip Select is enabled and a PCI orig-
inated cycle is positively decoded within the programmed I/O APIC address space.
If the external APIC is not used, this pin is a general-purpose output.
During Reset: High
After Reset: High
During POS: High/GPO
APICREQ#/
GPI5
I
APIC REQUEST. This active low input signal is asserted by an external APIC device prior to sending an interrupt
over the APIC serial bus. When PIIX4E samples this pin active it will flush its F-type DMA buffers pointing towards
PCI.
Once the buffers are flushed, PIIX4E asserts APICACK# which indicates to the external APIC that it can proceed to
send the APIC interrupt. The APICREQ# input must be synchronous to PCICLK.
If the external APIC is not used, this pin is a general-purpose input.
INTR
OD
INTERRUPT.
IRQ0/
GPO14
O
INTERRUPT REQUEST 0. This output reflects the state of the internal IRQ0 signal from the system timer.
If the external APIC is not used, this pin is a general-purpose output.
During Reset: Low
After Reset: Low
During POS: IRQ0/GPO
IRQ1
I
INTERRUPT REQUEST 1. IRQ1 is always edge triggered and can not be modified by software to level sensitive. A
low to high transition on IRQ1 is latched by PIIX4E.
IRQ1 must remain asserted until after the interrupt is acknowledged. If the input goes inactive before this time, a
default IRQ7 is reported in response to the interrupt acknowledge cycle.
IRQ 3:7, 9:11,
14:15
I
INTERRUPT REQUESTS 3:7, 9:11, 14:15. The IRQ signals provide both system board components and ISA Bus I/
O devices with a mechanism for asynchronously interrupting the CPU. These interrupts may be programmed for
either an edge sensitive or a high level sensitive assertion mode. Edge sensitive is the default configuration.
An active IRQ input must remain asserted until after the interrupt is acknowledged. If the input goes inactive before
this time, a default IRQ7 is reported in response to the interrupt acknowledge cycle.
IRQ8#/
GPI6
I/O
IRQ 8#. IRQ8# is always an active low edge triggered interrupt and can not be modified by software.
IRQ8# must remain asserted until after the interrupt is acknowledged. If the input goes inactive before this time, a
default IRQ7 is reported in response to the interrupt acknowledge cycle.
If using the internal RTC, then this can be programmed as a general-purpose input. If enabling an APIC, this signal
becomes an output and must not be programmed as a general purpose input.
IRQ9OUT#/
GPO29
O
IRQ9OUT#. IRQ9OUT# is used to route the internally generated SCI and SMBus interrupts out of the PIIX4E for
connection to an external IO APIC. If APIC is disabled, this signal pin is a General Purpose Output.
During Reset: High
After Reset: High
During POS: IRQ9OUT#/GPO
