UP-5900VS
CIRCUIT DESCRIPTION
5 – 43
(3) RS232 Interface
2 UARTs (8250) for RS232 are incorporated in the PSC2 as a Mega
Macro Function. UART1 and 2 are decoded as follows by the setting of
bit 7 of the SSR0 register.
Bit 7: CMOS (decode control of UART1 and 2)
The assignment of interrupt can be freely defined using system SW6 of
special system register 0 and the assign register.
The hardware configuration conforms to the RS232 of AT specifica-
tions.
(4) Drawer Interface
The I/O port driving the drawer solenoid is composed of the internal
gates of PSC2.
When power off (ACL signal = “0”) is detected, each output port is pre-
set and the driving of the drawer solenoid is immediately stopped.
The driving time of the drawer solenoid is automatically set to 45ms by
the hardware timer control after turning each drive port ON.
(5) CKDC Interface
As previously defined, the CKDC interface, is 2 sets of 8-bit serial inter-
face is incorporated in the PSC2. This interface is composed of an 8-bit
parallel-in/parallel-out shift register and a SCKF register for generating
shift clock. Also CKDCRES1/2 signals (reset of CKDC) and SHEN1/2#
signals (shift enable signal) must be prepared as CKDC interface. How-
ever SHEN1/2# are used in the PSC2 as dedi-cated signal pins input-
ting interrupt events.
SCKF is outputted to SCK pin without the logic changed and preset to
“1” by RESET. The serial data is in the form of LSB first. SCKF operates
with synchronized with SCK, and the operation speed depends on the
speed of CPU because the shift operation needs to clear and set SCKF
by software control for each bit.
STH is shifted in by the rising of SCK, and shifted out by the falling of
SCK. The shift-in and shift-out have a margin to the delay of line
because of 1/2 bit of phase difference.
(6) Timer Counter
The PSC2 incorporates 2 8-bit hardware free run counters necessary to
control dedicated devices. This 8-bit counter can be read or written as
TCNT register 0 and 1, counted up by input clock. This input clock is
selected using CLOCK SELECT (2 bits respectively) of the TCR regis-
ter. When TCNT0 is equal to the value of timer compare con-stant reg-
ister (TCC0), compare match signal can be generated and a maskable
interrupt can be generated. Also when TCNT1 is equal to TCC1, com-
pare match signal can be generated and a maskable interrupt can be
generated. When the TCNT0 overflows, an overflow signal can be gen-
erated and a maskable interrupt can be generated.
Types of internal timer interrupt
IS14: TINT0# (timer compare match interrupt 0)
IS13: TINT1# (timer compare match interrupt 1)
IS12: TOINT# (timer overflow interrupt)
(7) MCR Interface
This interface has 2 channels containing 96 bytes of FIFO respective-ly.
Read data are stored in the FIFO. Each channel functions inde-pen-
dently, so the 2 channels can be read simultaneously.
Description of Read Operation
1) The MCR interface goes into the status of waiting for reading a card
after the following settings are performed by the main CPU.
• Setting a mode: Sets a mode corresponding to the standard of
the handled card (JBA/ABA/IATA).
• Setting a start mark: Sets a start mark corresponding to the stan-
dard of the card.
• Resetting the interrupt: Resets the interrupt because no card can
be read when any interrupt is active.
2) After a card is scanned, the MCR interface changes serial data of
the MCR to parallel data. Changed data is written in the FIFO buffer
at every character in order from the start mark to the LRC.
The FIFO buffer has the capacity of 96 bytes, and the number of
characters in a card corresponding to each standard is as follows:
JBA (JIS II type): 72 characters maximum (8 bits a character)
ABA (MEGA MACRO FUNCTION II type second track): 40
characters maximum (5 bits a character)
IATA (JIS I type first track): 79 characters maximum (7 bits a
character)
The 2 FIFOs are prepared independently to 2 channels of inter-
face.
These FIFOs can be read simultaneously when connected to a
MCR corresponding to JBA/ABA or IATA/ABA.
SW7=1: DOS compatible COM3/COM4 mode (initial value)
COM3: 3E8H to 3EFH (8-byte address)
COM4: 2E8H to 2EFH (8-byte address)
SW7=0: Unique decode mode
Unique: PSC2+410H (16-byte address)
i.e. UART1 unit: PSC2+(410-417H)
UART2 unit: PSC2+(418-41FH)
HTS
(SERIAL OUTPUT)
HTS
(SHIFT CLOCK)
OUTPUT
F/F
SCKF
Q
D
CL
CK
8 BIT SHIFT REG.
DATA BUS
SCKFCS
RESET
STH
(SERIAL INPUT)
SDRCS
CLOCK
CKS
INTERUPT
DATA BUS
CLOCK
CKS
CLOCK SELECT
MATCH1
OVF
CONTOROL
LOGIC
MATCH0
CLOCK SELECT
DATA BUS
TCC0
COMPARE MATCH
TCC1
COMPARE MATCH
TCNT0
8BIT COMPARE
TCNT1
8BIT COMPARE
