UP-5900VS
CIRCUIT DESCRIPTION
5 – 47
18. LAN CONTROLLER
RealTak’s RTL8139C is used.
18-1. PIN ASSIGNMENTS
18-2. PIN DISCRIPTION
1) POWER MANAGEMENT/ISOLATION INTERFACE
1 VDD
2 CBE3B
3 IDSEL
4 AD23
5 AD22
6 AD21
7 GND
8 AD20
9 AD19
10 AD18
11 AD17
12 VDD
13 AD16
14 CBE2B
RTL8139C(L)
64 MA10
63 MA9
62 GND
61 MA8
60 MA7
59 VDD
58 VDD
57 MA6/9356SEL
56 GND
55 GND
53 MA5
52 MA4
51 MA3
49 MA2
48 MA1
47 MA0
46 VDD
45 AD0
44 AD1
43 AD2
42 AD3
41 AD4
40 GND
39 AD5
17 TRDYB
18 GND
19 DEVSELB
20 STOPB
21 PERRB
22 SERRB
23 PAR
24 CBE1B
25 VDD
26 AD15
27 AD14
28 AD13
29 AD12
30 GND
31 AD11
32 AD10
33 AD9
34 AD8
35 VDD
36 CBE0B
37 AD7
38 AD6
103 MD4
104 MD3
105 MD2
106 VDD
107 MD1
108 MD0
109 VDD
110 ROMCSB
111 GND
112 GND
113 GND
114 INTAB
115 RSTB
116 CLK
117 GNTB
118 REQB
119 VDD
120 AD31
121 AD30
122 AD29
123 AD28
124 GND
125 AD27
126 AD26
127 AD25
128 AD24
65 MA11
66 MA12
67 MA13
68 MA14
69 MA15
70 MA16
71 NC
72 NC
73 NC
74 GND
75 CLKRUNB
76 PMEB
77 VDD
78 X2
79 X1
80 GND
81 RTT3
82 RTT2
83 LWAKE/CSTSCHG
84 RTSET
85 GND
86 RXIN-
87 RXIN+
88 OEB
89 WEB
90 VDD
91 TXD-
92 TXD+
93 GND
94 NC
95 ISOLATEB
96 VDD
97 LED2
98 LED1
99 LED0
101 MD6
102 MD5
100 MD7
16 IRDYB
15 FRAMEB
54 NC
50 EECS
Symbol
Type
Pin No
Description
PMEB
(PME#)
O/D
76
Power Management Event: Open drain, active low. Used by the RTL8139C(L) to request a change
in its current power management state and/or to indicate that a power management event has
occurred.
ISOLATEB
(ISOLATE#)
I
95
Isolate pin: Active low. Used to isolate RTL8139C(L) from the PCI bus. The RTL8139C(L) does
not drive its PCI outputs (excluding PME#) and does not sample its PCI input (including RST# and
PCICLK) as long as Isolate pin is asserted.
LWAKE/
CSTSCHG
O
83
LAN WAKE-UP signal (When CardB_En=0, bit2 Config3): This signal is used to inform mother-
board to execute wake-up process. The motherboard must support Wake-On-LAN (WOL). There
are 4 choices of output, including active high, active low, positive pulse, and negative pulse, that
may be asserted from the LWAKE pin. Please refer to LWACT bit in CONFIG1 register and
LWPTN bit in CONFIG4 register for the setting of this output signal. The default output is an active
high signal. Once there is a PME event having come in, the LWAKE and PMEB assert at the same
time when the LWPME (bit4, CONFIG4) is set to 0. If the LWPME is set to 1, the LWAKE asserts
only when the PMEB asserts and the ISOLATEB is low.
CSTSCHG signal (When CardB_En=1, bit2 Config3): This signal is used in CardBus application
only and is used to inform motherboard to execute wake-up process whenever there is PME event
occurs. This is always an active high signal, the setting of LWACT (bit 4, Config1), LWPTN (bit2,
Config4), and LWPME (bit4, Config4) means nothing in this case.
This pin is a 3.3V signaling output pin.
