UP-5900VS
CIRCUIT DESCRIPTION
5 – 10
INIT#
I
The INIT# (Initialization) signal, when asserted, resets integer registers inside all processors without affecting their
internal (L1) caches or floating-point registers.
Each processor then begins execution at the power-on Reset vector configured during power-on configuration. The
processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must con-
nect the appropriate pins of all bus agents.
If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-
Test (BIST).
LINT[1:0]
I
The LINT[1:0] (Local APIC Interrupt) signals must connect the appropriate pins of all APIC Bus agents, including all
processors and the core logic or I/O APIC component. When the APIC is disabled, the LINT0 signal becomes INTR, a
maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward
compatible with the signals of those names on the Pentium processor. Both signals are asynchronous.
Both of these signals must be software configured via BIOS programming of the APIC register space to be used either
as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is
the default configuration.
LOCK#
I/O
The LOCK# signal indicates to the system that a transaction must occur atomically.
This signal must connect the appropriate pins of all system bus agents. For a locked sequence of transactions, LOCK#
is asserted from the beginning of the first transaction end of the last transaction.
When the priority agent asserts BPRI# to arbitrate for ownership of the system bus, it will wait until it observes LOCK#
deasserted. This enables symmetric agents to retain ownership of the system bus throughout the bus locked operation
and ensure the atomicity of lock.
PICCLK
I
The PICCLK (APIC Clock) signal is an input clock to the processor and core logic or I/O APIC which is required for
operation of all processors, core logic, and I/O APIC components on the APIC bus.
PICD[1:0]
I/O
The PICD[1:0] (APIC Data) signals are used for bidirectional serial message passing on the APIC bus, and must con-
nect the appropriate pins of the Intel Celeron processor for proper initialization.
PLL1, PLL2
(PGA packages only)
I
All Intel Celeron processors have internal analog PLL clock generators that require quiet power supplies. PLL1 and
PLL2 are inputs to the internal PLL and should be connected to VCCCORE through a low-pass filter that minimizes jit-
ter.
PRDY#
O
The PRDY (Probe Ready) signal is a processor output used by debug tools to determine processor debug readiness.
PREQ#
I
The PREQ# (Probe Request) signal is used by debug tools to request debug operation of the processors.
PWRGOOD
I
The PWRGOOD (Power Good) signal is a 2.5 V tolerant processor input. The processor requires this signal to be a
clean indication that the clocks and power supplies (VCCCORE, etc.) are stable and within their specifications. Clean
implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the
power supplies are turned on until they come within specification. The signal must then transition monotonically to a
high (2.5 V) state.
Figure 39 illustrates the relationship of PWRGOOD to other system signals.
PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising
edge of PWRGOOD. It must also meet the minimum pulse width specification in Table 17 and Table 18, and be fol-
lowed by a 1ms RESET# pulse.
The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage
sequencing issues. It should be driven high throughout boundary scan operation.
PWRGOOD Relationship at Power-On
REQ[4:0]#
I/O
The REQ[4:0]# (Request Command) signals must connect the appropriate pins of all processor system bus agents.
They are asserted by the current bus owner over two clock cycles to define the currently active transaction type.
RESET#
I
Asserting the RESET# signal resets the processor to a known state and invalidates the L1 cache without writing back
any of the contents. RESET# must stay active for at least one millisecond after VCCCORE and CLK have reached their
proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks.
A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. These
configuration options are described in the Pentium Pro Family Developerfs Manual, Volume 1: Specifications (Order
Number 242690).
The processor may have its outputs tristated via power-on configuration. Otherwise, if INIT# is sampled active during
the active-to-inactive transition of RESET#, the processor will execute its Built-in Self-Test (BIST). Whether or not BIST
is executed, the processor will begin program execution at the power on Reset vector (default 0_FFFF_FFF0h).
RESET# must connect the appropriate pins of all processor system bus agents.
RS[2:0]#
I
The RS[2:0]# (Response Status) signals are driven by the response agent (the agent responsible for completion of the
current transaction), and must connect the appropriate pins of all processor system bus agents.
RTTCTRL
I
The RTTCTRL input signal provides AGTL+ termination control. The Celeron FC-PGA processor samples this input to
sense the presence of motherboard AGTL+ termination.
SLEWCTRL
I
The SLEWCTRL input signal provides AGTL+ slew rate control. The Celeron FC-PGA processor samples this input to
determine the slew rate for AGTL+ signals when it is the driving agent.
Signal
Type
Description
BCLK
PWRGOOD
RESET#
1 ms
VCC
CORE
,
V
REF
