Samsung S3C2500B, User Manual

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32-BIT TIMERS S3C2500B
17-6
17.6.2 TIMER DATA REGISTERS
The timer data registers, TDATA0 - TDATA5, contain a value that specifies the time-out duration for each timer.
The formula for calculating the time-out duration is: (Timer data) cycles.
The timer is dependent on the system bus clock. When the system bus is 133 MHz, the minimum value, 0x1 for
TDATA, generates interrupt at every 7.5n sec. It takes about 32.2 sec for TDATA to go from 0x0 to
0xFFFFFFFF.
Although TOUT signal is designed to come out whenever time-out occurs, it is possible for TOUT signal not to
work properly for some TDATA values when interrupt is enabled. The reason is that ARM940T spends the
specific time to reach interrupt service routine after time-out takes place. The elapsed time from time-out to
interrupt service routine is approximately 27 cycles (200n sec, at 133 MHz). Therefore, TDATA should be set to
the bigger value than ‘0x1A’, to avoid another time-out, while it is carrying out the process between time-out and
interrupt routine.
Table 17-2. TDATA0 - TDATA5 Registers
Register Address R/W Description Reset Value
TDATA0 0xF0040010 R/W Timer 0 data register 0x00000000
TDATA1 0xF0040018 R/W Timer 1 data register 0x00000000
TDATA2 0xF0040020 R/W Timer 2 data register 0x00000000
TDATA3 0xF0040028 R/W Timer 3 data register 0x00000000
TDATA4 0xF0040030 R/W Timer 4 data register 0x00000000
TDATA5 0xF0040038 R/W Timer 5 data register 0x00000000
31 0
Timer Data
[31:0] Timer 0-5 data value
Figure 17-4. Timer Data Registers (TDATA0 - TDATA5)