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S3C2500B

SYSTEM CONFIGURATION

4-5

TIC

Group A

ARM940T

Group B

Group C

General

DMA

Ethernet

Controller 0

Ethernet

Controller 1

HDLC

Controller 2

HDLC

Controller 1

HDLC

Controller 0

Figure 4-3. Priority Groups of S3C2500B

AHB Bus Programmable Priority Register are HPRIF(Programmable Priority Register for Fixed) and HPRIR
(Programmable Priority Register for Round-Robin).

If system configuration register (0xF0000000) SYSCFG[0] = 0x1, the programmable fixed priority is run by
HPRIF register. Each Master has its own fixed priority index. For example, GDMA has the index 0. The reset
value of HPRIF register is 0x00543210. The first field of HPRIF[3:0] indicates the highest priority. So, the GDMA
has the highest AHB master when SYSCFG[0] = 0x1 and the HPRIF has the reset value. For example,
SYSCFG[0] = 0x1 and the HPRIF is 0x00432501, the fixed priority order from the highest to the lowest is
Ethernet Controller 0, General DMA, HDLC Controller 2, Ethernet Controller 1, HDLC Controller 0, and HDLC
Controller 1.

If system configuration register (0xF0000000) SYSCFG[0] = 0x0, the programmable round-robin priority is run by
HPRIR register. All AHB bus masters own their respective field position in HPRIR. The ratio of the bus occupancy
can be programmed by writing an arbitrary value on each field. The arbitrary value can be 0x0 to 0xF.
The ratio of the bus occupancy of the bus master in the first field is
(1)/((1)+(1)+(1)+(1)+(1)+(1)). The reset value of HPRIR register
is 0x00000000. So each master has the same bus occupancy ratio when SYSCFG[0] = 0x0 and the HPRIR has
the reset value. For example, SYSCFG[0] = 0x0 and the HPRIR is 0x0011F001, the expected ratios of the bus
occupancy of the bus masters, General DMA, Ethernet Controller 0, Ethernet Controller 1, HDLC Controller 0,
HDLC Controller 1, and HDLC Controller 2, are 2/24, 1/24, 1/24, 16/24, 2/24, and 2/24, respectively.

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Summary of Contents for S3C2500B

Page 1: ...21 S3C2500B 032003 USER S MANUAL S3C2500B 32 Bit RISC Microprocessor Revision 1 查询S3C2500B供应商捷多邦专业PCB打样工厂 24小时加急出货 ...

Page 2: ...S3C2500B 32 BIT RISC MICROPROCESSOR USER S MANUAL Revision 1 ...

Page 3: ...cations intended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors har...

Page 4: ... 7 2 7 4 Accessing Hi Registers in THUMB State 2 8 2 8 The Program Status Registers 2 8 2 8 1 The Condition Code Flags 2 9 2 8 2 The Control Bits 2 9 2 9 Exceptions 2 11 2 9 1 Action on Entering an Exception 2 11 2 9 2 Action on Leaving an Exception 2 11 2 9 3 Exception Entry Exit Summary 2 12 2 9 4 FIQ 2 12 2 9 5 IRQ 2 13 2 9 6 Abort 2 13 2 9 7 Software Interrupt 2 14 2 9 8 Undefined Instruction ...

Page 5: ... CMN Opcodes 3 16 3 5 7 Instruction Cycle Times 3 17 3 6 8 Assembler Syntax 3 17 3 6 PSR Transfer MRS MSR 3 19 3 6 1 Operand Restrictions 3 19 3 6 2 Reserved Bits 3 21 3 6 3 Instruction Cycle Times 3 21 3 6 4 Assembler Syntax 3 22 3 7 Multiply and Multiply Accumulate MUL MLA 3 23 3 7 1 CPSR Flags 3 24 3 7 2 Instruction Cycle Times 3 24 3 7 3 Assembler Syntax 3 24 3 8 Multiply Long and Multiply Acc...

Page 6: ...e Register List 3 44 3 11 7 Data Aborts 3 44 3 11 8 Instruction Cycle Times 3 44 3 11 9 Assembler Syntax 3 45 3 12 Single Data Swap SWP 3 47 3 12 1 Bytes and Words 3 47 3 12 2 Use of R15 3 47 3 12 3 Data Aborts 3 48 3 12 4 Instruction Cycle Times 3 48 3 12 5 Assembler Syntax 3 48 3 13 Software Interrupt SWI 3 49 3 13 1 Return from the Supervisor 3 49 3 13 2 Comment Field 3 49 3 13 3 Instruction Cy...

Page 7: ...3 19 2 Opcode Summary 3 65 3 20 Format 1 Move Shifted Register 3 67 3 20 1 Operation 3 67 3 20 2 Instruction Cycle Times 3 67 3 21 Format 2 Add Subtract 3 68 3 21 1 Operation 3 68 3 21 2 Instruction Cycle Times 3 69 3 22 Format 3 Move Compare Add Subtract Immediate 3 70 3 22 1 Operations 3 70 3 22 2 Instruction Cycle Times 3 70 3 23 Format 4 ALU Operations 3 71 3 23 1 Operation 3 71 3 23 2 Instruc...

Page 8: ...87 3 32 2 Instruction Cycle Times 3 87 3 33 Format 14 Push Pop Registers 3 88 3 33 1 Operation 3 88 3 33 2 Instruction Cycle Times 3 89 3 34 Format 15 Multiple Load Store 3 90 3 34 1 Operation 3 90 3 34 2 Instruction Cycle Times 3 90 3 35 Format 16 Conditional Branch 3 91 3 35 1 Operation 3 91 3 35 2 Instruction Cycle Times 3 92 3 36 Format 17 Software Interrupt 3 93 3 36 1 Operation 3 93 3 36 2 I...

Page 9: ...6 AHB Bus Master Priority Register 4 21 4 9 7 Core PLL Control Register 4 22 4 9 8 System Bus PLL Control Register 4 23 4 9 9 USB PLL Control Register 4 24 4 9 10 PHY PLL Control Register 4 24 Chapter 5 Memory Controller 5 1 Overview 5 1 5 2 Features 5 2 5 3 Memory Map 5 3 5 4 Bus Interface Signals 5 5 5 5 Endian Modes 5 7 5 6 Ext I O Bank Controller 5 13 5 6 1 Features 5 13 5 6 2 External Device ...

Page 10: ...6 5 5 Interrupt Pending Register 6 12 Chapter 7 Ethernet Controller 7 1 Overview 7 1 7 2 Features 7 2 7 3 MAC Function Blocks 7 3 7 3 1 Media Independent Interface MII 7 3 7 3 2 Physical Layer Entity PHY 7 4 7 3 3 Buffered Dma Interface BDI 7 4 7 3 4 The MAC Transmitter Block 7 4 7 3 5 The MAC Receiver Block 7 6 7 3 6 Flow Control Block 7 7 7 3 7 Buffered DMA BDMA Overview 7 7 7 4 Ethernet Control...

Page 11: ...ffer Descriptor 8 20 8 6 Buffer Descriptor 8 21 8 6 1 Transmit Buffer Descriptor 8 21 8 6 2 Receive Buffer Descriptor 8 22 8 7 HDLC Special Registers 8 24 8 7 1 HDLC Global Mode Register 8 27 8 7 2 HDLC Control Register 8 30 8 7 3 HDLC Status Register 8 36 8 7 4 Summary 8 36 8 7 5 HDLC Interrupt Enable Register 8 42 8 7 6 HDLC Tx Fifo 8 44 8 7 7 HDLC Rx Fifo 8 45 8 7 8 HDLC Brg Time Constant Regis...

Page 12: ...9 10 9 4 4 Operation 9 10 9 5 IOM2 Special Registers 9 11 9 5 1 IOM2CON Register 9 12 9 5 2 IOM2 Status Register 9 14 9 5 3 IOM2 Interrupt Enable Register 9 16 9 5 4 IOM2 TIC Bus Address Register 9 18 9 5 5 IOM2 IC Channel Transmit Data Register 9 19 9 5 6 IOM2 C I0 Channel Transmit Data Register 9 20 9 5 7 IOM2 C I1 Channel Transmit Data Register 9 21 9 5 8 IOM2 C I1 Channel Receive Data Register...

Page 13: ...on Address Register 10 10 10 5 2 USB Power Management Register 10 12 10 5 3 USB Interrupt Register 10 14 10 5 4 USB Interrupt Enable Register 10 17 10 5 5 USB Frame Number Register 10 19 10 5 6 USB Disconnect Timer Register 10 20 10 5 7 USB Endpoint 0 Common Status Register 10 22 10 5 8 USB Endpoint 1 Common Status Register 10 25 10 5 9 USB Endpoint 2 Common Status Register 10 30 10 5 10 USB Endpo...

Page 14: ... 12GDMA Controller 12 1 Overview 12 1 12 2 Feature 12 1 12 3 GDMA Special Registers 12 3 12 3 1 GDMA Programmable Priority Registers 12 4 12 3 2 GDMA Control Registers 12 9 12 3 3 GDMA Source Destination Address Registers 12 12 12 3 4 GDMA Transfer Count Registers 12 13 12 3 5 GDMA Run Enable Registers 12 14 12 3 6 GDMA Interrupt Pending Register 12 15 12 4 GDMA Mode Operation 12 16 12 4 1 Softwar...

Page 15: ...ed UART Transmit Buffer Register 14 16 14 3 5 High Speed UART Receive Buffer Register 14 17 14 3 6 High Speed UART Baud Rate Divisor Register 14 18 14 3 7 High Speed UART Baud Rate Examples 14 19 14 3 8 High Speed UART Control Character 1 Register 14 20 14 3 9 High Speed UART Control Character 2 Register 14 21 14 3 10 High Speed UART Autoband Boundary Register 14 22 14 3 11 High Speed UART Autobau...

Page 16: ...r 1732 bit Timers 17 1 Overview 17 1 17 2 Feature 17 1 17 3 Interval Mode Operation 17 2 17 4 Toggle Mode Operation 17 2 17 5 Timer Operation Guidelines 17 3 17 6 Timer Special Register 17 4 17 6 1 Timer Mode Register 17 4 17 6 2 Timer Data Registers 17 6 17 6 3 Timer Count Registers 17 7 17 6 4 Timer Interrupt Clear Registers 17 8 17 6 5 Watchdog Timer Register 17 9 Chapter 18Electrical Data 18 1...

Page 17: ......

Page 18: ...ht 3 13 3 8 Arithmetic Shift Right 3 13 3 9 Rotate Right 3 14 3 10 Rotate Right Extended 3 14 3 11 PSR Transfer 3 20 3 12 Multiply Instructions 3 23 3 13 Multiply Long Instructions 3 25 3 14 Single Data Transfer Instructions 3 28 3 15 Little Endian Offset Addressing 3 30 3 16 Half word and Signed Data Transfer with Register Offset 3 34 3 17 Half word and Signed Data Transfer with Immediate Offset ...

Page 19: ... Groups of S3C2500B 4 5 4 4 AHB Programmable Priority Registers 4 6 4 5 Shows the Clock Generation Logic of the S3C2500B 4 14 4 6 Divided System Clock Timing Diagram 4 19 5 1 Memory Bank Address map 5 4 5 2 Memory Controller Bus Signals 5 6 5 3 8 bit ROM SRAM and Flash Basic Connection 5 14 5 4 8 bit ROM SRAM and Flash Basic Connection 8 bit Memory x 2 5 15 5 5 16 bit SRAM Basic Connection 5 16 5 ...

Page 20: ...st Read Operation CAS Latency 3 5 58 5 32 Burst Write Operation 5 59 6 1 I2C Block Diagram 6 1 6 2 Master Transmitter and Slave Receiver 6 3 6 3 Master Receiver and Slave Transmitter 6 4 6 4 Start and Stop Conditions 6 5 6 5 Data Transfer Format 6 7 6 6 I2C Control Status Register 6 10 7 1 Ethernet Diagram 7 1 7 2 Data Structure of Tx Buffer Descriptor 7 10 7 3 Data Structure of Rx Buffer Descript...

Page 21: ...FIFO Function Diagram 8 45 8 19 HDLC BRG Time Constant Register 8 46 8 20 HDLC Preamble Constant Register 8 47 8 21 Address Recognition 8 48 8 22 HDLC Station Address and HMASK Register 8 49 8 23 DMA Tx Buffer Descriptor Pointer 8 49 8 24 DMA Rx Buffer Descriptor Pointer 8 50 8 25 Maximum Frame Length Register 8 50 8 26 DMA Receive Buffer Size Register 8 51 8 27 HDLC Synchronization Register 8 51 ...

Page 22: ...2 Strobe Register 9 26 10 1 SOF Packets 10 3 10 2 USB 1 1 Frame Model 10 4 10 3 USB Frame Format 10 5 10 4 USB Core Block Diagram 10 7 10 5 SIE Block Diagram 10 8 10 6 USBFA Register 10 11 10 7 USBPM Register 10 13 10 8 USBINTR Register 10 16 10 9 USBINTRE Register 10 18 10 10 USBFN Register 10 19 10 11 USBDISCONN Register 10 21 10 12 USBEP0CSR Register 10 24 10 13 USBEP1CSR Register 10 29 10 14 U...

Page 23: ...sole UART Interrupt Enable Register 13 12 13 6 Console UART Transmit Data Register 13 13 13 7 Console UART Receive Data Register 13 14 13 8 Console UART Baud Rate Divisor Register 13 15 13 9 Console UART Baud Rate Generator BRG 13 16 13 10 Console UART Control Character 1 Register 13 17 13 11 Console UART Control Character 2 Register 13 17 13 12 Interrupt Based Serial I O Transmit and Receive Timi...

Page 24: ...g Diagram Normal High Speed UART 14 29 14 23 Infra Red Transmit Mode Frame Timing Diagram 14 29 14 24 Infra Red Receive Mode Frame Timing Diagram 14 30 15 1 I O Port Mode Registers 1 2 15 4 15 2 I O Function Control Register 1 15 6 15 3 I O Function Control Register 2 15 7 15 4 I O Port Control Register for GDMA 15 8 15 5 I O Port Control Register for External Interrupt 15 10 15 6 I O Port Externa...

Page 25: ......

Page 26: ...1 1 43 1 19 S3C2500B I O Port Controller 1 43 1 20 S3C2500B Interrupt Controller 1 44 1 21 S3C2500B Timer Controller 1 45 2 1 PSR Mode Bit Values 2 10 2 2 Exception Entry Exit 2 12 2 3 Exception Vectors 2 14 2 4 ARM9TDMI Implementation Option 2 19 2 5 CP15 Register Map 2 21 2 6 ID Code Register 2 21 2 7 Cache Type Register Format 2 22 2 8 CP15 Register 1 2 23 2 9 Clocking Modes 2 23 2 10 Cacheable...

Page 27: ...elative Load Instruction 3 76 3 14 Summary of Format 7 Instructions 3 77 3 15 Summary of format 8 instructions 3 79 3 16 Summary of Format 9 Instructions 3 81 3 17 Half word Data Transfer Instructions 3 83 3 18 SP Relative Load Store Instructions 3 84 3 19 Load Address 3 85 3 20 The ADD SP Instruction 3 87 3 21 PUSH and POP Instructions 3 88 3 22 The Multiple Load Store Instructions 3 90 3 23 The ...

Page 28: ...le Endian 5 12 5 14 External 8 bit Load Operation with Little Endian 5 12 5 15 Ext I O Bank Controller Special Registers 5 21 5 16 Bank n Control BnCON Register 5 23 5 17 Muxed Bus Control Register 5 25 5 18 WAIT Control Register 5 27 5 19 Supported SDRAM Configuration of 32 bit External Bus 5 40 5 20 Supported SDRAM Configuration of 16 bit External Bus 5 41 5 21 SDRAM Address Mapping of 32 bit Ex...

Page 29: ...AC Transmit Interrupt Enable Register Description 7 19 7 18 BMTXSTAT Register 7 20 7 19 BDMA MAC Transmit Interrupt Status Register Description 7 20 7 20 BMRXINTEN Register 7 21 7 21 BDMA MAC Receive Interrupt Enable Register Description 7 21 7 22 BMRXSTAT Register 7 22 7 23 BDMA MAC Receive Interrupt Status Register Description 7 22 7 24 BDMARXLEN Register 7 23 7 25 BDMA Receive Frame Size Regist...

Page 30: ...l B Special Registers 8 25 8 6 HDLC Channel C Special Registers 8 26 8 7 HMODEA HMODEB and HMODEC Register 8 27 8 8 HMODE Register Description 8 27 8 9 HCONA HCONB and HCONC Register 8 30 8 10 HCON Register Description 8 30 8 11 HSTATA HSTATB and HSTATC Register 8 36 8 12 HSTAT Register Description 8 37 8 13 HINTENA HINTENB and HINTENC Register 8 42 8 14 HINTEN Register Description 8 42 8 15 HBRGT...

Page 31: ...nitor Channel Transmit Data Register 9 22 9 14 IOM2MRD IOM2 Monitor Channel Receive Data Register 9 22 9 15 TSAACON TSA A Control Register 9 23 9 16 TSABCON TSA B Control Register 9 24 9 17 TSACCON TSA C Control Register 9 25 9 18 IOM2STRB Strobe Register 9 26 10 1 USB Registers 10 9 10 2 USBFA Register 10 10 10 3 USBFA Register Description 10 10 10 4 USBPM Register 10 12 10 5 USBPM Register Descr...

Page 32: ...1 4 DES 3DES Interrupt Enable Register Description 11 6 11 5 DES 3DES Run Enable Register Description 11 6 11 6 DES 3DES Key1 Left Side Register Description 11 6 11 7 DES 3DES Key 1 Right Side Register Description 11 6 11 8 DES 3DES Key 2 Left Side Register Description 11 7 11 9 DES 3DES Key 2 Right Side Register Description 11 7 11 10 DES 3DES Key 3 Left Side Register Description 11 7 11 11 DES 3...

Page 33: ...3 16 13 14 CUCHAR 1 2 Registers 13 17 14 1 High Speed UART 0 Special Registers Overview 14 3 14 2 High Speed UART 1 Special Registers Overview 14 3 14 3 High Speed UART Control Registers 14 4 14 4 High Speed UART Control Register Description 14 4 14 5 High Speed UART Status Registers 14 9 14 6 High Speed UART Status Register Description 14 9 14 7 HUCON Interrupt Enable Registers 14 14 14 8 High Sp...

Page 34: ... INTMASK EXTMASK Register 16 5 16 5 Interrupt Priority Register 16 8 16 6 INTOFFSET_FIQ INTOFFSET_IRQ Register 16 9 16 7 Index Value of Interrupt Sources 16 10 16 8 IPRIORHI IPRIORLO Register 16 12 16 9 INTTSTHI INTTSTLO Register 16 12 17 1 TMOD Register 17 4 17 2 TDATA0 TDATA5 Registers 17 6 17 3 TCNT0 TCNT5 Registers 17 7 17 4 Timer Interrupt Clear Registers 17 8 17 5 WDT Register 17 9 17 6 Watc...

Page 35: ...re The ARM940T cached processor is a member of the ARM9 Thumb family of high performance 32 bit system on a chip processor solutions It provides a complete high performance CPU subsystem including ARM9TDMI RISC integer CPU 4KB instruction data caches write buffer and protection unit with an AMBA bus interface The ARM9TDMI core within the ARM940T executes both the 32 bit ARM and 16 bit Thumb instru...

Page 36: ...dependent interface MII or 7 wire interface Station management STA signaling for external physical layer configuration and link negotiation On chip CAM 21 addresses Full duplex mode for doubled bandwidth Pause operation hardware support for full duplex flow control Long packet mode for specialized environments Short packet mode for fast testing PAD generation for ease of processing and reduced pro...

Page 37: ...celerator DES or Triple DES mode ECB or CBC mode Encryption or decryption support General DMA support General DMA Channels Six GDMA channels Memory to memory data transfer Memory to peripheral data transfer high speed UART DES and USB controller Support for four external GDMA requests from GDMA request pins xGDMA_Req0 xGDMA_Req3 Six Programmable Timers Interval or toggle mode operation Hardware Wa...

Page 38: ...s 10MHz Provide up to 166MHz output to ARM940T PLL1 for system clock The Input frequency is 10MHz Provide up to 133MHz output to system PLL2 for USB The input frequency is 10MHz Provide 48MHz output to USB PLL3 for PHY The input frequency is 10MHz Provide 20MHz or 25MHz output to external PHY chip Operating Voltage Range Internal Power 1 8V 5 I O Power 3 3V 5 Operating temperature range 40 C 85 C ...

Page 39: ...Bridge Sys Bus Arbiter Six GDMA DES 3DES WDT Six Timers Clock Gen Reset Drv with 4 PLLs Interrupt Controller A H B I F ARM940T 166 MHz 4KB D Cache 4KB D Cache High Speed UART High Speed UART Console UART I2C USB 1 1 Function GPIOs 2 bank SDRAM 8 bank Flash ROM SRAM Ext I O External Bus Master 10 MHz OSC 20 MHz or 25 MHz REQ ACK 133 MHz APB BUS Figure 1 1 S3C2500B Block Diagram ...

Page 40: ...CT OVERVIEW S3C2500B 1 6 1 4 PACKAGE DIAGRAM TOP View A1 ball pad corner 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 A B C D E F G H J K L M N P R T U V W Y Figure 1 2 S3C2500B Pin Assignment Diagram ...

Page 41: ... TXD_10M O A12 ADDR16 O C2 MDC_0 O A13 ADDR12 O C3 PHY_CLKO O A14 ADDR9 O C4 HnDCD2 GPIO61 I O A15 ADDR6 O C5 HRXD2 GPIO57 I O A16 ADDR2 O C6 HRXC1 GPIO54 I O A17 XDATA31 I O C7 HnDTR1 GPIO50 I O A18 XDATA30 I O C8 HRXC0 DCL GPIO46 I O A19 XDATA25 I O C9 HnDTR0 BCL GPIO42 I O A20 XDATA24 I O C10 ADDR22 O B1 PHY_CLKSEL I C11 ADDR18 O B2 HTXC2 GPIO63 I O C12 ADDR14 O B3 HRXC2 GPIO62 I O C13 ADDR10 A...

Page 42: ... D8 GND F18 XDATA12 I O D9 HnRTS0 STRB GPIO43 I O F19 XDATA9 I O D10 ADDR23 ALE O F20 XDATA7 I O D11 VDD1 8 G1 RXD0_2 I D12 ADDR13 O G2 RXD0_1 I D 3 GND G3 VDD3 3 D14 ADDR4 O G4 CRS_0 I D15 VDD1 8 G17 XDATA11 I O D16 XDATA29 I O G18 XDATA8 I O D17 GND G19 XDATA6 I O D18 XDATA19 I O G20 XDATA5 I O D19 XDATA16 I O H1 RX_ERR_0 I D20 XDATA14 I O H2 RX_DV_0 LINK_10M I E1 TX_EN_0 O H3 RXD0_3 I E2 TXD0_3...

Page 43: ...ND J11 GND L11 GND J12 GND L12 GND J17 XDATA1 I O L17 VDD3 3 J18 XDATA0 I O L18 nWBE1 nBE1 DQM1 O J19 nSDCAS O L19 nWBE0 nBE0 DQM0 O J20 nSDRAS O L20 nWBE2 nBE2 DQM2 O K1 GND M1 VDD1 8_A K2 VDD1 8 M2 VDD1 8 K3 BUS_FILTER O M3 PHY_FILTER O K4 VDD1 8 M4 GND K9 GND M9 GND K10 GND M10 GND K11 GND M11 GND K12 GND M12 GND K17 nSDCS1 O M17 nRCS5 O K18 nSDCS0 O M18 nRCS6 O K19 nSDWE nWE16 O M19 nRCS7 O K2...

Page 44: ...20 nRCS4 O U2 CRS_1 I P1 GND U3 RXD1_1 I P2 MDC_1 O U4 GND P3 COL_1 I U5 USB_XCLK I P4 TXD1_1 LOOP_10M O U6 VDD3 3 P17 B0SIZE1 I U7 HURXD1 GPIO35 I O P18 CKE O U8 GND P19 nRCS0 O U9 GPIO0 I O P20 nRCS1 O U10 VDD3 3 R1 MDIO_1 I O U11 xINT2 GPIO10 I O R2 TX_CLK_1 I U12 xGDMA_Req0 GPIO14 I O R3 TXD1_2 O U13 GND R4 VDD1 8 U14 TIMER2 GPIO24 I O R17 VDD3 3 U15 VDD3 3 R18 B0SIZE0 I U16 TMODE I R19 nEWAIT...

Page 45: ...R1 GPIO37 I O W7 HUnDSR1 GPIO38 I O V8 HUnCTS1 GPIO40 I O W8 HUnDCD1 GPIO41 I O V9 GPIO1 I O W9 GPIO2 I O V10 GPIO5 I O W10 GPIO4 I O V11 xINT1 GPIO9 I O W11 xINT0 GPIO8 I O V12 xINT5 GPIO13 I O W12 xINT4 GPIO12 I O V13 xGDMA_Req3 GPIO17 I O W13 xGDMA_Req2 GPIO16 I O V14 xGDMA_Ack3 GPIO21 I O W14 xGDMA_Ack1 GPIO19 I O V15 TIMER3 GPIO25 I O W15 TIMER0 GPIO22 I O V16 TIMER5 GPIO27 I O W16 TIMER4 GPI...

Page 46: ...7 I O Y2 CLKSEL I Y12 xINT3 GPIO11 I O Y3 HUnDTR0 GPIO30 I O Y13 xGDMA_Req1 GPIO15 I O Y4 HUnDSR0 GPIO31 I O Y14 xGDMA_Ack0 GPIO18 I O Y5 HUnCTS0 GPIO33 I O Y15 xGDMA_Ack2 GPIO20 I O Y6 HUTXD1 GPIO36 I O Y16 TIMER1 GPIO23 I O Y7 HUnRTS1 GPIO39 I O Y17 GND Y8 HCLKO O Y18 SDA I O Y9 GPIO3 I O Y19 TMS I Y10 GPIO6 I O Y20 nTRST I ...

Page 47: ...TER 1 I poar50_abb PLL filter pin for System PLL If the PLL is used 320pF capacitor should be connected between the pin and ground PHY_FREQ 1 I Phic PHY clock frequency select for PHY PLL 0 20MHz 1 25MHz PHY_CLKSEL 1 I Phic Clock Select for PHY PLL If this pin is set to low the PHY PLL generates clock depending on PHY_FREQ state The PHY PLL goes into power down mode with PHY_CLKSEL set to high See...

Page 48: ...n operate independently as long as the CPU clock is faster than system clock CPU_FREQ 2 0 3 I phic CPU Clock Frequency Selection BUS_FREQ 2 0 3 I phic System Bus Clock Frequency Selection nRESET 1 I phis Not Reset NRESET is the global reset input for the S3C2500B and nRESET must be held to low for at least 64 clock cycles for digital filtering TMODE 1 I phicd Test Mode The TMODE pin setting is int...

Page 49: ...issued at the same time as burst read or burst write by asserting high on ADDR 10 AP XDATA 31 0 32 I O phbsut20 External bi directional 32bit data bus The S3C2500B supports 8 bit 16bit 32bit bus with ROM SRAM Flash Ext IO bank but supports 16 bit or 32 bit bus with SDRAM bank nSDCS 1 0 2 O phot20 Not chip select strobe for SDRAM Two SDRAM banks are supported nSDRAS 1 O phot20 Not row address strob...

Page 50: ... I O By controlling the nRCS signals you can map CPU address into the physical memory banks B0SIZE 1 0 2 I phic Bank 0 Data Bus Access Size Bank0 is used for the boot program You use these pins to set the size of the bank 0 data bus as follows 01 Byte 10 Half word 11 Word and 00 reserved nOE 1 O phot20 Not output enable Whenever a memory read access occurs the nOE output controls the output enable...

Page 51: ... get the control of the bus and the XBMACK goes low XBMACK 1 O phob8 External bus Acknowledge TAP Control 5 TCK 1 I phic JTAG Test Clock The JTAG test clock shifts state information and test data into and out of the S3C2500B during JTAG test operations TMS 1 I phicu JTAG Test Mode Select This pin controls JTAG test operations in the S3C2500B This pin is internally connected pull up TDI 1 I phicu J...

Page 52: ...ynchronously with minimum delay from the start of a collision on the medium in MII mode COL_10M is asserted when a 10 Mbit s PHY detects a collision TX_CLK_0 1 I phis Transmit Clock Transmit Clock for 10M The controller drives TXD 3 0 and TX_EN from the rising edge of TX_CLK In MII mode the PHY samples TXD 3 0 and TX_EN on the rising edge of TX_CLK For data transfers TXCLK_10M is provided by the 1...

Page 53: ...more TX_CLK periods TX_ERR causes the PHY to emit one or more symbols which are not part of the valid data or delimiter set located somewhere in the frame that is being transmitted PCOMP_10M is asserted immediately after the packet s DA field is received PCOMP_10M is used with the Management Bus of the DP83950 Repeater Interface Controller from National Semiconductor The MAC can be programmed to a...

Page 54: ...RXCLK_10 M clock comes from the 10Mbit s PHY RXD0 3 0 RXD_10M 4 I phis Receive Data Receive Data for 10M RXD is aligned on nibble boundaries RXD 0 corresponds to the first bit received on the physical medium which is the LSB of the byte in one clock period and the fifth bit of that byte in the next clock RXD_10M is shared with RXD 0 and it is a line for receiving data from the 10 Mbit s PHY RX_DV_...

Page 55: ...t Data I O When a read command is being executed data that is clocked out of the PHY is presented on this pin When a write command is being executed data that is clocked out of the controller is presented on this pin for the Physical Layer Entity PHY COL_1 1 I phis Collision Detected Collision Detected for 10M COL is asserted asynchronously with minimum delay from the start of a collision on the m...

Page 56: ...the first byte and the fifth bit of that byte during the next clock TXD_10M is shared with TXD 0 and is a data line for transmitting to the 10 Mbit s PHY LOOP_10M is shared with TXD 1 and is driven by the loop back bit in the control register TX_EN_1 1 O phob4 Transmit Enable Transmit Enable for 10M TX_EN provides precise framing for the data carried on TXD 3 0 This pin is active during the clock ...

Page 57: ... Bus of the DP83950 Repeater Interface Controller from National Semiconductor The MAC can be programmed to assert PCOMP if there is a CAM match or if there is not a match The RIC Repeater Interface Controller uses this signal to compress shorten the packet received for management purposes and to reduce memory usage See the DP83950 Data Sheet published by National Semiconductor for details on the R...

Page 58: ... LSB of the byte in one clock period and the fifth bit of that byte in the next clock RXD_10M is shared with RXD 0 and it is a line for receiving data from the 10M bit s PHY RX_DV_1 LINK_10M 1 I phis Receive Data Valid PHY asserts RX_DV synchronously holding it active during the clock periods in which RXD 3 0 contains valid data received PHY asserts RX_DV no later than the clock period when it pla...

Page 59: ... not exceed the rate of the S3C2500B internal master clock HnDTR0 BCL GPIO42 1 I O phbst8 IOM2 bit clock 768 KHz HDLC Ch 0 Data Terminal Ready NDTR0 output indicates that the data terminal device is ready for transmis sion and reception General I O Port HnRTS0 STRB GPIO43 1 I O phbst8 IOM2 Data Strobe 8 KHz programable signal for selecting an 8 bit timeslot or 16 bit timeslot HDLC Ch 0 Request To ...

Page 60: ...hbst8 IOM2 Data Clock HDLC Ch 0 Receiver Clock When this clock input is used as the receiver clock the receiver samples the data on the positive or negedge of HRXC0 clock This can be determined by S W selection This clock can be the source clock of the receiver the baud rate generator or the DPLL General I O Port HTXC0 FSC GPIO47 1 I O phbst8 IOM2 Frame Syncronization Clock HDLC Ch 0 Transmitter C...

Page 61: ... General I O Port HnDCD1 GPIO53 1 I O phbst8 HDLC Ch 1 Data Carrier Detected See the HnDCD0 description General I O Port HRXC1 GPIO54 1 I O phbst8 HDLC Ch 1 Receiver Clock See the HRXC0 description General I O Port HTXC1 GPIO55 1 I O phbst8 HDLC Ch 1 Transmitter Clock See the HTXC0 description General I O Port HDLC2 8 HTXD2 GPIO56 1 I O phbst8 HDLC Ch 2 Transmit Data See the HTXD0 description Gene...

Page 62: ...USB_CLKSEL is 0 USB PLL output is used as the USB clock When USB_CLKSEL is 1 the USB_XCLK is usedas the USB clock See Figure 4 5 USB_FILTER 1 O poar50_abb Filter for USB PLL If the PLL is used 320pF capacitor should be connected between the pin and ground CUART CURXD 1 I phis Console UART Receive Data 2 CUTXD 1 O phob8 Console UART Transmit Data HUART0 UCLK 1 I Phis HUART External Clock for HUART0...

Page 63: ...o this pin output can be controlled directly by HUART0 control register General I O Port HUnCTS0 GPIO33 1 I O phbst8 Not Clear to send This input pin function controlled by hardware flow control bit value in HUART0 control register If hardware flow control bit set to one HUART0 can transmit the transmitting data only when this pin state is active General I O Port HUnDCD0 GPIO34 1 I O phbst8 Not Da...

Page 64: ...ort GPIO Included xINT xGDMA_ Req xGDMA_ Ack Timer GPIO 7 0 8 I O phbst8 General I O Ports XINT 5 0 GPIO 13 8 6 I O phbst8 External interrupt requests General I O Ports XGDMA_Req 3 0 GPIO 17 14 4 I O phbst8 External DMA requests for GDMA General I O Ports XGDMA_Ack 3 0 GPIO 21 18 4 I O phbst8 External DMA acknowledge from GDMA General I O Ports TIMER0 GPIO 22 1 I O phbst8 TIMER0 Out General I O Po...

Page 65: ...bcut12 I O 12mA LVCMOS Level Tri State Buffer 3 3V Pull up resistor phbsud4 I O 4sm LVCMOS Schmit trigger level Tri State Buffer 3 3 Pull up resister phbst8 I O 8mA LVCMOS Schmit trigger level Tri State Buffer 3 3V phbst16 I O 16mA LVCMOS Schmit trigger leve Tri State Buffer 3 3V Phbst24 I O 24mA LVCMOS Schmit trigger level Tri State Buffer 3 3V Phbsut20 I O 20mA LVCMOS Schmit trigger level Tri St...

Page 66: ...L Configuration Register 0x000103111 Table 1 4 S3C2500B Memory Controller Registers Address R W Description Reset Value B0CON 0xF0010000 R W Bank 0 control register 0xC514E488 B1CON 0xF0010004 R W Bank 1 control register 0xC514E488 B2CON 0xF0010008 R W Bank 2 control register 0xC514E488 B3CON 0xF001000C R W Bank 3 control register 0xC514E488 B4CON 0xF0010010 R W Bank 4 control register 0xC514E488 ...

Page 67: ...r counter 0x00000000 BMTXINTENA 0xF00A0018 R W BDMA MAC Tx Interrupt enable register 0x00000000 BMRXINTENA 0xF00A001C R W BDMA MAC Rx Interrupt enable register 0x00000000 BMTXSTATA 0xF00A0020 R W BDMA MAC Tx Status register 0x00000000 BMRXSTATA 0xF00A0024 R W BDMA MAC Rx Status register 0x00000000 BDMARXLENA 0xF00A0028 R W Receive Frame Size 0x00000000 CFTXSTATA 0xF00A0030 R Transmit control frame...

Page 68: ...0xF00C0020 R W BDMA MAC Tx Status register 0x00000000 BMRXSTATB 0xF00C0024 R W BDMA MAC Rx Status register 0x00000000 BDMARXLENB 0xF00C0028 R W Receive Frame Size 0x00000000 CFTXSTATB 0xF00C0030 R Transmit control frame status 0x00000000 MACCONB 0xF00D0000 R W MAC control 0x00000000 CAMCONB 0xF00D0004 R W CAM control 0x00000000 MACTXCONB 0xF00D0008 R W Transmit control 0x00000000 MACTXSTATB 0xF00D...

Page 69: ...00000000 HSAR1 0 F0100028 R W HDLC station address 1 0 00000000 HSAR2 0 F010002C R W HDLC station address 2 0 00000000 HSAR3 0 F0100030 R W HDLC station address 3 0 00000000 HMASK 0 F0100034 R W HDLC mask register 0 00000000 HDMATxPTR 0 F0100038 R W DMA Tx buffer descriptor pointer 0 FFFFFFFF HDMARxPTR 0 F010003C R W DMA Rx buffer descriptor pointer 0 FFFFFFFF HMFLR 0 F0100040 R W Maximum frame le...

Page 70: ... 00000000 HSAR1 0 F0110028 R W HDLC station address 1 0 00000000 HSAR2 0 F011002C R W HDLC station address 2 0 00000000 HSAR3 0 F0110030 R W HDLC station address 3 0 00000000 HMASK 0 F0110034 R W HDLC mask register 0 00000000 HDMATxPTR 0 F0110038 R W DMA Tx buffer descriptor pointer 0 FFFFFFFF HDMARxPTR 0 F011003C R W DMA Rx buffer descriptor pointer 0 FFFFFFFF HMFLR 0 F0110040 R W Maximum frame l...

Page 71: ...00000000 HSAR1 0 F0120028 R W HDLC station address 1 0 00000000 HSAR2 0 F012002c R W HDLC station address 2 0 00000000 HSAR3 0 F0120030 R W HDLC station address 3 0 00000000 HMASK 0 F0120034 R W HDLC mask register 0 00000000 HDMATxPTR 0 F0120038 R W DMA Tx buffer descriptor pointer 0 FFFFFFFF HDMARxPTR 0 F012003C R W DMA Rx buffer descriptor pointer 0 FFFFFFFF HMFLR 0 F0120040 R W Maximum frame le...

Page 72: ...annel Rx Buffer 0x00000000 IOM2CITD0 0xF0130018 R W C I0 Channel Tx Buffer 0x0000000F IOM2CIRD0 0xF013001C R W C I0 Channel Rx Buffer 0x00000000 IOM2CITD1 0xF0130020 R W C I1 Channel Tx Buffer 0x0000003F IOM2CIRD1 0xF0130024 R W C I1 Channel Rx Buffer 0x00000000 IOM2MTD 0xF0130028 R W Monitor Channel Tx Buffer 0x000000FF IOM2MRD 0xF013002C R W Monitor Channel Rx Buffer 0x000000FF TSAACON 0xF013003...

Page 73: ... common status register 0x00000401 USBEP3CSR 0xF00E0024 R W USB endpoint 3 common status register 0x00000401 USBEP4CSR 0xF00E0028 R W USB endpoint 4 common status register 0x00000401 0xF00E002C Reserved USBWCEP0 0xF00E0030 R W USB write count register for endpoint 0 0x00000000 USBWCEP1 0xF00E0034 R W USB write count register for endpoint 1 0x00000000 USBWCEP2 0xF00E0038 R W USB write count registe...

Page 74: ...le register 0x00000000 DESKEY1L 0xF0090010 R W Key 1 left half 0x00000000 DESKEY1R 0xF0090014 R W Key 1 right half 0x00000000 DESKEY2L 0xF0090018 R W Key 2 left half 0x00000000 DESKEY2R 0xF009001C R W Key 2 right half 0x00000000 DESKEY3L 0xF0090020 R W Key 3 left half 0x00000000 DESKEY3R 0xF0090024 R W Key 3 right half 0x00000000 DESIVL 0xF0090028 R W IV left half 0x00000000 DESIVR 0xF009002C R W ...

Page 75: ...F0050030 W GDMA channel 1 run enable register 0x00000000 DIPR1 0xF0050034 R WC GDMA channel 1 interrupt pending register 0x00000000 DCON2 0xF0050040 R W GDMA channel 2 control register 0x00000000 DSAR2 0xF0050044 R W GDMA channel 2 source address register 0x00000000 DDAR2 0xF0050048 R W GDMA channel 2 destination address register 0x00000000 DTCR2 0xF005004C R W GDMA channel 2 transfer count regist...

Page 76: ...nable register 0x00000000 CUTXBUF 0xF006000C W Console UART transmit data register CURXBUF 0xF0060010 R Console UART receive data register CUBRD 0xF0060014 R W Console UART baud rate divisor register 0x0000 CUCHAR1 0xF0060018 R W Console UART control character register 1 0x00000000 CUCHAR2 0xF006001C R W Console UART control character register 2 0x00000000 Table 1 17 S3C2500B High speed UART Contr...

Page 77: ...502 Table 1 19 S3C2500B I O Port Controller Register Address R W Description Reset Value IOPMODE1 0xF0030000 R W I O port mode select lower register for port 0 to 31 0xF003FFFF IOPMODE2 0xF0030004 R W I O port mode select upper register for port 32 to 63 0xFFFFFFFF IOPCON1 0xF0030008 R W I O port function control register for port 0 to 31 0x0FFFFF00 IOPCON2 0xF003000C R W I O port select function ...

Page 78: ... INTPRIOR4 0xF0140030 R W Interrupt priority register 4 0x13121110 INTPRIOR5 0xF0140034 R W Interrupt priority register 5 0x17161514 INTPRIOR6 0xF0140038 R W Interrupt priority register 6 0x1B1A1918 INTPRIOR7 0xF014003C R W Interrupt priority register 7 0x1F1E1D1C INTPRIOR8 0xF0140040 R W Interrupt priority register 8 0x23222120 INTPRIOR9 0xF0140044 R W Interrupt priority register 9 0x00262524 INT...

Page 79: ...ster 0xFFFFFFFF TDATA1 0xF0040018 R W Timer 1 data register 0x00000000 TCNT1 0xF004001C R W Timer 1 count register 0xFFFFFFFF TDATA2 0xF0040020 R W Timer 2 data register 0x00000000 TCNT2 0xF0040024 R W Timer 2 count register 0xFFFFFFFF TDATA3 0xF0040028 R W Timer 3 data register 0x00000000 TCNT3 0xF004002C R W Timer 3 count register 0xFFFFFFFF TDATA4 0xF0040030 R W Timer 4 data register 0x00000000...

Page 80: ...PRODUCT OVERVIEW S3C2500B 1 46 NOTES ...

Page 81: ...he processor mode or the contents of the registers 2 2 SWITCHING STATE 2 2 1 ENTERING THUMB STATE Entry into THUMB state can be achieved by executing a BX instruction with the state bit bit 0 set in the operand register Transition to THUMB state will also occur automatically on return from an exception IRQ FIQ UNDEF ABORT SWI etc if the exception was entered with the processor in THUMB state 2 2 2...

Page 82: ...ess Word Address Most significant byte is at lowest address Word is addressed by byte address of most significant byte 24 15 16 Figure 2 1 Big Endian Addresses of Bytes within Words NOTE The data locations in the external memory are different with Figure 2 1 in the S3C2500B Please refer to the chapter 4 system manager 2 3 2 LITTLE ENDIAN FORMAT In Little Endian format the lowest numbered byte in a...

Page 83: ...pport a data transfer or channel process IRQ irq Used for general purpose interrupt handling Supervisor svc Protected mode for the operating system Abort mode abt Entered after a data or instruction prefetch abort System sys A privileged user mode for the operating system Undefined und Entered when an undefined instruction is executed Mode changes may be made under software control or may be broug...

Page 84: ...ormation Register 14 is used as the subroutine link register This receives a copy of R15 when a branch and link BL instruction is executed At all other times it may be treated as a general purpose register The corresponding banked registers R14_svc R14_irq R14_fiq R14_abt and R14_und are similarly used to hold the return values of R15 when interrupts and exceptions arise or when branch and link in...

Page 85: ...er R0 R1 R2 R3 R4 R5 R6 R7 R10 R8 R9 R11 R12 R15 PC R13_und R14_und R0 R1 R2 R3 R4 R5 R6 R7 R10 R8 R9 R11 R12 R15 PC R13_irq R14_irq R0 R1 R2 R3 R4 R5 R6 R7 R10 R8 R9 R11 R12 R15 PC R13_abt R14_abt R10 R8 R9 R11 R12 R15 PC R13_svc R14_svc R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 R8_fiq R9_fiq R10_fiq R11_fiq R12_fiq R13_fiq R14_fiq R15 PC R0 R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R1...

Page 86: ...s SPSRs for each privileged mode This is shown in Figure 2 4 CPSR CPSR SPSR_fiq CPSR SPSR_svc CPSR SPSR_abt CPSR SPSR_irq CPSR SPSR_und System User FIQ Supervisor About IRQ Undefined THUMB State Program Status Registers banked register THUMB State General Registers and Program Counter R0 R1 R2 R3 R4 R5 R6 R7 SP LR PC SP_fiq LR_fiq R0 R1 R2 R3 R4 R5 R6 R7 PC SP_svg LR_svc R0 R1 R2 R3 R4 R5 R6 R7 PC...

Page 87: ...B state SP maps onto ARM state R13 THUMB state LR maps onto ARM state R14 The THUMB state program counter maps onto the ARM state program counter R15 This relationship is shown in Figure 2 5 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R5 R6 R7 R8 R9 R10 R11 R12 Stack Pointer R13 Link Register R14 Program Counter R15 CPSR SPSR Stack Pointer SP Link Register LR Program Counter PC CPSR SPSR THUMB State ARM S...

Page 88: ...values with the CMP and ADD instructions For more information refer to Figure 3 34 2 8 THE PROGRAM STATUS REGISTERS The ARM9TDMI contains a Current Program Status Register CPSR plus five Saved Program Status Registers SPSRs for use by exception handlers These register s functions are Hold information about the most recently performed ALU operation Control the enabling and disabling of interrupts S...

Page 89: ...ftware The T bit This reflects the operating state When this bit is set the processor is executing in THUMB state otherwise it is executing in ARM state This is reflected on the TBIT external signal Note that the software must never change the state of the TBIT in the CPSR If this happens the processor will enter an unpredictable state Interrupt disable bits The I and F bits are the interrupt disa...

Page 90: ... LR_svc SP_svc PC CPSR SPSR_svc R12 R0 R14_svc R13_svc PC CPSR SPSR_svc 10111 Abort R7 R0 LR_abt SP_abt PC CPSR SPSR_abt R12 R0 R14_abt R13_abt PC CPSR SPSR_abt 11011 Undefined R7 R0 LR_und SP_und PC CPSR SPSR_und R12 R0 R14_und R13_und PC CPSR 11111 System R7 R0 LR SP PC CPSR R14 R0 PC CPSR Reserved bits The remaining bits in the PSRs are reserved When changing a PSR s flag or control bits you mu...

Page 91: ...the correct place on return from the exception This means that the exception handler need not determine which state the exception was entered from For example in the case of SWI MOVS PC R14_svc will always return to the next instruction regardless of whether the SWI was executed in ARM or THUMB state 2 Copies the CPSR into the appropriate SPSR 3 Forces the CPSR mode bits to a value which depends o...

Page 92: ...rated the data abort 4 The value saved in R14_svc upon reset is unpredictable 2 9 4 FIQ The FIQ Fast Interrupt Request exception is designed to support a data transfer or channel process and in ARM state has sufficient private registers to remove the need for register saving thus minimizing the overhead of context switching FIQ is externally generated by taking the nFIQ input LOW This input can ex...

Page 93: ... type Single data transfer instructions LDR STR write back modified base registers the Abort handler must be aware of this The swap instruction SWP is aborted as though it had not been executed Block data transfer instructions LDM STM complete If write back is set the base is updated If the instruction would have overwritten the base with data ie it has the base in the transfer list the overwritin...

Page 94: ...le it takes the undefined instruction trap This mechanism may be used to extend either the THUMB or ARM instruction set by software emulation After emulating the failed instruction the trap handler should execute the following irrespective of the state ARM or Thumb MOVS PC R14_und This restores the CPSR and returns to the instruction following the undefined instruction 2 10 EXCEPTION VECTORS The f...

Page 95: ...t are mutually exclusive since they each correspond to particular non overlapping decoding of the current instruction If a data abort occurs at the same time as a FIQ and FIQs are enabled ie the CPSR s F flag is clear ARM9TDMI enters the data abort handler and then immediately proceeds to the FIQ vector A normal return from FIQ will cause the data abort handler to resume execution Placing data abo...

Page 96: ...ntinuous 20 MHz processor clock The maximum IRQ latency calculation is similar but must allow for the fact that FIQ has higher priority and could delay entry into the IRQ handling routine for an arbitrary length of time The minimum latency for FIQ or IRQ consists of the shortest time the request can take through the synchroniser Tsyncmin plus Tfiq This is 4 processor cycles 2 12 RESET When the nRE...

Page 97: ...f system on a chip designs The EmbeddedICE software and hardware debug features of the ARM940T macrocell are accessed via a standard 5 pin JTAG port and are supported by ARM s Software Development Toolkit and Multi ICE interface hardware The EmbeddedICE features allow software download and debug of the final production system with no cost overhead there is no monitor code or other use of target re...

Page 98: ...tection Unit CP15 ARM9TDMI Processor Core Integral EmbeddedICE AMBA Interface Instruction Cache 4K I Cache Control Data Cache 4K D Cache Control CPID 31 0 CPDIN 31 0 CPDOUT 31 0 BA 31 0 Bcontrol BD 31 0 DA 31 0 DD 31 0 IA 31 0 ID 31 0 JTAG Interface 4 0 Figure 2 7 ARM940T Block Diagram ...

Page 99: ...rs defined in CP15 are accessible with MCR and MRC instructions These are described in ARM940T CP15 registers on page 2 5 Registers and operations provided by any coprocessors attached to the external coprocessor interface will be accessible with appropriate coprocessor instructions The ARM9TDMI processor core implements ARM Architecture v4T and so executes the ARM 32 bit instruction set and the c...

Page 100: ... data abort model significantly simplifies the software data abort handler 2 15 2 INSTRUCTION SET EXTENSION SPACES All ARM processors implement the undefined instruction space as one of the entry mechanisms for the undefined instruction exception That is ARM instructions with opcode 27 25 0b011 and opcode 4 1 are undefined on all ARM processors including the ARM9TDMI and ARM7TDMI ARM Architecture ...

Page 101: ...n Read write 10 14 Reserved Undefined 15 Test Not accessed in normal operations NOTE Register locations 0 2 5 and 6 each provide access to more than one register The register accessed depends upon the value of the opcode_2 field See the register descriptions that follow for further information 2 16 1 1 Register 0 ID code This is a read only register which returns a 32 bit device ID code The ID cod...

Page 102: ...register The register contains information about the size and architecture of the caches The format of the register is shown in Table 2 7 Table 2 7 Cache Type Register Format Register Bits Meaning Value 31 29 Reserved 000 28 25 Cache type 0111 24 Harvard Unified 1 defines Harvard cache 23 21 Reserved 000 20 18 DCache size 011 defines 4KB 17 15 DCache associativity 110 defines 64 way 14 DCache base...

Page 103: ... 0 Protection unit enable P The bits in the control register have the following functions Bits 31 30 Control the clocking mode of the processor as shown in Table 2 9 Clocking modes are discussed in Chapter5 Clock Modes Table 2 9 Clocking Modes Clockin Mode Bit 31 Bit 30 FastBus mode 0 0 Reserved 1 0 Synchronous 0 1 Asynchronous 1 1 Bit 13 Selects the location of the vector table During reset the b...

Page 104: ...cacheable bits If the opcode_2 field 1 the instruction cacheable bits are programmed For example MCR p15 0 Rd c2 c0 1 Write instruction cacheable bits MRC p15 0 Rd c2 c0 1 Read instruction cacheable bits The format for the data and instruction cacheable bits is similar as shown in Table 2 10 Setting a bit makes an area cacheable clearing it makes it non cacheable All defined bits in the control re...

Page 105: ...buffer control bit B_d7 for data area 7 6 Write buffer control bit B_d6 for data area 6 5 Write buffer control bit B_d5 for data area 5 4 Write buffer control bit B_d4 for data area 4 3 Write buffer control bit B_d3 for data area 3 2 Write buffer control bit B_d2 for data area 2 1 Write buffer control bit B_d1 for data area 1 0 Write buffer control bit B_d0 for data area 0 2 16 1 6 Register 5 Inst...

Page 106: ...0 bits of area 2 3 2 ap1 1 0 bits of area 1 1 0 ap0 1 0 bits of area 0 The values of the Iapn 1 0 and Dapn 1 0 bits define the access permission for each area of memory The encoding is shown in Table 2 13 NOTE On reset the values of the Iapn 1 0 and Dapn 1 0 bits for all areas are undefined However as on reset the protection unit is disabled and all areas are effectively set to no access The prote...

Page 107: ...a Protection Region Registers ARM instruction Protection region register MCR MRC p15 0 Rd c6 c7 0 Data memory region 7 MCR MRC p15 0 Rd c6 c6 0 Data memory region 6 MCR MRC p15 0 Rd c6 c5 0 Data memory region 5 MCR MRC p15 0 Rd c6 c4 0 Data memory region 4 MCR MRC p15 0 Rd c6 c3 0 Data memory region 3 MCR MRC p15 0 Rd c6 c2 0 Data memory region 2 MCR MRC p15 0 Rd c6 c1 0 Data memory region 1 MCR M...

Page 108: ...gister The behavior is undefined if this is not the case Area sizes are given in Table 2 17 Table 2 17 Area Size Encoding Bit encoding Area size Bit encoding Area size 00000 to 01010 Reserved 10101 4MB 01011 4KB 10110 8MB 01100 8KB 10111 16MB 01101 16KB 11000 32MB 01110 32KB 11001 64MB 01111 64KB 11010 128MB 10000 128KB 11011 256MB 10001 256KB 11100 512MB 10010 512KB 11101 1GB 10011 1MB 11110 2GB ...

Page 109: ...egister 7 ARM instruction Data Protection region register MCR p15 0 Rd c7 c5 0 should be zero Flush ICache MCR p15 0 Rd c7 c5 2 Index segment Flush ICache single entry MCR p15 0 Rd c7 c6 0 should be zero Flush DCache MCR p15 0 Rd c7 c6 2 Index segment Flush DCache single entry MCR p15 0 Rd c7 c10 2 Index segment Clean DCache single entry MCR p15 0 Rd c7 c13 1 Address Prefetch ICache line MCR p15 0...

Page 110: ...uses this to occur MCR p15 0 Rd c7 c0 4 The following instruction causes the same affect and has been added for backward compatibility with StrongARM SA 1 MCR p15 0 Rd c15 c8 2 This stalls the processor with internal clocks held high from the time that this instruction is executed until one of the signals nFIQ nIRQ or EDBGRQ is asserted Also if the debugger sets the debug request bit in the Embedd...

Page 111: ...the processor core with CPnWAIT asserted until any outstanding accesses in the write buffer have been completed that is until all data has been written to memory 2 16 1 9 Register 9 Instruction and data lockdown registers These registers allow regions of the cache to be locked down The opcode_2 field determines whether the instruction or data caches are programmed If the opcode_2 field 0 the data ...

Page 112: ...et the respective caches into a pseudo round robin replacement mode All defined bits in the control register are set to zero at reset Table 2 22 CP15 Register 15 Register bit Function 31 4 Reserved 3 ITRRobin 2 DTRRobin 1 0 Reserved 2 16 1 11 Reserved Registers Accessing a reserved register is unpredictable ...

Page 113: ...pt Undefined Single data transfer Cond 1 1 1 1 Ignored by processor Cond 1 1 1 0 CRn Rd CP Opc L CP CP 1 CRm Cond 1 1 1 0 CRn CRd CP Opc CP CP 0 CRm Cond 1 1 0 P U N W L Rn CRd CP Offset Cond 1 0 1 L Offset Cond 1 0 0 P U S W L Rn Register List Cond 0 1 1 1 Cond 0 1 1 P U B W L Rn Rd Offset Cond 0 0 0 P U 1 W L Rn Rd Offset 1 S H 1 Offset Cond 0 0 0 P U 0 W L Rn Rd 0 0 0 0 1 S H 1 Rm Cond 0 0 0 1 ...

Page 114: ...CPSR flags Rn Op2 CMP Compare CPSR flags Rn Op2 EOR Exclusive OR Rd Rn AND NOT Op2 OR op2 AND NOT Rn LDC Load coprocessor from memory Coprocessor load LDM Load multiple registers Stack manipulation Pop LDR Load register from memory Rd address MCR Move CPU register to coprocessor register cRn rRn op cRm MLA Multiply accumulate Rd Rm Rs Rn MOV Move register or constant Rd Op2 MRC Move from coprocess...

Page 115: ...arry Rd Op2 Rn 1 Carry SBC Subtract with carry Rd Rn Op2 1 Carry STC Store coprocessor register to memory Address CRn STM Store multiple Stack manipulation push STR Store register to memory address Rd SUB Subtract Rd Rn Op2 SWI Software Interrupt OS call SWP Swap register with memory Rd Rn Rn Rm TEQ Test bit wise equality CPSR flags Rn EOR Op2 TST Test bits CPSR flags Rn AND Op2 ...

Page 116: ...ag is set In practice fifteen different conditions may be used these are listed in Table 3 2 The sixteenth 1111 is reserved and must not be used In the absence of a suffix the condition field of most instructions is set to Always suffix AL This means the instruction will always be executed regardless of the CPSR condition codes Table 3 2 Condition Code Summary Code Suffix Flags Meaning 0000 EQ Z s...

Page 117: ...uctions 31 24 27 19 15 8 7 0 0 0 0 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 1 Cond Rn 28 16 11 12 23 20 4 3 3 0 Operand Register If bit0 of Rn 1 subsequent instructions decoded as THUMB instructions If bit0 of Rn 0 subsequent instructions decoded as ARM instructions 31 28 Condition Field Figure 3 2 Branch and Exchange Instructions 3 3 1 INSTRUCTION CYCLE TIMES The BX instruction takes 2S 1N cycles ...

Page 118: ...R0 Branch and change to THUMB state CODE16 Assemble subsequent code as Into_THUMB THUMB instructions ADR R5 Back_to_ARM Generate branch target to word aligned address hence bit 0 is low and so change back to ARM state BX R5 Branch and change back to ARM state ALIGN Word align CODE32 Assemble subsequent code as ARM instructions Back_to_ARM ...

Page 119: ...t of the pre fetch operation which causes the PC to be 2 words 8 bytes ahead of the current instruction 3 4 1 THE LINK BIT Branch with Link BL writes the old PC into the link register R14 of the current bank The PC value written into R14 is adjusted to allow for the pre fetch and contains the address of the instruction following the branch and link instruction Note that the CPSR is not saved with ...

Page 120: ...l be used expression The destination The assembler calculates the offset Examples here BAL here Assembles to 0xEAFFFFFE note effect of PC offset B there Always condition used as default CMP R1 0 Compare R1 with zero and branch to fred if R1 was zero otherwise continue BEQ fred Continue to next instruction BL sub ROM Call subroutine at computed address ADDS R1 1 Add 1 to register 1 setting CPSR fla...

Page 121: ...p1 Op2 0011 RSB Rd Op2 Op1 0100 ADD Rd Op1 Op2 0101 ADC Rd Op1 Op2 C 0110 SBC Rd OP1 Op2 C 1 0111 RSC Rd Op2 Op1 C 1 1000 TST set condition codes on Op1 AND Op2 1001 TEO set condition codes on OP1 EOR Op2 1010 CMP set condition codes on Op1 Op2 1011 SMN set condition codes on Op1 Op2 1100 ORR Rd Op1 OR Op2 1101 MOV Rd OP2 1110 BIC Rd Op1 AND NOT Op2 1111 MVN Rd NOT Op2 25 Immediate Operand 0 Opera...

Page 122: ...immediate value Imm according to the value of the I bit in the instruction The condition codes in the CPSR may be preserved or updated as a result of this instruction according to the value of the S bit in the instruction Certain operations TST TEQ CMP CMN do not write the result to Rd They are used only to perform tests and to set the condition codes on the result and always have the S bit set Th...

Page 123: ...10 Operand1 operand2 carry 1 RSC 0111 Operand2 operand1 carry 1 TST 1000 As AND but result is not written TEQ 1001 As EOR but result is not written CMP 1010 As SUB but result is not written CMN 1011 As ADD but result is not written ORR 1100 Operand1 OR operand2 MOV 1101 Operand2 operand1 is ignored BIC 1110 Operand1 AND NOT operand2 Bit clear MVN 1111 NOT operand2 operand1 is ignored The arithmeti...

Page 124: ...ns 3 5 2 1 Instruction Specified Shift Amount When the shift amount is specified in the instruction it is contained in a 5 bit field which may take any value from 0 to 31 A logical shift left LSL takes the contents of Rm and moves each bit by the specified amount to a more significant position The least significant bits of the result are filled with zeros and the high bits of Rm which do not map i...

Page 125: ...L 0 and allow LSR 32 to be specified An arithmetic shift right ASR is similar to logical shift right except that the high bits are filled with bit 31 of Rm instead of zeros This preserves the sign in 2 s complement notation For example ASR 5 is shown in Figure 3 8 31 Contents of Rm Value of Operand 2 0 carry out 4 5 30 Figure 3 8 Arithmetic Shift Right The form of the shift field which might be ex...

Page 126: ... The form of the shift field which might be expected to give ROR 0 is 31 Contents of Rm Value of Operand 2 0 carry out 4 5 Figure 3 9 Rotate Right used to encode a special function of the barrel shifter rotate right extended RRX This is a rotate right by one bit position of the 33 bit quantity formed by appending the CPSR C flag to the most significant end of the contents of Rm as shown in Figure ...

Page 127: ...ll be a logical extension of the shift described above 1 LSL by 32 has result zero carry out equal to bit 0 of Rm 2 LSL by more than 32 has result zero carry out zero 3 LSR by 32 has result zero carry out equal to bit 31 of Rm 4 LSR by more than 32 has result zero carry out zero 5 ASR by 32 or more has result filled with and carry out equal to bit 31 of Rm 6 ROR by 32 has result equal to Rm carry ...

Page 128: ...tate changes which atomically restore both PC and CPSR This form of instruction should not be used in User mode 3 5 5 USING R15 AS AN OPERAND If R15 the PC is used as an operand in a data processing instruction the register is used directly The PC value will be the address of the instruction plus 8 or 12 bytes due to instruction prefetching If the shift amount is specified in the instruction the P...

Page 129: ... operand instructions opcode cond S Rd Op2 CMP CMN TEQ TST instructions which do not produce a result opcode cond Rn Op2 AND EOR SUB RSB ADD ADC SBC RSC ORR BIC opcode cond S Rd Rn Op2 where Op2 Rm shift or expression cond A two character condition mnemonic See Table 3 2 S Set condition codes if S present implied for CMP CMN TEQ TST Rd Rn and Rm Expressions evaluating to a register number expressi...

Page 130: ...uality with 3 The S is in fact redundant as the assembler inserts it automatically SUB R4 R5 R7 LSR R2 Logical right shift R7 by the number in the bottom byte of R2 subtract result from R5 and put the answer into R4 MOV PC R14 Return from subroutine MOVS PC R14 Return from exception and restore CPSR from SPSR_mode ...

Page 131: ...nts to be transferred to the condition code flags N Z C and V of CPSR or SPSR_ mode without affecting the control bits In this case the top four bits of the specified register contents or 32 bit immediate value are written to the top four bits of the relevant PSR 3 6 1 OPERAND RESTRICTIONS In user mode the control bits of the CPSR are protected from change so only the condition code flags of the C...

Page 132: ... PSR Contents to a Register 0 3 0 Source Register 22 Destination PSR 0 CPSR 1 SPSR_ current mode 31 28 Condition Field 15 21 Destination Register 19 16 Source PSR 0 CPSR 1 SPSR_ current mode 31 28 Condition Field 3 0 Source Register 11 4 Source operand is an immediate value 7 0 Unsigned 8 bit immediate value 11 8 Shift applied to Imm 22 Destination PSR 0 CPSR 1 SPSR_ current mode 25 Immediate Oper...

Page 133: ... PSR register to a general register using the MRS instruction changing only the relevant bits and then transferring the modified value back to the PSR register using the MSR instruction Examples The following sequence performs a mode change MRS R0 CPSR Take a copy of the CPSR BIC R0 R0 0x1F Clear the mode bits ORR R0 R0 new_mode Select new mode MSR CPSR R0 Write back the modified CPSR When the aim...

Page 134: ... R15 psr CPSR CPSR_all SPSR or SPSR_all CPSR and CPSR_all are synonyms as are SPSR and SPSR_all psrf CPSR_flg or SPSR_flg expression Where this is used the assembler will attempt to generate a shifted immediate 8 bit field to match the expression If this is impossible it will give an error Examples In User mode the instructions behave as follows MSR CPSR_all Rm CPSR 31 28 Rm 31 28 MSR CPSR_flg Rm ...

Page 135: ...nstruction work on operands which may be considered as signed 2 complement or unsigned integers The results of a signed multiply nd of an unsigned multiply of 32 bit operands differ only in the upper 32 bits the low 32 bits of the signed and unsigned results are identical As these instructions only produce the low 32 bits of a multiply they can be used for both signed and unsigned multiplies For e...

Page 136: ...he number of 8 bit multiplier array cycles is required to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows 1 If bits 32 8 of the multiplier operand are all zero or all one 2 If bits 32 16 of the multiplier operand are all zero or all one 3 If bits 32 24 of the multiplier operand are all zero or all one 4 In all othe...

Page 137: ...LL and SMULL take two 32 bit numbers and multiply them to produce a 64 bit result of the form RdHi RdLo Rm Rs The lower 32 bits of the 64 bit result are written to RdLo the upper 32 bits of the result are written to RdHi The multiply accumulate forms UMLAL and SMLAL take two 32 bit numbers multiply them and add a 64 bit number to produce a 64 bit result of the form RdHi RdLo Rm Rs RdHi RdLo The lo...

Page 138: ...ired to complete the multiply which is controlled by the value of the multiplier operand specified by Rs Its possible values are as follows For Signed Instructions SMULL SMLAL If bits 31 8 of the multiplier operand are all zero or all one If bits 31 16 of the multiplier operand are all zero or all one If bits 31 24 of the multiplier operand are all zero or all one In all other cases For Unsigned I...

Page 139: ...cumulate long 32 x 32 64 64 SMULL cond S RdLo RdHi Rm Rs Signed multiply long 32 x 32 64 SMLAL cond S RdLo RdHi Rm Rs Signed multiply Accumulate long 32 x 32 64 64 where cond Two character condition mnemonic See Table 3 2 S Set condition codes if S present RdLo RdHi Rm Rs Expressions evaluating to a register number other than R15 Examples UMULL R1 R4 R2 R3 R4 R1 R2 R3 UMLALS R1 R5 R2 R3 R5 R1 R2 R...

Page 140: ...quired 31 27 19 15 0 Cond 28 16 11 12 21 23 B 20 L Rn Rd 22 01 I P U Offset W 26 24 25 15 12 Source Destination Registers 19 16 Base Register 20 Load Store Bit 0 Store to memory 1 Load from memory 21 Write back Bit 0 No write back 1 Write address into base 22 Byte Word Bit 0 Transfer word quantity 1 Transfer byte quantity 23 Up Down Bit 0 Down subtract offset from base 1 Up add offset to base 24 P...

Page 141: ...ure 3 5 3 9 3 BYTES AND WORDS This instruction class may be used to transfer a byte B 1 or a word B 0 between an ARM9TDMI register and memory The action of LDR B and STR B instructions is influenced by the BIGEND control signal of ARM9TDMI core The two possible configurations are described below 3 9 3 1 Little Endian Configuration A byte load LDRB expects the data on data bus inputs 7 through 0 if...

Page 142: ...oss data bus outputs 31 through 0 The external memory system should activate the appropriate byte subsystem to store the data A word load LDR should generate a word aligned address An address offset of 0 or 2 from a word boundary will cause the data to be rotated into the register so that the addressed byte occupies bits 31 through 24 This means that half words accessed at these offsets will be co...

Page 143: ...register Rn gets updated before the abort handler starts Sometimes it may be impossible to calculate the initial value Example LDR R0 R1 R1 Therefore a post indexed LDR or STR where Rm is the same register as Rn should not be used 3 9 6 DATA ABORTS A transfer to or from a legal address may cause problems for a memory management system For instance in a system which uses virtual memory the required...

Page 144: ...ing In this case base write back should not be specified Address can be 1 An expression which generates an address The assembler will attempt to generate an instruction using the PC as a base and a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre ind...

Page 145: ... R1 R2 R4 Store R1 at R2 and write back R2 R4 to R2 LDR R1 R2 16 Load R1 from contents of R2 16 but don t write back LDR R1 R2 R3 LSL 2 Load R1 from contents of R2 R3 4 LDREQB R1 R6 5 Conditionally load byte at R6 5 into R1 bits 0 to 7 filling bits 8 to 31 with zeros STR R1 PLACE Generate PC relative offset to address PLACE PLACE ...

Page 146: ...lculation may be written back into the base register if auto indexing is required 31 27 19 15 Cond 28 16 11 12 21 23 0 20 L Rn Rd 3 0 Offset Register 6 5 S H 0 0 SWP instruction 0 1 Unsigned halfwords 1 1 Signed byte 1 1 Signed half words 15 12 Source Destination Register 19 16 Base Register 20 Load Store 0 Store to memory 1 Load from memory 21 Write back 0 No write back 1 Write address into base ...

Page 147: ... base may be either a 8 bit unsigned binary immediate value in the instruction or a second register The 8 bit offset is formed by concatenating bits 11 to 8 and bits 3 to 0 of the instruction word such that bit 11 becomes the MSB and bit 0 becomes the LSB The offset may be added to U 1 or subtracted from U 0 the base register Rn The offset modification may be performed either before pre indexed P ...

Page 148: ...nfiguration A signed byte load LDRSB expects data on data bus inputs 7 through to 0 if the supplied address is on a word boundary on data bus inputs 15 through to 8 if it is a word address plus one byte and so on The selected byte is placed in the bottom 8 bit of the destination register and the remaining bits of the register are filled with the sign bit bit 7 of the byte Please see Figure 2 2 A h...

Page 149: ... 0 The external memory system should activate the appropriate half word subsystem to store the data Note that the address must be half word aligned if bit 0 of the address is HIGH this will cause unpredictable behaviour 3 10 5 USE OF R15 Write back should not be specified if R15 is specified as the base register Rn When using R15 as the base register you must remember it contains an address 8 byte...

Page 150: ...a corrected immediate offset to address the location given by evaluating the expression This will be a PC relative pre indexed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn expression offset of expression bytes Rn Rm offset of contents of index register 3 A post indexed addressing specification Rn expression offset o...

Page 151: ... the half word in R3 at R14 14 but don t write back LDRSB R8 R2 223 Load R8 with the sign extended contents of the byte address contained in R2 and write back R2 223 to R2 LDRNESH R11 R0 Conditionally load R11 with the sign extended contents of the half word address contained in R0 HERE Generate PC relative offset to address FRED STRH R5 PC FRED HERE 8 Store the half word in R5 at address FRED FRE...

Page 152: ...d in the instruction with each bit corresponding to a register A 1 in bit 0 of the register field will cause R0 to be transferred a 0 will cause it not to be transferred similarly bit 1 controls the transfer of R1 and so on Any subset of the registers or all the registers may be specified The only restriction is that the register list should not be empty Whenever R15 is stored to memory the stored...

Page 153: ...r transfers the addresses used and the value of Rn after the instruction has completed In all cases had write back of the modified base not been required W 0 Rn would have retained its initial value of 0x1000 unless it was also in the transfer list of a load multiple register instruction when it would have been overwritten with the loaded value 3 11 3 ADDRESS ALIGNMENT The address should normally ...

Page 154: ...C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3 20 Pre Increment Addressing Rn 1 R1 R1 2 R5 3 R1 R5 4 R7 Rn 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 0x100C 0x1000 0x0FF4 Figure 3 21 Post Decrement Addressing ...

Page 155: ... Transfer The registers transferred are taken from the user bank rather than the bank corresponding to the current mode This is useful for saving the user state on process switches Base write back should not be used when this mechanism is employed 3 11 4 3 R15 not in List and S Bit Set User Bank Transfer For both LDM and STM instructions the user bank registers are transferred rather than the regi...

Page 156: ...o the internal state of the processor will be the modification of the base register if write back was specified and this must be reversed by software and the cause of the abort resolved before the instruction may be retried 3 11 7 2 Aborts During LDM Instructions When ARM9TDMI detects a data abort during a load multiple instruction it modifies the operation of the instruction to ensure that recove...

Page 157: ...truction are shown in the following table 3 6 Table 3 6 Addressing Mode Names Name Stack Other L Bit P Bit U Bit Pre Increment load LDMED LDMIB 1 1 1 Post Increment load LDMFD LDMIA 1 0 1 Pre Decrement load LDMEA LDMDB 1 1 0 Post Decrement load LDMFA LDMDA 1 0 0 Pre Increment store STMFA STMIB 0 1 1 Post Increment store STMEA STMIA 0 0 1 Pre Decrement store STMFD STMDB 0 1 0 Post Decrement store S...

Page 158: ... in privileged modes STMFD R13 R0 R14 Save user mode regs on stack allowed only in privileged modes These instructions may be used to save state on subroutine entry and restore it efficiently on return to the calling routine STMED SP R0 R3 R14 Save R0 to R3 to use as workspace and R14 for returning BL somewhere This nested call will overwrite R14 LDMED SP R0 R3 R15 Restore workspace and return ...

Page 159: ...e processor first reads the contents of the swap address Then it writes the contents of the source register Rm to the swap address and stores the old memory contents in the destination register Rd The same register may be specified as both the source and destination The lock output goes HIGH for the duration of the read and write operations to signal to the external memory manager that they are lo...

Page 160: ...2 4 INSTRUCTION CYCLE TIMES Swap instructions take 1S 2N 1I incremental cycles to execute where S N and I are defined as squential S cycle non sequential and internal I cycle respectively 3 12 5 ASSEMBLER SYNTAX SWP cond B Rd Rm Rn cond Two character condition mnemonic See Table 3 2 B If B is present then byte transfer otherwise word transfer Rd Rm Rn Expressions evaluating to valid register numbe...

Page 161: ...erating system may be constructed 3 13 1 RETURN FROM THE SUPERVISOR The PC is saved in R14_svc upon entering the software interrupt trap with the PC adjusted to point to the word after the SWI instruction MOVS PC R14_svc will return to the calling program and restore the CPSR Note that the link mechanism is not re entrant so if the supervisor code wishes to use software interrupts within itself it...

Page 162: ...B Supervisor SWI entry point EntryTable Addresses of supervisor routines DCD ZeroRtn DCD ReadCRtn DCD WriteIRtn Zero EQU 0 ReadC EQU 256 WriteI EQU 512 Supervisor SWI has routine required in bits 8 23 and data if any in bits 0 7 Assumes R13_svc points to a suitable stack STMFD R13 R0 R2 R14 Save work registers and return address LDR R0 R14 4 Get SWI instruction BIC R0 R0 0xFF000000 Clear top 8 bit...

Page 163: ...connected to the S3C2500B the coprocessor instructions are still described here in full for completeness Remember that any external coprocessor described in this section is a software emulation 31 24 27 19 15 Cond CRm 28 16 11 12 23 20 3 0 Coprocessor operand register 7 5 Coprocessor information 11 8 Coprocessor number 15 12 Coprocessor destination register 19 16 Coprocessor operand register 23 20...

Page 164: ...er condition mnemonic See Table 3 2 p The unique number of the required coprocessor expression1 Evaluated to a constant and placed in the CP Opc field cd cn and cm Evaluate to the valid coprocessor register numbers CRd CRn and CRm respectively expression2 Where present is evaluated to a constant and placed in the CP field Examples CDP p1 10 c1 c2 c3 Request coproc 1 to do operation 10 on CR2 and C...

Page 165: ...n subtract offset from base 1 Up add offset to base 24 Pre Post Indexing Bit 0 Post add offset after transfer 1 Pre add offset bofore transfer 31 28 Condition Field 31 27 19 15 Cond 28 16 11 12 21 23 N 20 L Rn CRd 22 110 P U CP W 24 25 Offset 8 7 0 Figure 3 26 Coprocessor Data Transfer Instructions 3 15 1 THE COPROCESSOR FIELDS The CP field is used to identify the coprocessor which is required to ...

Page 166: ...if more than one is transferred will go to or come from an address one word 4 bytes higher than the first transfer and the address will be incremented by one word for each subsequent transfer 3 15 3 ADDRESS ALIGNMENT The base address should normally be a word aligned quantity The bottom 2 bits of the address will appear on A 1 0 and might be interpreted by the memory system 3 15 4 USE OF R15 If Rn...

Page 167: ...ed address If the address is out of range an error will be generated 2 A pre indexed addressing specification Rn offset of zero Rn expression offset of expression bytes A post indexed addressing specification Rn expression offset of expression bytes write back the base register set the W bit if is present Rn is an expression evaluating to a valid ARM9TDMI register number NOTE If Rn is R15 the asse...

Page 168: ...be moved to the CPSR to control the subsequent flow of execution 31 27 19 15 Cond 28 16 11 12 21 23 20 L CRn Rd 3 0 Coprocessor Operand Register 7 5 Coprocessor Information 11 8 Coprocessor Number 15 12 ARM Source Destination Register 19 16 Coprocessor Source Destination Register 20 Load Store Bit 0 Store to coprocessor 1 Load from coprocessor 21 Coprocessor Operation Mode 31 28 Condition Field 11...

Page 169: ...ent in the coprocessor busy wait loop 3 16 5 ASSEMBLER SYNTAX MCR MRC cond p expression1 Rd cn cm expression2 MRC Move from coprocessor to ARM9TDMI register L 1 MCR Move from ARM9TDMI register to coprocessor L 0 cond Two character condition mnemonic See Table 3 2 p The unique number of the required coprocessor expression1 Evaluated to a constant and placed in the CP Opc field Rd An expression eval...

Page 170: ...e undefined instruction mechanism involves offering this instruction to any coprocessors which may be present and all coprocessors must refuse to accept it by driving CPA and CPB HIGH 3 17 1 INSTRUCTION CYCLE TIMES This instruction takes 2S 1I 1N cycles where S N and I are defined as sequential S cycle non sequential N cycle and internal I cycle 3 17 2 ASSEMBLER SYNTAX The assembler has no mnemoni...

Page 171: ... for Logical OR CMP Rn p If Rn p OR Rm q THEN GOTO Label BEQ Label CMP Rm q BEQ Label This can be replaced by CMP Rn p CMPNE Rm q If condition not satisfied try other test BEQ Label Absolute Value TEQ Rn 0 Test sign RSBMI Rn Rn 0 and 2 s complement if necessary Multiplication by 4 5 or 6 Run Time MOV Rc Ra LSL 2 Multiply by 4 CMP Rb 5 Test value ADDCS Rc Rc Ra Complete multiply by 5 ADDHI Rc Rc Ra...

Page 172: ... ADDCS Rc Rc Rcnt Put relevant bit into result MOVS Rcnt Rcnt LSR 1 Shift control bit MOVNE Rb Rb LSR 1 Halve unless finished BNE Div2 Divide result in Rc remainder in Ra Overflow Detection in the ARM9TDMI 1 Overflow in unsigned multiply with a 32 bit result UMULL Rd Rt Rm Rn 3 to 6 cycles TEQ Rt 0 1 cycle and a register BNE overflow 2 Overflow in signed multiply with a 32 bit result SMULL Rd Rt R...

Page 173: ...eedback rather like a cyclic redundancy check generator Unfortunately the sequence of a 32 bit generator needs more than one feedback tap to be maximal length i e 2 32 1 cycles before repetition so this example uses a 33 bit register with taps at bits 33 and 20 The basic algorithm is newbit bit 33 eor bit 20 shift left the 33 bit number and put in newbit at the bottom this operation is performed f...

Page 174: ...Rb Ra LSL n D 1 Rb Ra D MOV Rb Rb LSL n 2 If C MOD 4 1 say C 2 n D 1 D odd n 1 D 1 ADD Rb Ra Ra LSL n D 1 Rb Ra D ADD Rb Ra Rb LSL n 3 If C MOD 4 3 say C 2 n D 1 D odd n 1 D 1 RSB Rb Ra Ra LSL n D 1 Rb Ra D RSB Rb Ra Rb LSL n This is not quite optimal but close An example of its non optimality is multiply by 45 which is done by RSB Rb Ra Ra LSL 2 Multiply by 3 RSB Rb Ra Rb LSL 2 Multiply by 4 3 1 ...

Page 175: ...be less than c e g 0 1 BIC Rb Ra 3 Get word aligned address LDMIA Rb Rd Rc Get 64 bits containing answer AND Rb Ra 3 Correction factor in bytes MOVS Rb Rb LSL 3 now in bits and test if aligned MOVNE Rd Rd LSR Rb Produce bottom of result word if not aligned RSBNE Rb Rb 32 Get other shift amount ORRNE Rd Rd Rc LSL Rb Combine two halves to get result ...

Page 176: ... 0 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 0 L 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 0 0 L 1 0 R 1 1 0 1 0 SP 1 L L S H 0 0 1 B L 0 1 H 0 1 B 0 0 1 1 1 I Op Op Op Op Op L 0 S 1 Offset5 Rs Rd Rn offset3 Rd Rs Rd Offset8 Rs Rd Hd Rd H1 H2 Rs Hs Rd Word8 Rd Rb Ro Ro Rb Rd Offset5 Rb Rd Rb Rd Offset5 Rd Rd Word8 Word8 SWord7 Rb Cond Rlist Rlist Softset8 Value8 Offset11 Offset Add sub...

Page 177: ...V V 1 AND AND V V ASR Arithmetic shift right V V B Unconditional branch V Bxx Conditional branch V BIC Bit clear V V BL Branch and link V BX Branch and exchange V V CMN Compare negative V V CMP Compare V V V EOR EOR V V LDMIA Load multiple V LDR Load word V LDRB Load byte V LDRH Load half word V LSL Logical shift left V V LDSB Load sign extended byte V LDSH Load sign extended half word V LSR Logic...

Page 178: ...odes Set SBC Subtract with carry V V STMIA Store multiple V STR Store word V STRB Store byte V STRH Store half word V SWI Software interrupt SUB Subtract V V TST Test bits V V NOTES 1 The condition codes are unaffected by the format 5 12 and 13 versions of this instruction 2 The condition codes are unaffected by the format 5 version of this instruction ...

Page 179: ... Offset5 MOVS Rd Rs LSL Offset5 Shift Rs left by a 5 bit immediate value and store the result in Rd 01 LSR Rd Rs Offset5 MOVS Rd Rs LSR Offset5 Perform logical shift right on Rs by a 5 bit immediate value and store the result in Rd 10 ASR Rd Rs Offset5 MOVS Rd Rs ASR Offset5 Perform arithmetic shift right on Rs by a 5 bit immediate value and store the result in Rd 3 20 2 INSTRUCTION CYCLE TIMES Al...

Page 180: ...ted from a Lo register The THUMB assembler syntax is shown in Table 3 9 NOTE All instructions in this group set the CPSR condition codes Table 3 9 Summary of Format 2 Instructions OP I THUMB Assembler ARM Equivalent Action 0 0 ADD Rd Rs Rn ADDS Rd Rs Rn Add contents of Rn to contents of Rs Place result in Rd 0 1 ADD Rd Rs Offset3 ADDS Rd Rs Offset3 Add 3 bit immediate value to contents of Rs Place...

Page 181: ... format have an equivalent ARM instruction as shown in Table 3 9 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples ADD R0 R3 R4 R0 R3 R4 and set condition codes on the result SUB R6 R2 6 R6 R2 6 and set condition codes ...

Page 182: ...t8 MOVS Rd Offset8 Move 8 bit immediate value into Rd 01 CMP Rd Offset8 CMP Rd Offset8 Compare contents of Rd with 8 bit immediate value 10 ADD Rd Offset8 ADDS Rd Rd Offset8 Add 8 bit immediate value to contents of Rd and place the result in Rd 11 SUB Rd Offset8 SUBS Rd Rd Offset8 Subtract 8 bit immediate value from contents of Rd and place the result in Rd 3 22 2 INSTRUCTION CYCLE TIMES All instr...

Page 183: ... Rs 0001 EOR Rd Rs EORS Rd Rd Rs Rd Rd EOR Rs 0010 LSL Rd Rs MOVS Rd Rd LSL Rs Rd Rd Rs 0011 LSR Rd Rs MOVS Rd Rd LSR Rs Rd Rd Rs 0100 ASR Rd Rs MOVS Rd Rd ASR Rs Rd Rd ASR Rs 0101 ADC Rd Rs ADCS Rd Rd Rs Rd Rd Rs C bit 0110 SBC Rd Rs SBCS Rd Rd Rs Rd Rd Rs NOT C bit 0111 ROR Rd Rs MOVS Rd Rd ROR Rs Rd Rd ROR Rs 1000 TST Rd Rs TST Rd Rs Set condition codes on Rd AND Rs 1001 NEG Rd Rs RSBS Rd Rs 0 ...

Page 184: ...n are identical to that of the equivalent ARM instruction Examples EOR R3 R4 R3 R3 EOR R4 and set condition codes ROR R1 R0 Rotate right R1 by the value in R0 store the result in R1 and set condition codes NEG R5 R3 Subtract the contents of R3 from zero store the result in R5 Set condition codes ie R5 R3 CMP R2 R6 Set the condition codes on the result of R2 R6 MUL R0 R7 R0 R7 R0 and set condition ...

Page 185: ...TION There are four sets of instructions in this group The first three allow ADD CMP and MOV operations to be performed between Lo and Hi registers or a pair of Hi registers The fourth BX allows a Branch to be performed which may also be used to switch processor state The THUMB assembler syntax is shown in Table 3 12 NOTE In this group only CMP Op 01 sets the CPSR condition codes The action of H1 ...

Page 186: ...ge 8 15 to a register in the range 0 7 10 1 0 MOV Hd Rs MOV Hd Rs Move a value from a register in the range 0 7 to a register in the range 8 15 00 0 1 MOV Hd Hs MOV Hd Hs Move a value between two registers in the range 8 15 00 1 0 BX Rs BX Rs Perform branch plus optional state change to address in a register in the range 0 7 00 1 1 BX Hs BX Hs Perform branch plus optional state change to address i...

Page 187: ...m THUMB to ARM state ADR R1 outofTHUMB Load address of outofTHUMB into R1 MOV R11 R1 BX R11 Transfer the contents of R11 into the PC Bit 0 of R11 determines whether ARM or THUMB state is entered ie ARM state here ALIGN CODE32 outofTHUMB Now processing ARM instructions 3 24 4 USING R15 AS AN OPERAND If R15 is used as an operand the value will be the address of the instruction 4 with bit 0 cleared E...

Page 188: ...d from the resulting address into Rd NOTE The value specified by Imm is a full 10 bit address but must always be word aligned ie with bits 1 0 set to 0 since the assembler places Imm 2 in field Word 8 The value of the PC will be 4 bytes greater than the address of this instruction but bit 1 of the PC is forced to 0 to ensure it is word aligned 3 25 2 INSTRUCTION CYCLE TIMES All instructions in thi...

Page 189: ...ormat 7 Instructions L B THUMB Assembler ARM Equivalent Action 0 0 STR Rd Rb Ro STR Rd Rb Ro Pre indexed word store Calculate the target address by adding together the value in Rb and the value in Ro Store the contents of Rd at the address 0 1 STRB Rd Rb Ro STRB Rd Rb Ro Pre indexed byte store Calculate the target address by adding together the value in Rb and the value in Ro Store the byte value ...

Page 190: ... ARM instruction as shown in Table 3 14 The instruction cycle times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STR R3 R2 R6 Store word in R3 at the address formed by adding R6 to R2 LDRB R2 R0 R7 Load into R2 the byte found at the address formed by adding R7 to R0 ...

Page 191: ...ormat 8 instructions L B THUMB Assembler ARM Equivalent Action 0 0 STRH Rd Rb Ro STRH Rd Rb Ro Store half word Add Ro to base address in Rb Store bits 0 15 of Rd at the resulting address 0 1 LDRH Rd Rb Ro LDRH Rd Rb Ro Load half word Add Ro to base address in Rb Load bits 0 15 of Rd from the resulting address and set bits 16 31 of Rd to 0 1 0 LDSB Rd Rb Ro LDRSB Rd Rb Ro Load sign extended byte Ad...

Page 192: ...es for the THUMB instruction are identical to that of the equivalent ARM instruction Examples STRH R4 R3 R0 Store the lower 16 bits of R4 at the address formed by adding R0 to R3 LDSB R2 R7 R1 Load into R2 the sign extended byte found at the address formed by adding R1 to R7 LDSH R3 R4 R2 Load into R3 the sign extended half word found at the address formed by adding R2 to R4 ...

Page 193: ... Assembler ARM Equivalent Action 0 0 STR Rd Rb Imm STR Rd Rb Imm Calculate the target address by adding together the value in Rb and Imm Store the contents of Rd at the address 0 1 LDR Rd Rb Imm LDR Rd Rb Imm Calculate the source address by adding together the value in Rb and Imm Load Rd from the address 1 0 STRB Rd Rb Imm STRB Rd Rb Imm Calculate the target address by adding together the value in...

Page 194: ... the THUMB instruction are identical to that of the equivalent ARM instruction Examples LDR R2 R5 116 Load into R2 the word found at the address formed by adding 116 to R5 Note that the THUMB opcode will contain 29 as the Offset5 value STRB R1 R0 13 Store the lower 8 bits of R1 at the address formed by adding 13 to R0 Note that the THUMB opcode will contain 13 as the Offset5 value ...

Page 195: ... Rd at the resulting address 1 LDRH Rd Rb Imm LDRH Rd Rb Imm Add Imm to base address in Rb Load bits 0 15 from the resulting address into Rd and set bits 16 31 to zero NOTE Imm is a full 6 bit address but must be half word aligned ie with bit 0 set to 0 since the assembler places Imm 1 in the Offset5 field 3 29 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instru...

Page 196: ...the SP R7 Store the contents of Rd at the resulting address 1 LDR Rd SP Imm LDR Rd R13 Imm Add unsigned offset 255 words 1020 bytes in Imm to the current value of the SP R7 Load the word from the resulting address into Rd NOTE The offset supplied in Imm is a full 10 bit address but must always be word aligned ie bits 1 0 set to 0 since the assembler places Imm 2 in the Word8 field 3 30 2 INSTRUCTI...

Page 197: ...ARM Equivalent Action 0 ADD Rd PC Imm ADD Rd R15 Imm Add Imm to the current value of the program counter PC and load the result into Rd 1 ADD Rd SP Imm ADD Rd R13 Imm Add Imm to the current value of the stack pointer SP and load the result into Rd NOTE The value specified by Imm is a full 10 bit value but this must be word aligned ie with bits 1 0 set to 0 since the assembler places Imm 2 in field...

Page 198: ... times for the THUMB instruction are identical to that of the equivalent ARM instruction Examples ADD R2 PC 572 R2 PC 572 but don t set the condition codes bit 1 of PC is forced to zero Note that the THUMB opcode will contain 143 as the Word8 value ADD R6 SP 212 R6 SP R13 212 but don t set the condition codes Note that the THUMB opcode will contain 53 as the Word 8 value ...

Page 199: ...er SP NOTE The offset specified by Imm can be up to 508 but must be word aligned ie with bits 1 0 set to 0 since the assembler converts Imm to an 8 bit sign magnitude number before placing it in field SWord7 The condition codes are not set by this instruction 3 32 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 20 The instruction cyc...

Page 200: ...in Table 3 21 NOTE The stack is always assumed to be full descending Table 3 21 PUSH and POP Instructions L B THUMB Assembler ARM Equivalent Action 0 0 PUSH Rlist STMDB R13 Rlist Push the registers specified by Rlist onto the stack Update the stack pointer 0 1 PUSH Rlist LR STMDB R13 Rlist R14 Push the Link Register and the registers specified by Rlist if any onto the stack Update the stack pointe...

Page 201: ...THUMB instruction are identical to that of the equivalent ARM instruction Examples PUSH R0 R4 LR Store R0 R1 R2 R3 R4 and R14 LR at the stack pointed to by R13 SP and update R13 Useful at start of a sub routine to save workspace and return address POP R2 R6 PC Load R2 R6 and R15 PC from the stack pointed to by R13 SP and update R13 Useful to restore workspace and return from sub routine ...

Page 202: ...ist STMIA Rb Rlist Store the registers specified by Rlist starting at the base address in Rb Write back the new base address 1 LDMIA Rb Rlist LDMIA Rb Rlist Load the registers specified by Rlist starting at the base address in Rb Write back the new base address 3 34 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 22 The instruction c...

Page 203: ...ch Instructions Code THUMB Assembler ARM Equivalent Action 0000 BEQ label BEQ label Branch if Z set equal 0001 BNE label BNE label Branch if Z clear not equal 0010 BCS label BCS label Branch if C set unsigned higher or same 0011 BCC label BCC label Branch if C clear unsigned lower 0100 BMI label BMI label Branch if N set negative 0101 BPL label BPL label Branch if N clear positive or zero 0110 BVS...

Page 204: ...cifies a full 9 bit two s complement address this must always be half word aligned ie with bit 0 set to 0 since the assembler actually places label 1 in field SOffset8 2 Cond 1110 is undefined and should not be used Cond 1111 creates the SWI instruction see 3 35 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in Table 3 23 The instruction cycle...

Page 205: ...nt Action SWI Value 8 SWI Value 8 Perform Software Interrupt Move the address of the next instruction into LR move CPSR to SPSR load the SWI vector address 0x8 into the PC Switch to ARM state and enter SVC mode NOTE Value 8 is used solely by the SWI handler it is ignored by the processor 3 36 2 INSTRUCTION CYCLE TIMES All instructions in this format have an equivalent ARM instruction as shown in T...

Page 206: ...uction Table 3 25 Summary of Branch Instruction THUMB Assembler ARM Equivalent Action B label BAL label half word offset Branch PC relative Offset11 1 where label is PC 2048 bytes NOTE The address specified by label is a full 12 bit two s complement address but must always be half word aligned ie bit 0 set to 0 since the assembler places label 1 in the Offset11 field Examples here B here Branch on...

Page 207: ...ction 1 H 0 In the first instruction the Offset field contains the upper 11 bits of the target address This is shifted left by 12 bits and added to the current PC address The resulting address is placed in LR 3 38 1 2 Instruction 2 H 1 In the second instruction the Offset field contains an 11 bit representation lower half of the target address This is shifted left by 1 bit and added to LR LR which...

Page 208: ... Equivalent Action 0 BL label none LR PC OffsetHigh 12 1 temp next instruction address PC LR OffsetLow 1 LR temp 1 Examples BL faraway Unconditionally Branch to faraway next and place following instruction address ie next in R14 the Link register and set bit 0 of LR high Note that the THUMB opcodes will contain the number of half words to offset faraway Must be Half word aligned ...

Page 209: ... using a sequence of 4 or more instructions Thumb ARM 1 Multiplication by 2 n 1 2 4 8 LSL Ra Rb LSL n MOV Ra Rb LSL n 2 Multiplication by 2 n 1 3 5 9 17 LSL Rt Rb n ADD Ra Rb Rb LSL n ADD Ra Rt Rb 3 Multiplication by 2 n 1 3 7 15 LSL Rt Rb n RSB Ra Rb Rb LSL n SUB Ra Rt Rb 4 Multiplication by 2 n 2 4 8 LSL Ra Rb n MOV Ra Rb LSL n MVN Ra Ra RSB Ra Ra 0 5 Multiplication by 2 n 1 3 7 15 LSL Rt Rb n S...

Page 210: ...0 and ADD 1 SUB 1 to get abs value Save signs 0 or 1 in R0 R2 for later use in determining sign of quotient remainder PUSH R0 R2 Justification shift 1 bit at a time until divisor R0 value is just than dividend R1 value To do this shift dividend right by 1 and stop as soon as shifted value becomes LSR R0 R1 1 MOV R2 R3 B FT0 just_l LSL R2 1 0 CMP R2 R0 BLS just_l MOV R0 0 Set accumulator to 0 B FT0...

Page 211: ...a2 a2 0 Central part is identical code to udiv without MOV a4 0 which comes for free as part of signed entry sequence MOVS a3 a1 BEQ divide_by_zero just_l Justification stage shifts 1 bit at a time CMP a3 a2 LSR 1 MOVLS a3 a3 LSL 1 NB LSL 1 is always OK if LS succeeds BLO s_loop div_l CMP a2 a3 ADC a4 a4 a4 SUBCS a2 a2 a3 TEQ a3 a1 MOVNE a3 a3 LSR 1 BNE s_loop2 MOV a1 a4 MOVS ip ip ASL 1 RSBCS a1 ...

Page 212: ...ment in a1 returns quotient in a1 remainder in a2 MOV a2 a1 LSR a3 a1 2 SUB a1 a3 LSR a3 a1 4 ADD a1 a3 LSR a3 a1 8 ADD a1 a3 LSR a3 a1 16 ADD a1 a3 LSR a1 3 ASL a3 a1 2 ADD a3 a1 ASL a3 1 SUB a2 a3 CMP a2 10 BLT FT0 ADD a1 1 SUB a2 10 0 MOV pc lr 3 39 3 2 ARM Code udiv10 Take argument in a1 returns quotient in a1 remainder in a2 SUB a2 a1 10 SUB a1 a1 a1 lsr 2 ADD a1 a1 a1 lsr 4 ADD a1 a1 a1 lsr ...

Page 213: ...method and address remap function etc 4 2 FEATURES Key features of the system configuration include the following Various clock mode operation the fastbus mode sync mode and async mode Product code and revision number System clock control clock status Peripheral clock enable disable AHB bus master priority define Fixed Round Robin Core System USB PHY PLL Configuration Register Setting ...

Page 214: ...00 0x00000000 0x48000000 Figure 4 1 S3C2500B Address map after resest Each memory block is mapped within the fixed location of memory space As shown in the figure 4 1 the maximum size of ROM SRAM Flash External IO bank is restricted to 16M bytes and the SDRAM bank can be mapped within 1G byte memory space It must be noticed that the base address of each bank is fixed and the bank size is variable ...

Page 215: ...04000000 0x84000000 Memory bank5 0x05000000 0x85000000 Memory bank6 0x06000000 0x86000000 Memory bank7 0x07000000 0x87000000 SDRAM bank0 0x40000000 0x00000000 SDRAM bank1 0x80000000 0x40000000 4 5 EXTERNAL ADDRESS TRANSLATION The S3C2500B address bus is in some respects different than the bus used in other standard CPUs Based on the required data bus width of each memory bank the internal system a...

Page 216: ...B has 6 AHB bus masters General DMA Ethernet Controller 0 Ethernet Controller 1 HDLC Controller 0 HDLC Controller 1 and HDLC Controller 2 The S3C2500B can program the bus priority of each bus masters among Group B So the bus priority of bus masters in only Group B can be programmed Group C has the ARM940T CPU The relative priority of Group B and Group C is determined more or less in an alternating...

Page 217: ...order from the highest to the lowest is Ethernet Controller 0 General DMA HDLC Controller 2 Ethernet Controller 1 HDLC Controller 0 and HDLC Controller 1 If system configuration register 0xF0000000 SYSCFG 0 0x0 the programmable round robin priority is run by HPRIR register All AHB bus masters own their respective field position in HPRIR The ratio of the bus occupancy can be programmed by writing a...

Page 218: ...hprif4 hprif5 24 31 Reserved AHB Masters Index for HPRIF Field for HPRIR General DMA GDMA 0 HPRIR 3 0 Ethernet Contoller 0 1 HPRIR 7 4 Ethernet Contoller 1 2 HPRIR 11 8 HDLC Controller 0 3 HPRIR 15 12 HDLC Controller 1 4 HPRIR 19 16 HDLC Controller 2 5 HPRIR 23 20 x 0 1 31 0 System bus arbitration method ARB 0 Round robin 1 Fixed priority SYSCFG NOTE See page 4 16 and 4 17 Figure 4 4 AHB Programma...

Page 219: ...6 4 0 Not Used 0 GDMA 1 6 5 0 Not Used 0 GDMA 1 6 6 0 Not Used 0 GDMA 1 6 When HPRIR is 0x0 and only GDMA Ethernet controller 0 and 1 are used the expected bus occupancy for each channel is 1 3 However S3C2500B does not work in that way instead GDMA gets 4 6 of the bus occupancy Ethernet controller 0 1 6 and Ethernet controller 1 1 6 In short GDMA is run four times more than Ethernet controller 0 ...

Page 220: ... GDMA 1 3 0 Ethernet controller 0 1 3 1 6 3 Ethernet controller 0 1 3 0 Ethernet controller 1 1 3 1 6 3 Ethernet controller 1 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Problem Problem Solving Writing 0x000330 instead of 0x0 will give each channel of three masters with the same amount of bus occupancy This is because GDMA is run to fill the blank of non used masters in this case HDLC0 HDLC1 HDLC2 ...

Page 221: ...ion of the ARM940T clock and the system clock If the CLKMOD 1 0 is 00 the fastbus clock mode is defined In this mode the ARM940T clock and the system bus clock is the same clock and the clock is from the CPU PLL output The two clocks are of the same phase and of the same frequency If the CLKMOD 1 0 is 11 the async clock mode is defined In this mode the ARM940T clock is out of the CPU PLL and the s...

Page 222: ... 48MHz 3 b010 3 b010 133MHz 133MHz 48MHz 3 b010 3 b011 133MHz 125MHz 48MHz 3 b010 3 b100 133MHz 100MHz 48MHz 3 b010 3 b101 133MHz 66MHz 48MHz 3 b010 3 b110 133MHz 50MHz 48MHz 3 b010 3 b111 133MHz 33MHz 48MHz 2 b11 Async 3 b011 3 b000 125MHz 133MHz 48MHz 3 b011 3 b001 125MHz 133MHz 48MHz 3 b011 3 b010 125MHz 133MHz 48MHz 3 b011 3 b011 125MHz 125MHz 48MHz 3 b011 3 b100 125MHz 100MHz 48MHz 3 b011 3 b...

Page 223: ...133MHz 48MHz 3 b101 3 b010 66MHz 133MHz 48MHz 3 b101 3 b011 66MHz 125MHz 48MHz 3 b101 3 b100 66MHz 100MHz 48MHz 3 b101 3 b101 66MHz 66MHz 48MHz 3 b101 3 b110 66MHz 50MHz 48MHz 3 b101 3 b111 66MHz 33MHz 48MHz 2 b11 Async 3 b110 3 b000 50MHz 133MHz 48MHz 3 b110 3 b001 50MHz 133MHz 48MHz 3 b110 3 b010 50MHz 133MHz 48MHz 3 b110 3 b011 50MHz 125MHz 48MHz 3 b110 3 b100 50MHz 100MHz 48MHz 3 b110 3 b101 5...

Page 224: ...SCFG 27 24 When the PLL clock enable bit is set to 0 during the PLL control variable change the stable PLL output clock is provided The PLL output frequency is determined as follows Fout Fin M 8 P 2 2 S Where the Fin is the frequency of the PLL input clock and the Fout is the frequency of the PLL output clock The four PLLs in the S3C2500B are controlled by above formula and the table 4 4 shows the...

Page 225: ...he internal clock is PLL output clock between 166MHz and 33MHz CLKCON 1 7 The CLKCON 15 0 register CLKMOD 1 0 pins and CPU_FREQ 2 0 pins can control the AMBA clock divider The CLKMOD 1 0 pins and BUS_FREQ 2 0 pins can generate the various AMBA bus clock frequecies referring to the Table 3 The CLKCON 15 0 register can divide the various AMBA clock frequecies of the Table 4 3 8 All PLL can be contro...

Page 226: ...xternal memory bus the S3C2500 asserts XMBACK high and drives the state of the external memory bus to high impedance after S3C2500 finishes current transfer with memory When the external bus master takes the control of external memory bus it should take care of SDRAM refresh operation S3C2500 can get the control of the memory bus 1 cycle after XBMREQ is deactivated PXBMREQ HCLK PXBMACK Figure 4 6 ...

Page 227: ...0008 System clock control register 0x00000000 PCLKDIS 0xF000000C Peripheral clock disable register 0x00000000 CLKST 0xF0000010 Clock Status register HPRIF 0xF0000014 AHB bus master fixed priority register 0x00543210 HPRIR 0xF0000018 AHB bus master round robin priority register 0x00000000 CPLLCON 0xF000001C Core PLL Configuration Register 0x0001039E SPLLCON 0xF0000020 System BUS PLL Configuration R...

Page 228: ...stant from the two constant values When this bit is set to 0 the BUS PLL constant is always set to generates the clock frequency 4 8 times the input clock When this bit is set to 1 the USB PLL constant is from the UPLLCON register 0 PPLLREN 28 PPLLCON register enable This bit controls which value is used for the PHY PLL constant from the two constant values When this bit is set to 0 the PHY PLL co...

Page 229: ...ndian 1 Big endian REMAP 8 External memory address remapping enable 0 Remap disable 1 Remap Enable ROM Bank0 0x00000000 ROM Bank0 0x80000000 ROM Bank1 0x01000000 ROM Bank1 0x81000000 ROM Bank2 0x02000000 ROM Bank2 0x82000000 ROM Bank3 0x03000000 ROM Bank3 0x83000000 ROM Bank4 0x04000000 ROM Bank4 0x84000000 ROM Bank5 0x05000000 ROM Bank5 0x85000000 ROM Bank6 0x06000000 ROM Bank6 0x86000000 ROM Ban...

Page 230: ...ODE Register Address R W Description Reset Value PDCODE 0xF0000004 R Product code and revision number register 0x250000B0 PDCODE Bit Description Initial State PC 31 16 Product code 0x2500 Reserved 15 8 Reserved 0x0 MajRev 7 4 Major revision number 0xB MinRev 3 0 Minor revision number 0x0 ...

Page 231: ...he internal system clock remains the same as the internal clock In other case the duty cycle of internal system clock is no logner 50 Register Address R W Description Reset Value CLKCON 0xF0000008 R W Clock control register 0x00000000 CLKCON Bit Description Initial State Reserved 31 16 Reserved 0 DVAL 15 0 System clock dividing value If all bits are 0 non divided clock is used Only one bit can be ...

Page 232: ...25 HDLC1 clock disable 0x0 HDLC0 24 HDLC0 clock disable 0x0 SDRAMC 23 SDRAMC clock disable 0x0 MEMCON 22 MEMCON clock disable 0x0 DES 21 DES clock disable 0x0 IIC 20 IIC clock disable 0x0 IOPC 19 IOPC clock disable 0x0 WDT 18 Watch dog timer clock disable 0x0 TIMER5 17 TIMER5 clock disable 0x0 TIMER4 16 TIMER4 clock disable 0x0 TIMER3 15 TIMER3 clock disable 0x0 TIMER2 14 TIMER2 clock disable 0x0 ...

Page 233: ...the CLKST 11 0 should be taken for the BUS frequency because the CPU clock and system bus clock is the same In the sync mode the BUS frequency in the CLKST 23 12 should also be ignored and the half of the CPU frequency should be taken for the BUS frequency Register Address R W Description Reset Value CLKST 0xF0000010 R Clock Status register Read Only CLKST Bit Description Initial State Clock Mode ...

Page 234: ...1C R W Core PLL control register 0x0001039E CPLLCON Bit Description Initial State Reserved 31 12 0x0 S 17 16 Scaler 0x1 Reserved 15 14 0x0 P 13 8 Pre divider 0x3 M 7 0 Main divider 0x9E Output clock frequency is determined by following formula Fout Fin M 8 P 2 2 S If Fin 10MHz P 3 M 158 0x9E and S 1 Fout is 166 MHz FCLK signal of ARM940T core is connected to Fout 166MHz clock But BCLK signal of AR...

Page 235: ...20 R W System BUS PLL control register 0x0001037D SPLLCON Bit Description Initial State Reserved 31 12 0x0 S 17 16 Scaler 0x1 Reserved 15 14 0x0 P 13 8 Pre divider 0x3 M 7 0 Main divider 0x7D Output clock frequency is determined by following formula Fout Fin M 8 P 2 2 S If Fin 10MHz P 3 M 125 0x7D and S 1 Fout is 133 MHz FCLK signal of ARM940T core is connected to Fout 133MHz clock But BCLK signal...

Page 236: ...a Fout Fin M 8 P 2 2 S If Fin 10MHz P 3 M 40 0x28 and S 1 Fout is 48MHz 4 9 10 PHY PLL CONTROL REGISTER PPLLCON If you want to use this register you should set PPLLREN in SYSCFG 28 to 1 This register doesn t work with PPLLREN set to 0 Register Address R W Description Reset Value PPLLCON 0xF0000028 R W PHY PLL control register 0x00010311 PPLLCON Bit Description Initial State Reserved 31 12 0x0 S 17...

Page 237: ...trol signals for external memory accesses For example if a master block such as DMA controller or CPU generates an address that corresponds to a SDRAM bank the SDRAM controller generates the required SDRAM access signals To provide the required signals for bus traffic between the S3C2500B and ROM SRAM and the external I O banks To compensate for differences in bus width for data flowing between th...

Page 238: ...24 bit external address pins 32 bit internal and external data bus Various timing control options NOTE By generating an external bus request an external device can access the S3C2500B s external memory interface pins In addition the S3C2500B can access slow external devices by using a WAIT signal The WAIT signal which is generated by the external device extends the duration of the CPU s memory acc...

Page 239: ...fixed The initial system memory map following system start up is shown in Figure 5 1 Table 5 1 Base Address of Each Bank Bank Base Address EXT I O Bank 0 0x00000000 EXT I O Bank 1 0x01000000 EXT I O Bank 2 0x02000000 EXT I O Bank 3 0x03000000 EXT I O Bank 4 0x04000000 EXT I O Bank 5 0x05000000 EXT I O Bank 6 0x06000000 EXT I O Bank 7 0x07000000 SDRAM Bank 0 0x40000000 SDRAM Bank 1 0x80000000 ...

Page 240: ... Bank 5 EXT I O Bank 4 EXT I O Bank 3 EXT I O Bank 1 EXT I O Bank 2 EXT I O Bank 0 NOTES 1 ROM SRAM Flash and External I O Bank have the same operation in internal logic Therefore you may connect a SRAM or a Flash Memory with a External I O Bank 2 Each EXT I O bank address is fixed with maximum address range S3C2500 has 24 address pins which restrict to 16M byte address 3 Each SDRAM bank supports ...

Page 241: ...ss size for the Bank 0 nOE 1 LOW O Specifies read write state from S3C2500B When S3C2500B read from ext I O device nOE s value is 1 b0 nRCS 8 LOW O Specifies which ext I O device is selected nEWAIT nREADY 1 LOW I Signal be controlled from ext I O slow device to delay cycles in data read and write HCLKO 1 HIGH O S3C2500B system clock out CKE 1 HIGH O Clock enable for SDRAM nSDCS 2 LOW O Chip select...

Page 242: ...gnals ROM SRAM Flash and SDRAM common signals External device interface signals Adjust with pin selection nOE nRCS 7 0 ADDR 23 0 HCLKO CKE nSDCS 1 0 nSDRAS nSDCAS nWBE nBE DQM 3 0 nEWAIT nREADY nSDWE nWE16 B0SIZE 1 0 XBMREQ DATA 31 0 XBMACK S3C2500B Figure 5 2 Memory Controller Bus Signals ...

Page 243: ...Width STORE CPU Reg External Memory 32 bit 16 bit 8 bit Bit Num CPU Register Data 31 0 abcd 31 0 xxab 31 0 xxcd 31 0 xxxa 31 0 xxxb 31 0 xxxc 31 0 xxxd CPU Address WA HA HA 1 BA BA 1 BA 2 BA 3 Bit Num CPU Data Bus 31 0 abcd 31 0 abab 31 0 cdcd 31 0 aaaa 31 0 bbbb 31 0 cccc 31 0 dddd External Address ADDR EA Bit Num External Data 31 0 dcba 31 0 xxba 31 0 dcxx 31 0 xxxa 31 0 xxbx 31 0 xcxx 31 0 dxxx...

Page 244: ...ata 31 0 abcd 31 0 xxab 31 0 xxxa 31 0 xxxb CPU Address WA HA BA BA 1 Bit Num CPU Data Bus 31 0 abcd 31 0 abab 31 0 aaaa 31 0 bbbb External Address ADDR EA EA 1 EA EA Bit Num External Data 15 0 ba 15 0 dc 15 0 ba 15 0 xa 15 0 bx Timing Sequence 1st 2nd Table 5 6 External 16 bit Datawidth Load Operation with Big Endian Transfer Width LOAD CPU Reg External Memory 32 bit 16 bit 8 bit Bit Num CPU Regi...

Page 245: ...7 0 xxxa CPU Address WA HA BA Bit Num CPU Data Bus 31 0 abcd 31 0 abab 31 0 aaaa External Address EA EA 1 EA 2 EA 3 EA EA 1 EA Bit Num External Data 7 0 a 7 0 b 7 0 c 7 0 d 7 0 a 7 0 b 7 0 a Timing Sequence 1st 2nd 3rd 4th 1st 2nd Table 5 8 External 8 bit Datawidth Load Operation with Big Endian Transfer Width LOAD CPU Reg External Memory 32 bit 16 bit 8 bit Bit Num CPU Register Data 31 0 abcd 15 ...

Page 246: ... 0 xxxa CPU Address WA HA HA 1 BA BA 1 BA 2 BA 3 Bit Num CPU Data Bus 31 0 abcd 31 0 cdcd 31 0 abab 31 0 dddd 31 0 cccc 31 0 bbbb 31 0 aaaa External Address ADDR EA Bit Num External Data 31 0 abcd 31 0 xxcd 31 0 abxx 31 0 xxxd 31 0 xxcx 31 0 xbxx 31 0 axxx Timing Sequence Table 5 10 External 32 bit Datawidth Load Operation with Little Endian Transfer Width LOAD CPU Reg External Memory 32 bit 16 bi...

Page 247: ...r Data 31 0 abcd 31 0 xxab 31 0 xxxb 31 0 xxxa CPU Address WA HA BA BA 1 Bit Num CPU Data Bus 31 0 abcd 31 0 abab 31 0 bbbb 31 0 aaaa External Address ADDR EA 1 EA EA EA Bit Num External Data 15 0 ab 15 0 cd 15 0 ab 15 0 xb 15 0 ax Timing Sequence 1st 2nd Table 5 12 External 16 bit Datawidth Load Operation with Little Endian Transfer Width LOAD CPU Reg External Memory 32 bit 16 bit 8 bit Bit Num C...

Page 248: ...0 xxxa CPU Address WA HA BA Bit Num CPU Data Bus 31 0 abcd 31 0 abab 31 0 aaaa External Address ADDR EA 3 EA 2 EA 1 EA EA 1 EA EA Bit Num External Data 7 0 a 7 0 b 7 0 c 7 0 d 7 0 a 7 0 b 7 0 a Timing Sequence 1st 2nd 3rd 4th 1st 2nd Table 5 14 External 8 bit Datawidth Load Operation with Little Endian Transfer Width LOAD CPU Reg External Memory 32 bit 16 bit 8 bit Bit Num CPU Register Data 31 0 a...

Page 249: ...data bus Ext I O bank controller has three kind of the register for eight banks and then it can be controlled by various timing control options 5 6 1 FEATURES The following is a list of the Ext I O Bank Controller s features 8 banks ROM SRAM Flash Memory External I O interface 16M byte maximum address range per bank 24 bit external address pins 32 bit internal and external data bus Various timing ...

Page 250: ...TERNAL DEVICE CONNECTION Figure 5 3 illustrates a simple connection between 8 bit ROM Flash and S3C2500B ADDR DATA nOE nCS nWE 8 bit ROM Flash nOE nRCS 0 ADDR 23 0 DATA 7 0 nWBE 0 S3C2500B Figure 5 3 8 bit ROM SRAM and Flash Basic Connection ...

Page 251: ...it ROM Flash and S3C2500B for the consisting of 16 bit ROM SRAM Flash nOE nRCS 0 nWBE 0 nWBE 1 ADDR 23 0 DATA 7 0 DATA 15 8 ADDR 23 0 DATA 7 0 nOE nCS nWE 8 bit ROM Flash ADDR 23 0 DATA 7 0 nOE nCS nWE 8 bit ROM Flash S3C2500B Figure 5 4 8 bit ROM SRAM and Flash Basic Connection 8 bit Memory x 2 ...

Page 252: ...6 Figure 5 5 illustrates a connection between 16 bit ROM SRAM and S3C2500B ADDR DATA nOE nCS Upper byte Lower byte 16 bit SRAM nWE nOE nRCS nBE 0 ADDR 23 0 DATA 15 0 nBE 1 nSDWE nWE16 S3C2500B Figure 5 5 16 bit SRAM Basic Connection ...

Page 253: ...OLLER 5 17 Figure 5 6 illustrates a connection between 16 bit ROM Flash and S3C2500B ADDR DATA nOE nWE 16 bit ROM Flash nCS nOE nSDWE nWE16 ADDR 23 0 DATA 15 0 nRCS S3C2500B Figure 5 6 16 bit ROM and Flash Basic Connection ...

Page 254: ... 5 7 illustrates a connection between 16 bit ROM and S3C2500B nOE nRCS ADDR 23 0 DATA 31 0 DATA 15 0 DATA 31 16 S3C2500B ADDR DATA nOE nCS nWE 16 bit ROM ADDR DATA nOE nCS nWE 16 bit ROM nSDWE nWE16 Figure 5 7 16 bit ROM Basic Connection 2 ...

Page 255: ...on between 16 bit SRAM and S3C2500B nOE nRCS ADDR 23 0 DATA 31 0 nWBE 1 DATA 15 0 DATA 31 16 nWBE 0 ADDR DATA nOE nCS Upper byte 16 bit ROM Lower byte ADDR DATA nOE nCS Upper byte 16 bit ROM Lower byte nWBE 3 nWBE 2 S3C2500B Figure 5 8 16 bit SRAM Basic Connection 2 ...

Page 256: ... nRCS ADDR 23 ALE DATA 7 0 nWBE nREADY Figure 5 9 ROM SRAM with Muxed Address Data Bus Connection NOTE If the external I O use nReady signal insteady of nWait you must select nReady in WAITCON register of memory controller ADDR 23 bit is used the address latch enable ALE signal to latch an address for the ROM and SRAM which have the muxed bus structure ...

Page 257: ...ndard system configuration The special registers are also used to control access to all banks Table 5 15 Ext I O Bank Controller Special Registers Name Address Description Reset Value B0CON 0xF0010000 Bank 0 control register 0xC514E488 B0SIZE 3 0x8514E488 B0SIZE 2 0x4514E488 B0SIZE 1 B1CON 0xF0010004 Bank 1 control register 0xC514E488 B2CON 0xF0010008 Bank 2 control register 0xC514E488 B3CON 0xF00...

Page 258: ... the nOE assertion to be delayed Thus the external memory may use more stable address Access cycles TACC extend nCS cycles to access external memory After nOE is deasserted chip selection hold time TCOH can be used when nCS is keep up B0CON is used to set the external access timings for external I O bank 0 B1CON is used to set the external access timing for I O bank 1 and so on BnCON Bank number F...

Page 259: ...514E488 B0SIZE 1 B1CON 0xF0010004 R W Bank 1 control register 0xC514E488 B2CON 0xF0010008 R W Bank 2 control register 0xC514E488 B3CON 0xF001000C R W Bank 3 control register 0xC514E488 B4CON 0xF0010010 R W Bank 4 control register 0xC514E488 B5CON 0xF0010014 R W Bank 5 control register 0xC514E488 B6CON 0xF0010018 R W Bank 6 control register 0xC514E488 B7CON 0xF001001C R W Bank 7 control register 0x...

Page 260: ...s 1100 12 cycles 1101 13 cycles 1110 14 cycles 1111 15 cycles 20 16 Access cycles nOE low time TACC 00000 reserved 00001 reserved 00010 reserved 00011 3 cycles 00100 4 cycles 00101 5 cycles 00110 6 cycles 00111 7 cycles 01000 8 cycles 01001 9 cycles 01010 10 cycles 01011 11 cycles 01100 12 cycles 01101 13 cycles 01110 14 cycles 01111 15 cycles 10000 16 cycles 10001 17 cycles 10010 18 cycles 10011 ...

Page 261: ...h as nCS nWBE nOE nEWAIT for 8 bit memory and nCS nWE16 nOE nEWAIT for 16 bit memory 3 The DW of bank 0 is the same with B0SIZE 1 0 pin That is read only value The initial value of other banks is 11 5 6 3 2 Muxed bus control register Ext I O Bank controller supports memory devices which have the muxed bus interface To use muxed bus memory device muxed bus enable MBE and muxed bus address cycle TMA...

Page 262: ...000 8 cycles 20 18 Muxed bus address cycle for bank 6 TMA6 001 1 cycle 010 2 cycles 011 3 cycles 100 4 cycles 101 5 cycles 110 6 cycles 111 7 cycles 000 8 cycles 23 21 Muxed bus address cycle for bank 7 TMA7 001 1 cycle 010 2 cycles 011 3 cycles 100 4 cycles 101 5 cycles 110 6 cycles 111 7 cycles 000 8 cycles 24 Address Data muxed bus enable for bank 0 MBE0 0 disable 1 enable 25 Address Data muxed...

Page 263: ...e bank except first access cycle So TCOHDIS helps you to access slow External I O devices more quickly Performance by using COHDIS in the WAITCON register when slow External I O is used could be improved If you use slow External I O you must set TCOH to a proper value because you have to prevent the data collision But when you set TCOH to a non zero value all types of data access in the selected b...

Page 264: ...EN2 9 External wait enable for bank 1 EWAITEN1 8 External wait enable for bank 0 EWAITEN0 7 nWait nReady select for bank 7 NREADY7 0 nWait 1 nReady 6 nWait nReady select for bank 6 NREADY6 5 nWait nReady select for bank 5 NREADY5 4 nWait nReady select for bank 4 NREADY4 3 nWait nReady select for bank 3 NREADY3 2 nWait nReady select for bank 2 NREADY2 1 nWait nReady select for bank 1 NREADY1 0 nWai...

Page 265: ...29 5 6 4 TIMING DIAGRAM nRCS nOE ADDR DATA Addr HCLKO D ata Fetch tACC Data tRCSd tnOEd tADDRd tDATAd TACC 0x8 8 cycles TCOS 0x0 0 cycle TCOH 0x0 0 cycle TACS 0x0 0 cycle tRCSh tnOEh tADDRh tDATAh Figure 5 14 Read Timing Diagram 1 ...

Page 266: ...R S3C2500B 5 30 nRCS nSDWE ADDR DATA Addr HCLKO tACC Data TACC 0x8 8 cycles TCOS 0x0 0 cycle TCOH 0x0 0 cycle TACS 0x0 0 cycle tADDRd tRCSh tnSDWEh tADDRh tDATAh tRCSd tnSDWEd tDATAd Figure 5 15 Write Timing Diagram 1 ...

Page 267: ...R 5 31 nRCS nOE ADDR DATA Addr HCLKO Data Fetch tACC Data tCOH tACS tCOS TACC 0x5 5 cycles TCOS 0x1 1 cycle TCOH 0x1 1 cycle TACS 0x1 1 cycle tRCSd tnOEd tADDRd tDATAd tRCSh tnOEh tADDRh tDATAh Figure 5 16 Read Timing Diagram 2 ...

Page 268: ...00B 5 32 nRCS nSDWE ADDR DATA HCLKO tACC Data tCOH tACS tCOS TACC 0x5 5 cycles TCOS 0x1 1 cycle TCOH 0x1 1 cycle TACS 0x1 1 cycle tADDRd tRCSh tnSDWEh tADDRh tDATAh tRCSd tnSDWEd tDATAd Addr Figure 5 17 Write Timing Diagram 2 ...

Page 269: ...cycles TCOS 1 1 cycle TCOH 2 2 cycle TACS 1 1 cycle COHDIS 1 Enable Addr1 at Bank n tACC Data 1 tCOH tACS tCOS Addr2 at Bank n tACC Data 2 tACS tCOS nSDWE tCOH 1st access cycle at Bank n 2nd access cycle at Bank n Figure 5 18 Read after Write at the Same Bank COHDIS 1 ...

Page 270: ...ALE DATA HCLKO Data Fetch tACC Data tCOH tMA tCOS TACC 0x4 4 cycles TCOS 0x1 1 cycle TCOH 0x1 1 cycle TMA 0x2 2 cycles MBE 1 Enable Addr tDATAd tRCSd tRCSh tnOEh tnOEd tDATAh tADDRh tALEh tALEd tADDRd Figure 5 19 Read Timing Diagram Muxed Bus ...

Page 271: ...LE DATA HCLKO Data Fetch tACC Data tCOH tMA tCOS TACC 0x4 4 cycles TCOS 0x1 1 cycle TCOH 0x1 1 cycle TMA 0x2 2 cycles MBE 1 Enable Addr tDATAd tGCSd tGCSh tnSDWEh tnSDWEd tDATAh tADDRh tALEh tALEd tADDRd Figure 5 20 Write Timing Diagram Muxed Bus ...

Page 272: ... DATA Addr HCLKO tACC tACS tCOS TACC 0x5 5 cycles TCOS 0x1 1 cycle TCOH 0x0 0 cycle TACS 0x1 1 cycle EWAITEN 1 Enable nEWAIT nReady tnSDWEd tADDRd tADDRh tnSDWEh tDATAh tRCSh tRCSd tDATAd Data tnWAITd tnWAITh Figure 5 21 Write Timing Diagram nEWAIT ...

Page 273: ...LKO tACC tACS tCOS TACC 0x5 5 cycles TCOS 0x1 1 cycle TCOH 0x0 0 cycle TACS 0x1 1 cycle EWAITEN 1 Enable NREADY 1 nReady nEWAIT nReady tDATAd tRCSd tnSDWEd tADDRd tDATAh tADDRh tnSDWEh tRCSh Data tnWAITd tnWAITh Addr Figure 5 22 Write Timing Diagram nREADY ...

Page 274: ...formance Supports for 16M bit 64M bit 128M bit and 256M bit SDRAM devices with two or four leaves Allows a direct interface to up to two banks of SDRAM Each bank supports 16 or 32 bits wide and up to 128M byte in size Support byte half word and word transaction CAS latency can be 1 2 or 3 Provides auto refresh and self refresh mode to sustain the contents of SDRAM memory ...

Page 275: ... bus width is 32 bits Table 5 20 Illustrates the supported SDRAM configurations when external bus width is 16 bits If 16M bit device which has two leaves is used only ADDR 13 is used to select a leaf If SDRAM device which has four leaves is used both ADDR 14 and ADDR 13 are used to select a leaf Only the chip select signals nSDCS 1 0 are to select a bank The other SDRAM control signals are common ...

Page 276: ...DR 21 32 M 2 64 M 4M 16 1 12 8 HADDR 22 HADDR 21 16 M 2 32 M 2M 32 1 11 8 HADDR 22 HADDR 21 8 M 2 16 M 128M bit 16M 8 1 12 10 HADDR 22 HADDR 21 64 M 2 128 M 8M 16 1 12 9 HADDR 22 HADDR 21 32 M 2 64 M 4M 32 1 12 8 HADDR 22 HADDR 21 16 M 2 32 M 256M bit 32M 8 1 13 10 HADDR 22 HADDR 21 128 M 2 256 M 16M 16 1 13 9 HADDR 22 HADDR 21 64 M 2 128 M 8M 32 1 13 8 HADDR 22 HADDR 21 32 M 2 64 M NOTE Banks Num...

Page 277: ...M 1M 16 1 11 8 HADDR 20 2 M 2 4 M 64M bit 8M 8 1 12 9 HADDR 21 HADDR 20 16 M 2 32 M 4M 16 1 12 8 HADDR 21 HADDR 20 8 M 2 16 M 128M bit 16M 8 1 12 10 HADDR 21 HADDR 20 32 M 2 64 M 8M 16 1 12 9 HADDR 21 HADDR 20 16 M 2 32 M 256M bit 32M 8 1 13 10 HADDR 21 HADDR 20 64 M 2 128 M 16M 16 1 13 9 HADDR 21 HADDR 20 32 M 2 64 M NOTE Banks Number of external SDRAM memory bank used The controller supports up ...

Page 278: ...128M bit 16M 8 22 21 25 24 9 8 7 6 5 4 3 2 8M 16 22 21 24 9 8 7 6 5 4 3 2 4M 32 22 21 9 8 7 6 5 4 3 2 256M bit 32M 8 22 21 26 25 9 8 7 6 5 4 3 2 16M 16 22 21 25 9 8 7 6 5 4 3 2 8M 32 22 21 9 8 7 6 5 4 3 2 SDRAM Row Address AddrOut 14 0 Technology 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16M bit 2M 8 21 20 19 18 17 16 15 14 13 12 11 10 1M 16 21 20 19 18 17 16 15 14 13 12 11 10 64M bit 8M 8 22 21 23 20 19...

Page 279: ...0 Technology 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 16M bit 2M 8 20 19 18 17 16 15 14 13 12 11 10 9 1M 16 20 19 18 17 16 15 14 13 12 11 10 9 64M bit 8M 8 21 20 22 19 18 17 16 15 14 13 12 11 10 9 4M 16 21 20 22 19 18 17 16 15 14 13 12 11 10 9 128M bit 16M 8 21 20 22 19 18 17 16 15 14 13 12 11 10 9 8M 16 21 20 22 19 18 17 16 15 14 13 12 11 10 9 256M bit 32M 8 21 20 23 22 19 18 17 16 15 14 13 12 11 10 9 ...

Page 280: ...L OP code MRS Refresh Auto refresh H L L L H X REF Self refresh L L L L H SREF Row activate H L L H H V X ACT Read with auto precharge H L H L H V H RDA without auto precharge L RD Write with auto precharge H L H L L V H WRA without auto precharge L WR Burst stop H L H H L X BST Precharge Bank selection H L L H L V L PRE All banks X H PALL Active power down L H X X X X APWDN Precharge power down L...

Page 281: ...s completed before the requested data is read from memory to maintain data consistency between the write buffer and SDRAM memory 5 7 7 SELF REFRESH The SDRAM controller provides the auto refresh REF and self refresh SREF command to sustain the contents of the SDRAM The auto refresh is issued to SDRAM periodically when refresh timer is expired The self refresh is entered and exited by request of on...

Page 282: ... 0 of the CMDREG to 01 This automatically issues a PALL command to the SDRAM 3 Write 0xF into the refresh timer register This provides a refresh cycle every 15 clock cycles 4 Wait for a time period equivalent to 120 clock cycles 8 refresh cycles 5 Program the normal operational value into the refresh timer 6 Program the CFGREG to their normal operation values 7 Program the INIT 1 0 to 10 This auto...

Page 283: ...nd register 0x00000000 REFREG 0xF0020008 Refresh timer register 0x00000020 WBTOREG 0xF002000C Write buffer time out register 0x00000000 5 3 9 1 Configuration Register The configuration register is 32 bit read write some bits are read only register This register contains SDRAM control parameters such as external bus width memory type and various timing parameters Table 5 25 SDRAM Configuration Regi...

Page 284: ...s 01 64M bit SDRAM memory devices 10 128M bit SDRAM memory devices 11 256M bit SDRAM memory devices R W 00 RP 9 8 Row Pre charge time 00 RP 1 cycle 01 RP 2 cycles 10 RP 3 cycles 11 RP 4 cycles R W 11 RCD 11 10 RAS to CAS delay 00 RCD 1 cycle 01 RCD 2 cycles 10 RCD 3 cycles 11 RCD 4 cycles R W 11 RC 15 12 Row Cycle 0000 RC 1 cycles 0001 RC 2 cycles 1110 RC 15 cycles 1111 RC 16 cycles R W 1001 RAS 1...

Page 285: ...mory devices 9 8 Row Pre charge time RP 00 1 cycle 01 2 cycles 10 3 cycles 11 4 cycles 11 10 RAS to CAS delay RCD 00 1 cycle 01 2 cycles 10 3 cycles 11 4 cycles 15 12 Row Cycle RC 0000 1 cycle 0001 2 cycles 0010 3 cycles 0011 4 cycles 0100 5 cycles 0101 6 cycles 0110 7 cycles 0111 8 cycles 1000 9 cycles 1001 10 cycles 1010 11 cycle 1011 12 cycles 1100 13cycles 1101 14 cycles 1110 15 cycles 1111 16...

Page 286: ...t value INIT 1 0 Control bits for SDRAM device initialization 00 Normal operation 01 Automatically issue a PALL to the SDRAM 10 Automatically issue a MRS to the SDRAM 11 reserved R W 00 WBUF 2 Write buffer enable 0 Disable merging write buffer 1 Enable merging write buffer NOTE Disabling the write buffer will flush any stored value s to the external SDRAM memory R W 0 BUSY 3 SDRAM controller statu...

Page 287: ...L to the SDRAM 10 Automatically issue a MRS to the SDRAM 11 reserved 2 Write buffer enable 0 Disable merging write buffer 1 Enable merging write buffer 3 SDRAM controller status bit 0 SDRAM controller is idle 1 SDRAM controller is busy 31 4 Reserved 31 0 3 4 1 2 RESERVED W B U F I N I T B U S Y Figure 5 24 SDRAM Command Register ...

Page 288: ...and a system bus clock frequency of 133MHz 15 6 x 10 6 x 133 x 10 6 2075 For refresh period of 7 8us in 256Mbit and a system bus clock frequency of 133MHz 7 8 x 10 6 x 133 x 10 6 1037 The refresh timer is set to 32 on reset To ensure a refresh interval of less than 15 6us in 16 64 and 128Mbit after reset The minimum frequency of system bus clock allowed is 32 15 6 x 10 6 2 1MHz The refresh timer i...

Page 289: ...00000000 WBTOREG Bit Description R W Default value WBTO 15 0 Write buffer time out delay time R W 0x00000000 31 16 Reserved A write to a merging write buffer loads the value in the timeout register into the time out down counter of the buffer When the time out counter reaches 0 the merging write buffer contents is written flushed to the external memory The down counter is clocked by system bus clo...

Page 290: ...IMING Read ADDR DATA HCLKO nSDCAS nSDWE CKE nSDRAS nSDCS DQM nWBE Row Active Row Addr tCC tCL tCH tCSd tCSh tRASd tRASh tADDRd tCASd tCASh tADDRh tRDd tRDh tDQMd tDQMh tRCD Col Addr Data DQM Latency CAS Latency Figure 5 27 Single Read Operation CAS Latency 2 ...

Page 291: ... DATA HCLKO nSDCAS nSDWE CKE nSDRAS nSDCS DQM nWBE Row Active Row Addr tCC tCL tCH tCSd tCSh tRASd tRASh tADDRd tCASd tCASh tADDRh tRDd tRDh tDQMd tDQMh tRCD Col Addr Data DQM Latency CAS Latency Figure 5 28 Single Read Operation CAS Latency 3 ...

Page 292: ... 56 Write ADDR DATA HCLKO nSDCAS nSDWE nSDRAS nSDCS Data Row Active Row Addr tCC tCL tCSd tCSh tRASd tRASh tADDRd tCASd tCASh tADDRh tWDd tWDh tDQMd tDQMh tRCD tWEd tWEh DQM nWBE Col Addr CKE tCH Figure 5 29 Single Write Operation ...

Page 293: ...a Data Data Write ADDR DATA HCLKO nSDCAS nSDWE CKE nSDRAS nSDCS Row Active Row Addr tRCD tCC tCL tCH tCSd tCSh tRASd tRASh tADDRd tCASd tCASh tADDRh tRDh tDQMd tDQMh CAS Latency DQM Latency tRDd DQM nWBE Figure 5 30 Burst Read Operation CAS Latency 2 ...

Page 294: ...a Data Data Write ADDR DATA HCLKO nSDCAS nSDWE CKE nSDRAS nSDCS Row Active Row Addr tRCD tCC tCL tCH tCSd tCSh tRASd tRASh tADDRd tCASd tCASh tADDRh tRDh tDQMd tDQMh CAS Latency DQM Latency tRDd DQM nWBE Figure 5 31 Burst Read Operation CAS Latency 3 ...

Page 295: ... Addr Data Data Write ADDR DATA HCLKO nSDCAS nSDWE CKE nSDRAS nSDCS DQM nWBE Row Active Row Addr tRCD tCC tCL tCH tCSd tCSh tRASd tRASh tADDRd tCASd tCASh tADDRh tWDh tDQMd tDQMh tWDd Data Data tWEd tWEh Figure 5 32 Burst Write Operation ...

Page 296: ...MEMORY CONTROLLER S3C2500B 5 60 NOTES ...

Page 297: ...s limited only by the maximum bus capacitance of 400 pF 6 2 FEATURES Supports only single master mode Supports 8 bit bi directional serial data transfers Supports 7 bit addressing Figure 6 1 shows a block diagram of the S3C2500B I 2 C controller Data Control Serial Clock Line Control Serial Clock Prescaler Control status register IICCON RESET BUSY COND1 COND0 ACK LRB IEN Prescaler register IICPS S...

Page 298: ...ter of the serial I2 C Using a prescaler register the user can program the serial clock frequency that is supplied to the I2 C controller The serial clock frequency is calculated as follows Serial clock frequency fSYSCLK 16 prescaler register value 1 3 where fSYSCLK is the system clock frequency ...

Page 299: ... transfers proceed as follows Case 1 A master IC wants to send data to another IC slave 1 Master addresses slave 2 Master sends data to the slave master is transmitter slave is receiver 3 Master terminates the data transfer Start Condition Address P 9 Stop Condition SDA by Receiver SCL from Master 8 9 8 R W ACK ACK S SDA by Transmitter MSB Acknowledge from receiver Acknowledge from receiver 2 1 MS...

Page 300: ...6 4 2 GENERAL CHARACTERISTICS Both SDA and SCL are bi directional lines which are connected to a positive supply voltage through a pull up resistor When the I 2 C is free the SDA and SCL lines are both high level The output stages of I 2 C interfaces connected to the bus have an open drain or open collector to perform the wired AND function Data on the I 2 C can be transferred at a rate up to 100K...

Page 301: ... generated by the master The bus is considered to be busy after the start condition is generated The bus is considered to be free again when a brief time interval has elapsed following the stop condition Start condition a High to Low transition of the SDA line while SCL is high Stop condition a Low to High transition of the SDA line while SCL is high Start Condition Address P 9 Stop Condition SDA ...

Page 302: ...clock pulse The receiver must pull down the SDA line during the acknowledge pulse so that it remains stable low during the high period of this clock pulse Usually a receiver which has been addressed is obliged to generate an acknowledge after each byte is received When a slave receiver does not acknowledge from the slave address the slave must leave the data line high The master can then generate ...

Page 303: ...erate another start condition and address another slaves without first generating a stop condition This feature supports the use of various combinations of read write formats for data transfers S Slave address A Data 1 8 bits A Data 2 Data M A P S Slave address A Data 1 8 bits A Data 2 Data M A A P Multiple byte master receiver format Multiple byte master transmitter format NOTE S Start W Write bi...

Page 304: ...h an acknowledge However ICs can also be made to ignore this address The second byte of the general call address then defines the action to be taken 6 4 6 5 Definition of Bits in the First Data Byte The first seven bits of the first data byte make up the slave address The eighth bit is the LSB or direction bit which determines the direction R W of the message When an address is sent each IC on the...

Page 305: ...ead only It holds the value of the last received bit over the I 2 C Normally this bit will be the value of the slave acknowledgement To check for slave acknowledgement you test the LRB 3 Acknowledge enable ACK The ACK bit is normally set to 1 This causes the I 2 C controller to send an acknowledge automatically after each byte This bit must be 0 when the I 2 C controller is operating in receiver m...

Page 306: ...h ACK not received 3 Acknow enable ACK Controls generation of an ACK signal in receive mode 0 Do not generate an ACK at 9th SCL No more received data is required from the slave 1 Generate an ACK signal at 9th SCL 5 4 COND 1 and COND 0 Generate a control such as start or stop 00 No effect 01 Generate start condition BF bit should be set simultaneously 10 Generate stop condition 11 SCL will be relea...

Page 307: ...e shift register and read form the data buffer I2C data is always shifted in or out of the shift register 31 8 Reserved Not applicable 6 5 3 PRESCALER REGISTER IICPS The prescaler register for the I2C is described in Table 6 6 Table 6 5 IICPS Register Register Address R W Description Rest Value IICPS 0xF00F0008 R W Prescaler register 0x00000000 Table 6 6 IICPS Register Description Bit Number Bit N...

Page 308: ...escaler counter It is read in test mode only to check the counter s current value 31 16 Reserved Not applicable 6 5 5 INTERRUPT PENDING REGISTER IICPND The I2C interrupt pending register for the I2C is described in Table 6 10 Table 6 9 IICPND Register Register Address R W Description Rest Value IICPND 0xF00F0010 R W Interrupt pending register 0x00000000 Table 6 10 IICPND Register Description Bit N...

Page 309: ...R 6 13 IICBUF IIC Slave Address 0 x 0 No Yes IIC Setup Reset IICPS Setup IICCON Start BF IICBUF IIC Upper Address IICBUF IIC Lower Address IICCON Stop All Data Sent IICBUF One Byte Data Figure 6 7 Write Operation Flow Chart ...

Page 310: ...p Reset IICPS Setup IICCON Start BF IICBUF IIC Upper Address IICBUF IIC Lower Address IICCON Repeated Start ACK IICCON Start ACK Empty the BF Bit IICCON Stop Send No ACK All Data Received IICBUF One Byte Data IICBUF IIC Slave Address 0 x 1 Figure 6 8 Read Operation Flow Chart ...

Page 311: ...ck a content addressable memory CAM for storing network addresses a number of commands status and error counter registers The MII supplies the transmission and reception clocks of 25MHz for 100M bps operation 2 5 MHz for the 10M bps speed or 1MHz for the 1M bps for Home PNA The MII conforms to the ISO IEC 802 3 standards B D I M I I 10 M b p s 7 W i r e MAC TxFIFO 80x9 MAC Preamble SFD CRC PAD JAM...

Page 312: ...gnment logic Old and new physical media support compatible with existing 10M bps networks 100M bps or 10M bps operation to allow price performance options and to support phased conversions Full IEEE 802 3 compatibility for existing applications Media Independent interface MII or 7 wire interface Station management STA signaling for external physical layer configuration and link negotiation On chip...

Page 313: ...also supports generation of pause frame and provides timers and counters for pause control MAC control command and status registers Controls programmable options including the enabling or disabling of signals that notify the system when conditions occur The status registers hold information for error handling software and the error counters accumulate statistical information for network management...

Page 314: ...If no collision occurs and transmission is underway the additional 16 bytes handle system latency and avoid FIFO under run When the system interface has set the MACTXCON 0 bit the transmission state machine requests data from the BDI The system controller then fetches data from the system memory The data is stored in the MTxFIFO until the threshold for transmit data is satisfied When the MTxFIFO i...

Page 315: ...mes and then retransmits the data After 16 attempts the transmission state machine sets an error bit and generates an interrupt if enabled to signify the failure to transmit a frame due to excessive collisions It flushes the MTxFIFO and the MAC is ready for the next frame 7 3 4 7 Transmit Data Parity Checker Data in the FIFO is even parity When data is read for transmission the transmission state ...

Page 316: ... CAM1 and length type op code and operand to the CAM18 entry You must write the MAC transmit control register to set the send pause control bit In addition CAM19 and CAM20 can be used to construct a user define control frame 7 3 5 3 Parallel CRC Checker The receiver block computes a CRC across the data and the transmitted CRC and then checks that the resulting syndrome is valid A parallel CRC chec...

Page 317: ...he BDMA engine controls the data feeding and reception between the MAC and the system bus AMBA using two buffers BDMA TxBUFF BTxBUFF and BDMA RxBUFF BRxBUFF The BTxBUFF and BRxBUFF hold data and status information for frames being transmitted and received respectively Each buffer is controlled by the block which consists of a bus arbiter a control and status block buffer descriptors 7 3 7 1 Bus Ar...

Page 318: ...ns The beginning of a frame should be placed on word boundary Misalignment of the BDMA transfer would complicate the design of the DMA and degrade the performance To avoid this you can use an alignment widget between the BDMA Buffer word and the MAC FIFO byte by controlling the widget field in Tx buffer descriptor The widget discards the first n bytes up to three where n is the value read from the...

Page 319: ...DMARXDPTR is not updated to the next pointer It always has the first buffer descriptor address Because BDMA pointers are fixed as initial addresses BDMA count register values indicate the number of frames to be handled by BDMA In addition users can determine how many buffer descriptors to use by controlling the BDMATXCON 3 0 BTxNBD and BDMARXCON 3 0 BRxNBD If the last buffer descriptor was used by...

Page 320: ...send 24 Comp The transmition is finished 23 ParErr MTxFIFO Parity Error 22 LateColl The Collision occured after 64 byte times 21 NoCarr No Carrier sense is detected when MAC Tx transmits a frame 20 DeferErr MAC doesn t run the transmission process until 6071 nibble or 24284 bit times The current frame is aborted 19 Underflow MTxFIFO underflow 18 ExColl The excessive collision is occured 16 times c...

Page 321: ...s set or when MACRXCON 0 MRxEn is clear 24 MRx10Stat The frame was received over 10Mbps wire 7 interface 23 BRxDone The reception process by the BDMA is done without error 22 RxParErr MRxFIFO Parity Error 21 MUFS Set when the size of the Rx frame is larger than the Maximum Untagged Frame Size 1518bytes if the long packet is not enabled in the MAC Rx control register 20 Overflow MRxFIFO Overflow 19...

Page 322: ...er than 1518 byte the BRxBS should be at least 4 bytes larger than the BRxMFS or less than 1518 byte for the reception with a single or multiple buffer descriptors respectively BRxBS of BDMARXLEN not used BRxBS of BDMARXLEN BRxBS of BDMARXLEN Memory for Rx bufer descriptor not used not used BRXBDCNT N 1 BRXBDCNT 1 buffer pointer 1 status length buffer pointer 2 status length buffer pointer N statu...

Page 323: ...XINTENA 0xF00A001C R W BDMA MAC Rx Interrupt enable register 0x00000000 BMTXSTATA 0xF00A0020 R W BDMA MAC Tx Status register 0x00000000 BMRXSTATA 0xF00A0024 R W BDMA MAC Rx Status register 0x00000000 BDMARXLENA 0xF00A0028 R W Receive Frame Size 0x00000000 CFTXSTATA 0xF00A0030 R Transmit control frame status 0x00000000 MACCONA 0xF00B0000 R W MAC control 0x00000000 CAMCONA 0xF00B0004 R W CAM control...

Page 324: ...0xF00C0020 R W BDMA MAC Tx Status register 0x00000000 BMRXSTATB 0xF00C0024 R W BDMA MAC Rx Status register 0x00000000 BDMARXLENB 0xF00C0028 R W Receive Frame Size 0x00000000 CFTXSTATB 0xF00C0030 R Transmit control frame status 0x00000000 MACCONB 0xF00D0000 R W MAC control 0x00000000 CAMCONB 0xF00D0004 R W CAM control 0x00000000 MACTXCONB 0xF00D0008 R W Transmit control 0x00000000 MACTXSTATB 0xF00D...

Page 325: ... 1 8 of the BDMA Tx Buffer 010 means wait to fill 2 8 of the buffer and so on through 100 which means wait to fill 4 8 of the BDMA Tx Buffer NOTE If the last data of the frame arrives in BDMA Tx Buffer the data transfer from the BDMA Tx Buffer to the MAC TxFIFO starts immediately regardless of the level of these bits 7 Tx Byte Swapping BTxBSWAP Use to prevent disorder of byte sequence when memory ...

Page 326: ...nvalid bytes are inserted when the word is assembled by the BDMA 00 No invalid bytes 01 1 invalid byte 10 2 invalid bytes and 11 3 invalid bytes 6 Reserved Not applicable 7 Rx Byte Swapping BRxBSWAP Use to prevent disorder of byte sequence when memory operate on big endian format and byte unit access If this bit is set the reception byte is swapped B3 B2 B1 B0 B0 B1 B2 B3 8 Reserved Not applicable...

Page 327: ...t buffer descriptor start address register contains the address of the first buffer descriptor on the frame to be sent 7 4 1 4 BDMA Receive Buffer Descriptor Start Address Register Table 7 10 BDMARXDPTR Register Registers Address R W Description Reset Value BDMARXDPTRA 0xF00A000C R W BDMA Rx buffer descriptor base register 0x00000000 BDMARXDPTRB 0xF00C000C R W BDMA Rx buffer descriptor base regist...

Page 328: ...ter value is dependent on the BTxNBD of the BDMATXCON register Buffer descriptor current address BDMATXDPTR BTXBDCNT 3 7 4 1 6 BDMA Receive Buffer Descriptor Counter Table 7 14 BRXBDCNT Register Registers Address R W Description Reset Value BRXBDCNTA 0xF00A0014 R W BDMA Rx buffer descriptor counter of current pointer 0x00000000 BRXBDCNTB 0xF00C0014 R W BDMA Rx buffer descriptor counter of current ...

Page 329: ...nables Underflow interrupt 2 Enable MAC Tx deferral DeferErrIE This bit enables DeferErr interrupt 3 Enable MAC Tx no carrier NoCarrIE This bit enables NoCarr interrupt 4 Enable MAC Tx late collision LateCollIE This bit enables LateColl interrupt 5 Enable MAC Tx transmit parity TxParErrIE This bit enables TxParErr interrupt 6 Enable MAC Tx completion TxCompIE This bit enables TxComp interrupt 15 7...

Page 330: ... during the frame transmission 2 Deferral Error DeferErr This bit is set when MAC doesn t run the transmission process from TX_EN falling to 6 071 nibble times or 24 284 bit times 3 No carrier NoCarr This bit is set if no carrier sense is detected during the transmission frame 4 Late collision LateColl This bit is set if a collision occurs after 512 bit times or 64 byte times 5 Transmit parity err...

Page 331: ...IE This bit enables CRCErr interrupt 3 Enable MAC Rx overflow OverflowIE This bit enables Overflow interrupt 4 Enable MAC Rx long error LongErrIE This bit enables LongErr interrupt 5 Enable MAC Rx receive parity RxParErrIE This bit enables RxParErr interrupt 6 Factorial test bit 15 7 Reserved Not applicable 16 Enable BDMA Rx done for every received frames BRxDoneIE This bit enables BRxDone interru...

Page 332: ...yte 4 Long error LongErr This bit is set if the MAC received a frame longer than 1518 bytes It is not set if the long enable bit in the receive control register MACRXCON is set 5 Parity error RxParErr This bit is set if a parity error is detected in the MAC RxFIFO 6 Factorial test bit 15 7 Reserved Not applicable 16 BDMA Rx done in every received frames BRxDone This bit is set each time the BDMA r...

Page 333: ...ncoming frame larger than the BRxBS multiple buffer descriptors are used for the frame reception NOTE BRxBS value has to keep multiples of 16 in byte unit For long packet reception larger than 1518 bytes the BRxBS should be at least 4 bytes larger than the BRxMFS or less than 1518 bytes for the reception with a single or multiple buffer descriptor respectively 15 12 Reserved Not applicable 27 16 B...

Page 334: ...ngine to read this register and to generate an interrupt to notify the system that the transmission of a MAC control packet has been completed Table 7 26 CFTXSTAT Register Registers Address R W Description Reset Value CFTXSTATA 0xF00A0030 R Transmit control frame status 0x00000000 CFTXSTATB 0xF00C0030 R Transmit control frame status 0x00000000 Table 7 27 Transmit Control Frame Register Description...

Page 335: ... any current frames has been completed 1 Halt immediate MHaltImm Set this bit to immediately stop all transmission and reception 2 Software reset MReset Set this bit to reset all MAC control and status register and MAC state machines This bit is automatically cleared 3 Full duplex If the PHY chip advertising full duplex set this bit In this case collision does not detected 4 MAC loopback MLoopBack...

Page 336: ... the frames with the matched destination addresses Negative CAM comparison mode MCompEn 1 MNegCAM 1 The address comparison is same as the CAM comparison mode But the CAM controller rejects the frames with the matched destination addresses and accepts frames with the address outside the CAM address enabled No CAM comparison mode MCompEn 0 The CAM controller accepts frames with all types of destinat...

Page 337: ...of any current frame 2 Suppress padding MNoPad Set this bit not to generate pad bytes for frames of less than 64 bytes 3 Suppress CRC MNoCRC Set this bit to suppress addition of a CRC at the end of a frame 4 Fast back off MFBack Set this bit to use faster back off times for testing 5 No defer MNoDef Set this bit to disable the defer counter The defer counter keeps counting until the carrier sense ...

Page 338: ...Transmission collision count MCollCnt This 4 bit value is the count of collisions that occurred while successfully transmitting the frame 12 Transmission deferred MTxDefer This bit is set if transmission of a frame was deferred because of a delay during transmission 13 Signal quality error SQEErr According to the IEEE802 3 specification the SQE signal reports the status of the PMA MAU or transceiv...

Page 339: ... stop reception immediately 1 Receive halt request MRxHalt Set this bit to halt reception after completing the reception of any current frame 2 Long enable MLongEn Set this bit to receive frames with lengths greater than 1518 bytes 3 Short enable MShortEn Set this bit to receive frames with lengths less than 64 bytes 4 Strip CRC value MStripCRC Set this bit to check the CRC and then strip it from ...

Page 340: ...cription Reset Value MACRXSTATA 0xF00B0014 R W Receive status 0x00000000 MACRXSTATB 0xF00D0014 R W Receive status 0x00000000 Table 7 39 MAC Receive Status Register Description Bit Number Bit Name Description 7 0 These bits are equal to the BMRXSTAT 7 0 8 Short Frame Error MRxShort This bit is set if the frame was received with short frame 9 Receive 10 Mb s status MRx10Stat This bit is set to 1 if ...

Page 341: ...escription Reset Value STADATAA 0xF00B0018 R W Station management data 0x00000000 STADATAB 0xF00D0018 R W Station management data 0x00000000 Table 7 41 Station Management Register Description Bit Number Bit Name Description 15 0 Station management data This register contains a 16 bit data value for the station management function ...

Page 342: ... address 0x00006000 Table 7 43 STACON Register Description Bit Number Bit Name Description 4 0 PHY register address MPHYRegAddr A 5 bit address contained in the PHY of the register to be read or written 9 5 PHY address MPHYaddr The 5 bit address of the PHY device to be read or written 10 Write MPHYwrite To initiate a write operation set this bit to 1 For a read operation clear it to 0 11 Busy bit ...

Page 343: ...n 21 entries the higher bits are ignored Table 7 44 CAMEN Register Registers Address R W Description Reset Value CAMENA 0xF00B0028 R W CAM enable 0x00000000 CAMENB 0xF00D0028 R W CAM enable 0x00000000 Table 7 45 CAM Enable Register Description Bit Number Bit Name Description 20 0 CAM enable Set the bits in this 21 bit value to selectively enable CAM locations 20 through 0 To disable a CAM location...

Page 344: ...es an interrupt if the corresponding interrupt enable bit is set If station management software wants more frequent interrupts you can set the missed error count register to a value closer to the rollover value of 0x7FFF For example setting a register to 0x7F00 would generate an interrupt when the count value reaches 256 occurrences Table 7 46 MISSCNT Register Registers Address R W Description Res...

Page 345: ...Pause count received The count value indicates the number of time slots the transmitter was paused due to the receipt of control pause operation frames from the MAC 7 4 2 13 MAC Remote Pause Count Register Table 7 50 RMPZCNT Register Registers Address R W Description Reset Value RMPZCNTA 0xF00B0044 R Remote pause count 0x00000000 RMPZCNTB 0xF00D0044 R Remote pause count 0x00000000 Table 7 51 Remot...

Page 346: ...try with the destination address the CAM1 entry with the source address and the CAM 18 entry with length type opcode and operand You then set the send pause bit in the MAC transmit control register Table 7 52 CAM Register Registers Address R W Description Reset Value CAMA 0xF00B0080 0xF00B00FC R W CAM content 32 word Undefined CAMB 0xF00D0080 0xF00D00FC R W CAM content 32 word Undefined Table 7 55...

Page 347: ...o qualify as a valid station address the first bit transmitted the LSB of the first byte must be a 0 Length or type 2 byte The MAC treats length fields greater than 1500 byte as type fields Byte values less than or equal to 1500 indicate the number of logical link control LLC data bytes in the data field The MAC transmits the high order byte first Logical link control LLC data 46 to 1500 byte Data...

Page 348: ...oint SNAP Subnetwork access protocol PID Protocol identifier LLC Logical lick control FCS Frame check sequence OR Data frame delivered to user Figure 7 5 Fields of an IEEE802 3 Ethernet Frame 7 5 1 1 Options that affect the Standard MAC Frame There are a number of factors and options that can affect the standard MAC frame as described in Table 7 2 Some PHYs may deliver a longer or shorter preamble...

Page 349: ...he first 64 bytes until after this station has acquired the net At that time the transmitter requests more data and transmits it until the signalling the end of data to be transmitted The transmitter appends the calculated CRC to the end of the frame A frame transmit operation can be subdivided into two operations 1 MII transmit interface operation and 2 BDMA MAC transmit interface operation 7 5 1...

Page 350: ...0 random integer r 2K K min n back off limit 10 r is the number of slot times the MAC must wait in case of a collision and n is the number of retry attempts For example after the first collision n is 1 and r is a random number between 0 and 1 The pseudo random generator in this case is one bit wide and gives a random number of either 0 or 1 After the second attempt r is a random number between 0 a...

Page 351: ...te time 8 byte preamble and SFD and 64 byte frame the main transmission state machine stops the transmission and transmits a jam pattern 32 bit 1 s It then increments the collision attempt counter returns control to the back off state machine and re transmits the frame when the back off time has elapsed and the gap time is valid If there are no collisions the transmitter block transmits the rest o...

Page 352: ...of data must be present in the MTxFIFO The BDMA engine can start stuffing data into the MTxFIFO and then enable the transmit bit or it can enable the transmit bit first and then start stuffing data into the MTxFIFO The transmitting operation can only start if both of these conditions are met 7 5 1 4 Receiving a Frame The receiver block when enabled constantly monitors a data stream coming either f...

Page 353: ... RX_DV signal which entered the MII from the PCS layer will be ON when the PCS layer recovers the Rx_clk from the receive bit stream and delivers the nibble data on RxD 3 0 data line The RX_DV signal must be ON before the starting frame delimiter SFD is received When the Rx_DV signal is ON the preamble and SFD parts of the frame header are delivered to MII synchronized with the 25MHz Rx_clk The ca...

Page 354: ...eset the MRxFIFO is empty To enable the reception the system must set the receive enable bit in the MACRXCON register If the BDMA engine cannot transfer the received data to the BRxBUFF and memory due to the disabled BDMA or the inaccessibility on the system bus the MAC RxFIFO may overflow Carrier sense on Carrier sense ON after detection SFD store byte stream in in FIFO Recognize address Move the...

Page 355: ... PHY device register it must transmit the frame data up to a specific register address to the PHY device During the write time which is an undirected transmission the STA transmits a stream of turn around bits As a result by transmitting a write or read message to a PHY device through the MDIO the STA can issue a request to set the operation or to read the operation status As its response this mes...

Page 356: ...id and the frame must contain a valid pause opcode and a parameter pause period field If the length type field does not have the special value specified for MAC control frames the MAC takes no action and the frame is treated as a normal frame If the frame is marked as a MAC control frame and pass through is enabled it is passed to the software drivers User can set the control bit in the MAC contro...

Page 357: ...signals the end of the pause operation and before allowing the transmit circuit to resume its operation If a second full duplex pause operation is recognized while the first operation is in effect the pause counter is reset with the current operand value Note that a count value of zero may cause pre mature termination of a pause operation that is already in progress 7 5 3 2 Remote Pause Operation ...

Page 358: ...erflow of the MTxFIFO during transmission indicates that the system cannot keep up with the demand of the MAC and the transmission is aborted No Carrier The carrier sense signal CrS is monitored from the beginning of the start of frame delimiter SFD to the last byte transmitted A NoCarr indicates that CrS was never present during transmission a possible network problem but the transmission will NO...

Page 359: ...orts a CRC error if it is invalid The PHY informs the MAC if it detects a medium error such as a coding violation by asserting the input pin RX_ER When the MAC sees RX_ER asserted it sets CRCErr bit of the BMRXSTAT register Frame too long The receiver block checks the length of the incoming frame at the end of reception including CRC but excluding preamble and SFD If the length is longer than the ...

Page 360: ...td 802 3 Section 22 3 Signal Characteristics Output Valid TX_CLK TXD 3 0 TX_EN 4 9ns MIN 28ns MIN Figure 7 13 Timing Relationship of Transmission Signals at MII RX_CLK RXD 3 0 RX_DV Th 5ns Ts 3ns Input Valid Figure 7 14 Timing Relationship of Reception Signals at MII MDC MDIO Input Valid Ts 15ns Figure 7 15 MDIO Sourced by PHY MDC MDIO Output Valid Th 13ns Figure 7 16 MDIO Sourced by STA ...

Page 361: ...ns The HDLC module supports a CPU data link interface that conforms to the synchronous data link control SDLC and high level data link control HDLC standards In addition the following function blocks are integrated into the HDLC module Three channel DMA engine for Tx Rx Support buffer descriptors per frame Digital phase locked loop DPLL block Baud rate generator BRG ...

Page 362: ... for clock recovery Baud rate generator NRZ NRZI FM Manchester data formats for Tx Rx Loop back and auto echo mode Tx and Rx clock inversion Tx and Rx FIFOs with 8 word 8 x 32 bit depth Selectable 1 word or 4 word data transfer mode for Tx Rx Data alignment logic Endian translation Programmable interrupts Modem interface Hardware flow control Buffer descriptor for Tx Rx Three channel DMA Controlle...

Page 363: ...ntroller Address Data Control Tx FIFO 8 Words Flag Abort Idle Generateor and Transmitter Receive shift Register Rx FIFO 8 words FCS Generator Zero Insertion Flag Abort Idle Detection Zero Delection loop DPLL dplloutR dplloutT RxD TxC TxD autoecho RxC MCLK2 66 MHz brgout1 brgout2 Word System BUS HDLC Control and Status Registers FCS Checker Encoder Decoder Remote Serial Port BRG Figure 8 1 HDLC Mod...

Page 364: ...extended up to four bytes using a optional software control setting 8 3 1 1 Flag F A flag is a unique binary pattern 01111110 that is used to delimit HDLC frames This pattern is generated internally by the transmitter An opening flag starts a frame and a closing flag ends the frame Opening flags and closing flags are automatically appended to frames A single flag pattern can optionally serve as bo...

Page 365: ...e however must actually contain information data The word length of the I field is eight bits in the S3C2500B HDLC module And Its total length can be extended by 8 bits until terminated by the FCS field and the closing flag 8 3 1 6 Frame Check Sequence FCS Field The 16 bits that precede the closing flag comprise the frame check sequence FCS field The FCS field contains the cyclic redundancy check ...

Page 366: ...nce can be extended up to at least 16 consecutive 1s by setting the abort extend control bit TxABTEXT in HCON to 1 This feature is useful for forcing the mark idle state The receiver interprets the reception of seven or more consecutive 1s as an abort The receiver responds the abort received as follows An abort in an out of frame condition an abort has no meaning during the idle or the time fill A...

Page 367: ... output of the baud rate generator may toggle upon reaching zero the value in the time constant register is loaded into the counter and the process is repeated The time constant may be changed any time but the new value does not take effect until the next load of the counter The output of the baud rate generator may be used as either the transmit clock the receive clock or both It can also drive t...

Page 368: ... Rate MCLK2 66 MHz R C 24 576 MHz BRGOUT2 CNT0 CNT1 CNT2 Freq Dev CNT0 CNT1 CNT2 Freq Dev 400K 164 0 0 400000 0 0 60 0 0 402885 0 7 600K 109 0 0 600000 0 0 40 0 0 599415 0 1 800K 82 0 0 795181 0 6 30 0 0 792774 0 9 1000K 65 0 0 1000000 0 0 24 0 0 983040 1 7 4000K 16 0 0 3882353 2 9 5 0 0 4096000 2 4 6000K 10 0 0 6000000 0 0 3 0 0 6144000 2 4 8000K 7 0 0 8250000 3 1 2 0 0 8192000 2 4 10000K 6 0 0 9...

Page 369: ...l phase locked loop It consists of a 5 bit counter an edge detector and a pair of output decoders Edge Detector Count Modifier Decoder Receive Clock dplloutR HMODE 18 16 5 bit Counter Decoder Transmit clock dplloutT RxD TxC RxC MCLK2 BRGOUT1 BRGOUT2 Figure 8 3 DPLL Block Diagram 8 4 9 CLOCK USAGE METHOD NOTE BRGCLK HMODE 19 DPLLCLK HMODE 18 16 TxCLK HMODE 22 20 RxCLK HMODE 26 24 DPLLOUTT DPLLORTR ...

Page 370: ...ison the mark space ratio 50 of the incoming signal must not deviate more than 1 5 of its baud rate if proper locking is to occur In the FM mode the DPLL clock must be 16 times the data rate The 5 bit counter in the DPLL counts from 0 to 31 so the DPLL makes two sampling clocks during the 0 to 31 counting cycle The DPLL output is Low while the DPLL is waiting for an edge in the incoming data strea...

Page 371: ...ock select Transmit clock select Receive clock select BRG DPLL enable to use internal clock You must also set the clock for various components before each component is enabled Additional registers may also have to be programmed depending on the features you select All settings for the HDLC mode register HMODE and the HDLC control register HCON must be programmed before the HDLC is enabled To enabl...

Page 372: ... provides four different data encoding methods selected by bits in HCON1 18 16 An example of these four encoding methods is shown in figure 8 5 1 1 0 0 1 0 Data NRZ NRZI FM1 Biphase Mark FM0 Biphase Space Manchester NRZ NRZI Type TxClock Data RxClock FM0 FM1 Manchester type TxClock Data RxClock Bit Cell Level High 1 Low 0 No Change 1 Change 0 Bit Center Transition Transition 1 No Transition 0 No T...

Page 373: ...HDLC Data Setup and Timing Diagrams Tx data will be sent with delayed 9 82nsec to 10 66nsec from the falling edge of Tx Clock The data of the red period should not be changed That is the RxD should be stable from 0 2nsec to 1 0nsec after RxC rising edge It does not allow data transition during this period The RxC will be Rx receiver clock through Rx clock selection part with some delay And this Rx...

Page 374: ...ssuming the TxFA bit is set to 1 When you select 4 word transfer mode four successive words can be transferred to the FIFO if the TxFA bit is set to 1 The nCTS clear to send input nRTS request to send and nDCD data carrier detect are provided for a modem or other hardware peripheral interface In auto enable mode nDCD becomes the receiver enable However the receiver enable bit must be set before th...

Page 375: ...nsmitting an abort The underrun state is indicated when the transmitter underrun status bit TxU is 1 Whenever you set the transmission abort control bit TxABT in HCON the transmitter immediately aborts the frame transmits at least eight consecutive 1s clearing the Tx FIFO If the transmission abort extension control bit TxABTEXT is set at the time an idle pattern at least 16 consecutive 1s is trans...

Page 376: ...receiver operation is free of the nDCD input level 8 5 5 1 Receiver Interrupt Mode Whenever data is available in the HRXFIFO an interrupt is generated by RxFA if the interrupt is enabled The CPU reads the HDLC status register either in response to the interrupt request or in turn during a polling sequence When the received data available bit RxFA is 1 the CPU can read the data from the HRXFIFO If ...

Page 377: ...lowing data transmission At the beginning of the data is an open flag while at the end a closing flag If the frame being transferred discontinues nRTS goes back to the High after the data transmission is completed TxClock TxD RTS CTS Data 14 22 cycles 5 13 cycles Figure 8 8 CTS Lost During Transmission When the condition of nCTS is shifted from Low to High it is detected at the falling edge of Tx ...

Page 378: ...xClock TxD RTS CTS Data 5 12 cycles Figure 8 9 CTS Delayed on If nCTS remains still High for a while after nRTS enters Low to allow data transmission from HTxFIFO the data transmission starts 5 12 cycles after nCTS is shifted to Low ...

Page 379: ...smit buffer descriptor Receive buffer descriptor Each Tx DMA buffer descriptor has the following elements Buffer data pointer Ownership bit Control field for transmitter Status field for Tx Transmit buffer length Each Rx DMA buffer descriptor has the following elements Buffer data pointer Ownership bit Status field for Rx Accumulated received buffer length for a frame ...

Page 380: ... register If the received data is longer than the value of the maximum frame length register this frame is ignored and the FLV bit is set The software also sets the DMA Rx buffer descriptor pointer to point to a chain of buffer descriptors all of which have their ownership bit The DMA controller can be started to set the DMA Rx enable bit in the control register When a frame is received it is move...

Page 381: ...0 Big Endian 1 Little Endian 19 Last L 0 This is not the last buffer in the frame 1 This is the last buffer int the frame 20 Buffer Data Pointer Decrement D 0 Increment 1 Decrement 22 21 Widget Alignment Control WA 00 No invalid bytes 01 1 invalid bytes 10 2 invalid bytes 11 3 invalid bytes Tx Status Bit These bit may be regarded as valid when the L bit in Tx control bit is set 26 Transmission com...

Page 382: ...9 Overrun OV 0 Normal 1 The received frame overruns 20 DPLL Two Miss DTM 0 Normal 1 DPLL two miss clock occurs 21 Rx Abort ABT 0 Normal 1 The received frame aborted 22 First In Frame F 0 This buffer descriptor status is not the first to the frame 1 This buffer descriptor status is the first to the frame 23 Last In Frame L 0 This buffer descriptor status is not the last to the frame 1 This buffer d...

Page 383: ...e Register Value NOTE 1 Buffer length is accumulated until the last bit is set in STATUS Buffer data pointer indicates the buffer memory start address 2 After HRXBDMAXCNT Buffer Descriptors used the Rx Buffer Descriptor Address Pointer points start address Buffer Data Pointer 2 Status Buffer Length Buffer Data Pointer N Status Buffer Length 0 31 HRXBDMAXCNT N Figure 8 12 Data Structure of the Rece...

Page 384: ...0 F0100018 R HRxFIFO entry register 0 00000000 HBRGTCA 0 F010001C R W HDLC BRG time constant register 0 00000000 HPRMBA 0 F0100020 R W HDLC preamble register 0 00000000 HSAR0A 0 F0100024 R W HDLC station address 0 0 00000000 HSAR1A 0 F0100028 R W HDLC station address 1 0 00000000 HSAR2A 0 F010002C R W HDLC station address 2 0 00000000 HSAR3A 0 F0100030 R W HDLC station address 3 0 00000000 HMASKA ...

Page 385: ...00000000 HSAR1B 0 F0110028 R W HDLC station address 1 0 00000000 HSAR2B 0 F011002c R W HDLC station address 2 0 00000000 HSAR3B 0 F0110030 R W HDLC station address 3 0 00000000 HMASKB 0 F0110034 R W HDLC mask register 0 00000000 HDMATxPTRB 0 F0110038 R W DMA Tx buffer descriptor pointer 0 FFFFFFFF HDMARxPTRB 0 F011003C R W DMA Rx buffer descriptor pointer 0 FFFFFFFF HMFLRB 0 F0110040 R W Maximum f...

Page 386: ...00000000 HSAR1C 0 F0120028 R W HDLC station address 1 0 00000000 HSAR2C 0 F012002c R W HDLC station address 2 0 00000000 HSAR3C 0 F0120030 R W HDLC station address 3 0 00000000 HMASKC 0 F0120034 R W HDLC mask register 0 00000000 HDMATxPTRC 0 F0120038 R W DMA Tx buffer descriptor pointer 0 FFFFFFFF HDMARxPTRC 0 F012003C R W DMA Rx buffer descriptor pointer 0 FFFFFFFF HMFLRC 0 F0120040 R W Maximum f...

Page 387: ...Endian mode RxLittle This bit determines whether the data is in Little or Big endian format HRXFIFO is in Little endian If this bit is set to 0 then the data on the system bus should be in Big endian Therefore the bytes will be swapped in Big endian 5 Tx Little Endian mode TxLittle This bit determines whether Tx data is in Little or Big endian TxLittle format HTxFIFO is in Little endian If this bi...

Page 388: ...GCLK If this bit is 1 MCLK2 is selected as the source clock for the baud rate generator BRG If this bit is 0 the external clock at the RXC pin is selected as the BRG source clock 22 20 Tx clock select TxCLK Using this setting you can configure the transmit clock source to one of the following pins TXC RXC DPLLOUTT BRGOUT1 or BRGOUT2 To select one of these pins set the TxCLK bits to 000 001 010 011...

Page 389: ...1 6 byte 010 3 byte 110 7 byte 011 4 byte 111 8 byte 11 Reserved 14 12 Data Format DF 000 NRZ data format 001 NRZI 010 FM0 001 FMI 100 Manchester 31 0 3 4 5 1 2 TXC OPS 30 28 27 26 23 22 20 19 15 14 10 24 18 16 12 11 8 7 6 RxCLK TxCLK B R G C L K DPLL CLK DF T x L i t t l e TxPL R x L i t t l e T x C I N V R x C I N V M F F R T R n R T S T x T R A N S R x T R A N S 15 RTRnRTS 0 Request to send 1 R...

Page 390: ... cannot be loaded into the HTxFIFO If this bit is set to 1 the idle pattern is sent continuously In this case the data can be loaded into HTxFIFO and then sent 5 Rx enable RxEN When the RxEN bit is 0 the receiver enters a disabled state and can not detect the flag pattern if any In this case receiver block is cleared except for the HRXFIFO and the status bits associated with receiver operation are...

Page 391: ...tempts it sets the two clock missing bit and the DPLL automatically enters the Search mode To reset both clocks missing latches you can disable and re enable the DPLL using the reset Rx status 9 BRG enable BRGEN This bit controls the operation of the baud rate generator BRG To enable the BRG counter set the BRGEN bit to 1 To inhibit counting clear the bit to 0 10 Tx 4 word mode Tx4WD When this bit...

Page 392: ...he selected active or inactive idle state continues until data is sent after nRESET has return to High level The flag idle pattern is 7EH the mark idle pattern is FFH 18 Tx single flag TxSFLAG This bit controls whether separate closing and opening flags are transmitted in succession to delimit frames When this bit is 0 independent opening and closing flags are transmitted in order to separate fram...

Page 393: ... is used only by the Transmitter Interrupt Mode not by the Transmitter DMA Mode see 8 14 27 Rx no CRC RxNOCRC When this bit is set to 1 the receiver does not check for CRC by hardware CRC data is always moved to the HRXFIFO 28 Auto enable AutoEN This bit programs the function of both nDCD and nCTS However TxEN and RxEN must be set before the nCTS and nDCD pins can be used When this bit is 0 if the...

Page 394: ...id byte 01 1 invalid byte 10 2 invalid byte 11 3 invalid byte 14 DMA Tx stop or skip DTxSTSK 0 DMA Tx stops when DMA not owner bit is set 1 DMA Tx skips when DMA not owner bit is set 15 DMA Rx stop or skip DRxSTSK 0 DMA Rx stops when DMA not owner bit is set 1 DMA Rx skips when DMA not owner bit is set 16 DMA Rx memory address decrement DRxMADEC 0 Address is incremented 1 Address is decremented 17...

Page 395: ...ht consecutive 1 s are transmitted 1 At least 16 consecutive 1 s are transmitted 22 Tx abort TxABT 0 Normal 1 Enable at least eight consecutive 1 s are transmitted 23 Tx preamble TxPRMB 0 Transmit a mark idle is time fill bit pattern 1 Transmit the content of HPRMB 24 Tx data terminology ready TxDTR 0 nDTR goes high level 1 nDTR goes low level 25 Rx frame discontinue TxDISCON 0 Normal 1 Ignore the...

Page 396: ...HSTATC Register Registers Address R W Description Reset Value HSTATA 0 F0100008 R W HDLC Channel A Status Register 0X00000000 HSTATB 0 F0110008 R W HDLC Channel B Status Register 0X00000000 HSTATC 0 F0120008 R W HDLC Channel C Status Register 0X00000000 8 7 4 SUMMARY There are two kinds of bits in a status register 1 TxFA TxCTS RxFA RxDCD RxFV RxCRCE RxNO RxIERR and RxOV bits are show each bit s s...

Page 397: ...nCTS input pin is Low this status bit is 1 If nCTS input pin is High level TxCTS is 0 This bit does not generate an interrupt 7 Tx stored clear to send TxSCTS This bit is set to 1 each time a transition in nCTS input occurs You can clear this bit by writing 1 to this bit 8 Tx under run TxU When the transmitter runs out of data during a frame transmission an underrun occurs and the frame is automat...

Page 398: ...m of 15 consecutive 1s have been received The event is stored in the status register and can be used to trigger a receiver interrupt The RxIDLE bit continues to reflect the inactive idle condition until a 0 is received You can clear this bit by writing a 1 to this bit 16 Rx abort RxABT The RxABT status bit is set to 1 when seven or more consecutive 1s abort sequence have been received When an abor...

Page 399: ...xFD In case of MFF bit is 0 default when DNA Tx operation has successfully transferred rest byte of frame from Tx FIFO to destination this bit will be set to 1 But if MFF is set to 1 transceiver will keep sending the data until there is no data transfer from memory to TxFIFO 28 Reserved Not applicable 29 DMA Tx not owner DTxNO This bit is set when DMA is not owner of the current buffer descriptor ...

Page 400: ...out of data during transmission 9 Rx FIFO available RxFA 0 Normal operation 1 Data is available in the RxFIFO 10 Tx Frame Good TxFG 0 Normal operation 1 Tx Data sent well 11 Rx flag detected RxFD 0 Normal operation 1 This bit is set when the last bit of the flag sequence is received 12 Rx data carrier detected RxDCD 0 nDCD input pin is High 1 nDCD input pin is Low 13 Rx stored data carrier detecte...

Page 401: ...ed a frame from RxFIFO to buffer memory 25 Reserved 26 DMA Rx not owner DRxNO 0 DMA has the ownership 1 CPU has the ownership 27 DMA Tx frame done DTxFD 0 Normal operation 1 DMA Tx operation has successfully transferred a frame from memory to TxFIFO 28 Reserved 29 DMA Tx not owner DTxNO 0 DMA has the ownership 1 CPU has the ownership 30 DPLL one clock missing DPLLOM 0 Normal operation 1 Set in FM ...

Page 402: ...ailable to read interrupt enable 10 TxFGIE Tx Frame Good interrupt enable 11 RxFDIE Rx flag detected interrupt enable 12 Reserved 13 RxSDCDIE DCD transition interrupt enable 14 RxFVIE Rx frame valid interrupt enable 15 RxIDLEIE Idle detected interrupt enable 16 RxABTIE Abort detected interrupt enable 17 RxCRCEIE CRC error frame interrupt enable 18 RxNOIE Non octet aligned frame interrupt enable 19...

Page 403: ...IE 10 Tx Frame Good Interrupt enable TxFGIE 11 Flag detected interrupt enable RxFDIE 12 Reserved 13 DCD transition interrupt enable RxSDCDIE 14 Valid frame interruopt enable RxFVIE 15 Idle detected interruot enable RxIDLEIE 16 Abort detected interrupt enable RxABTIE 17 CRC error frame interrupt enable RxCRCEIE 18 Non dctet aligned frame interrupt enable RxNOIE 19 Rx overrun interrupt enable RxOVIE...

Page 404: ...controller writes data to the HTxFIFO Tx buffer descriptor Buffer Length field value must be pre set However if the Last bit is set in buffer descriptor the last byte pointer in HTxFIFO is also set This means the last byte of the frame is in HTxFIFO If the transmitted frame is longer than the Buffer Length field value the last byte pointer will not be set and the next buffer descriptor having the ...

Page 405: ... indicate the current state of the HRXFIFO When the HRXFIFO data status bit is 1 the HRXFIFO is ready to be read The HRXFIFO data status is controlled by the 4 word or 1 word transfer selection bit Rx4WD When an overrun occurs the overrun frame of the HRXFIFO is no longer valid An in frame abort or a High level on nDCD input with the AutoEN bit in HCON is set to 1 the frame is cleared in the HRXFI...

Page 406: ...r this reason you should first disable the baud rate generator before loading the new time constant into the HBRGTC register The formula for determining the appropriate time constant for a given baud rate is shown below The desired rate is shown in bits per second This formula shows how the counter decrements from N down to zero plus one cycles for reloading the time constant This value is then fe...

Page 407: ...ble 8 16 HPRMBA and HPRMBB Register Registers Address R W Description Reset Value HPRMBA 0 F0100020 R W HDLC Preamble Constant Register 0x00000000 HPRMBB 0 F0110020 R W HDLC Preamble Constant Register 0x00000000 HPRMBC 0 F0120020 R W HDLC Preamble Constant Register 0x00000000 1 0 Preamble pattern 31 0 21 Preamble Pattern 22 23 24 25 26 27 28 29 30 16 18 17 19 20 11 13 12 14 15 7 8 10 9 Figure 8 20...

Page 408: ...F0100028 R W HDLC station address 1 0x00000000 HSADR2A 0 F010002C R W HDLC station address 2 0x00000000 HSADR3A 0 F0100030 R W HDLC station address 3 0x00000000 HMASKA 0 F0100034 R W HDLC address mask register 0x00000000 HSADR0B 0 F0110024 R W HDLC station address 0 0x00000000 HSADR1B 0 F0110028 R W HDLC station address 1 0x00000000 HSADR2B 0 F011002C R W HDLC station address 2 0x00000000 HSADR3B ...

Page 409: ...he address of the Tx buffer data pointer on the data to be sent During a DMA operation the buffer descriptor pointer is updated by the next buffer data pointer Table 8 19 DMA Tx Buffer Descriptor Pointer Registers Registers Address R W Description Reset Value HDMATXPTRA 0 F0100038 R W DMA Tx Buffer Descriptor Pointer 0xFFFFFFFF HDMATXPTRB 0 F0110038 R W DMA Tx Buffer Descriptor Pointer 0xFFFFFFFF ...

Page 410: ...A Rx buffer descriptor pointer 0 DMA Rx Buffer Descriptor Pointer 25 26 27 28 29 30 Figure 8 24 DMA Rx Buffer Descriptor Pointer 8 7 13 MAXIMUM FRAME LENGTH REGISTER The HDLC controller checks the length of an incoming frame against the user defined value in DMA mode If the frame received exceeds this register value the frame is discarded and FLV Frame Length Violated bit is set in the buffer desc...

Page 411: ...Size 22 23 24 25 26 27 28 29 30 Figure 8 26 DMA Receive Buffer Size Register 8 7 15 SYNCHRONIZATION REGISTER The HDLC synchronous register content will be sent during flag idle in HDLC mode In mark idle mode this register content can not used However in transparent mode with in line sync this register value used for searching sync pattern This sync pattern is used as like opening or closing flag I...

Page 412: ...rent Control Register 0xXXXX0000 TCONC 0xF012004C R W Transparent Control Register 0xXXXX0000 Bit Number Bit Name Description 1 0 Data sampling DS These bit values determine which data bits are regarded as valid after the nDCD state active 00 the first valid bit is D4 01 the first valid bit is D3 10 D2 and 11 D1 See Figure 8 28 data sampling method 3 2 Reserved Not applicable 4 RTS control RTS It ...

Page 413: ...x buffer descriptor count register 0 XXXXX000 HTXBDCNTC 0 F01200C0 R Tx buffer descriptor count register 0 XXXXX000 8 7 18 RX BUFFER DESCRIPTOR COUNT REGISTER Rx Buffer Descriptor count register which shows how many Rx buffer descriptor is used Table 8 26 HRXBDCNTA HRXBDCNTB and HRXBDCNTC Register Registers Address R W Description Reset Value HRXBDCNTA 0 F01000C4 R Rx buffer descriptor count regis...

Page 414: ...rol register 0 XXXXXFFF HTXBDMAXCNTC 0 F01200C8 R W Tx buffer descriptor maximum count control register 0 XXXXXFFF 8 7 20 RX BUFFER DESCRIPTOR MAXIMUM COUNT REGISTER Rx Buffer Descriptor maximum count register sets rx buffer descriptor maximum counts For example if you set the HRXBDMAXCNT register to 0xFFF then you can use 1 20 buffer descriptor If you set the HRXBDMAXCNT register to 0xFFE 0xFFC 0...

Page 415: ...ICs The S3C2500B includes the IOM2 controller to enable a modular interface to the terminal network such as an ISDN interface 9 2 FEATURES IOM2 terminal mode support Inter device communication via IC channel TIC bus access control Monitor channel collision control Optional signals such as BCL and STRB Bus Deactivation Activation via C I0 Bus Reversal ...

Page 416: ...ree additional signals are specified in the terminal mode to facilitate connecting components that do not directly support IOM2 These are a 1x Bit rate Clock BCL and two Serial Data Strobes that identify the location of the B channels SDS1 and SDS2 The S3C2500B includes two optional signals BCL and SDS1 SDS1 is called STRB in S3C2500B In S3C2500B the terminal mode operation is supported but line c...

Page 417: ...dshake bits that control data flow 9 3 4 COMMAND AND INDICATE CHANNELS Three Command and Indicate channels C I0 C I1 and C I2 provide real time status between devices connected via the IOM2 bus 9 3 5 INTERCOMMUNICATION CHANNELS Two intercommunication data channels IC1 and IC2 provide 64 Kbit s data paths between user devices 9 3 6 TIC BUS One D channel accesses bus TIC bus The TIC function is impl...

Page 418: ...itor transmit and MR monitor receive For example data is placed onto the monitor channel and the MX bit is activated This data will be transmitted repeatedly once per 8 KHz frame until the transfer is acknowledged via the MR bit Receiver Transmitter MX MR 1st Byte MR MX MD 1st byte Acknowledge MX Monitor transmit bit active low MR Monitor receive bit active low MD Monitor data 2nd Byte MX MD 2nd b...

Page 419: ...ing it once in the inactive state When the MRxBA interrupt is generated and the CPU read out the IOM2MRD the receiver acknowledges the data by returning the MR bit active after sending it once in the inactive state This in turn causes the transmitter to generate an MTxBA interrupt When the last byte has been transmitted and acknowledged the CPU set the MTxEOM End of Message Request to 1 This enfor...

Page 420: ...llision detection interrupt is generated and the transmitter reverts back to waiting for the idle condition 9 3 7 4 C I Channel Operation The C I0 channel carries the commands and indications between the S3C2500B and layer 1 device to control the activation deactivation procedures C I0 channel access may be arbitrated via in the TIC bus access protocol The CPU have access to C I0 channel by using ...

Page 421: ...compares the bit with the value on DU If any bit mismatches that is a sent bit set to 1 is read back as 0 the IOM2 controller withdraws immediately from the TIC bus If more than one device attempt to access the bus simultaneously the one with the lowest address values wins If all the TIC bus address bits match the TIC bus is immediately occupied by the IOM2 controller by setting the BAC to 0 in th...

Page 422: ...Only one channel must be accessed at a time since the IOM2 controller has registers for one channel The IC channel0 is accessed by setting the ICSEL bit to 0 Because the data output is open drain the unused IC channel and all High bits of the chosen IC channel are placed in a high impedance state unless used by an HDLC frame 9 3 7 7 Pin Direction Reversal The data signals on the IOM2 bus are defin...

Page 423: ... can directly be connected to the external serial interface In PCM highway and IOM2 interface the TSA is located between the HDLC and the external serial interface By intervening in between the TSA provides the appropriate HDLC clocks during its programmed timeslot within an 8 KHz frame The TSA can support a maximum data rate of up to 10 Mbps with HDLCs In PCM highway interface up to 156 time slot...

Page 424: ..._RXCC PCM_DCLC DCE_RXCC DCE_RXDC PCM_RXDC DCE_RXDC 9 4 4 OPERATION The Time Slot Assigner TSA controllers are configured as follows 1 Configure the TSAxCON register Define the start bit position for each TSA Define the stop bit position for each TSA Determine operating mode for each TSA DCE PCM highway non multiplexed or multiplexed and IOM2 interface 2 Enable TSA by setting TSAEN bit in IOM2CON 1...

Page 425: ...4 R W IC Channel Rx Buffer 0x00000000 IOM2CITD0 0xF0130018 R W C I0 Channel Tx Buffer 0x0000000F IOM2CIRD0 0xF013001C R W C I0 Channel Rx Buffer 0x00000000 IOM2CITD1 0xF0130020 R W C I1 Channel Tx Buffer 0x0000003F IOM2CIRD1 0xF0130024 R W C I1 Channel Rx Buffer 0x00000000 IOM2MTD 0xF0130028 R W Monitor Channel Tx Buffer 0x000000FF IOM2MRD 0xF013002C R W Monitor Channel Rx Buffer 0x000000FF TSAACO...

Page 426: ... 1 6 Monitor Channel Address Valid MAV 0 cleared before the first byte is received 1 The CPU indicates the monitor receiver that the first byte address received is valid 7 Monitor Channel Sends End of Message MTxEOM 0 cleared after the EOM is sent 1 The monitor transmitter is forced to send an End of Message EOM 8 Bus Request for C I0 BREQ 0 The TIC bus is released 1 The IOM2 controller starts to ...

Page 427: ...8 Bus Request BREQ 0 Normal 1 Request TIC bus to send C I0 data 9 Monitor Channel Select MSEL 0 Monitor 0 selected 1 Monitor 1 selected 10 IC channel Select ICSEL 0 IC 0 selected 1 IC 1 selected 11 AWAKE AWAKE 0 Normal 1 Request the transceiver to deliver DCL 12 LoopBack LOOP 0 Normal 1 Loopback mode 13 TSA Enable TSAEN 0 Disable 1 Enable 14 Transceiver Type Select TTSEL 0 Transceiver that transmi...

Page 428: ...ransmitter should respond to this by sending EOM MX 1 during more than two frames 6 Monitor Channel Collision Detected MCOL 0 normal 1 The monitor channel collision has occurred 7 Monitor Channel Tx Buffer Available MTxBA 0 Cleared when the IOM2MTD is written 1 A new data can be written to IOM2MTD 8 Monitor Channel Rx Buffer Available MRxBA 0 Cleared when the IOM2MRD is read 1 A new data has recei...

Page 429: ...tor Transmit Buffer Available MTxBA 0 Normal 1 Monitor tx buffer empty 8 Monitor Receive Buffer Available MRxBA 0 Normal 1 Monitor rx buffer data ready 9 Monitor Transmit Abort Detected MTxABT 0 Normal 1 Monitor channel Tx abort received 10 IC Buffer Available ICBA 0 Normal 1 IC buffer available 11 ALIVE ALIVE 0 IOM2 bus is in the inactive state DCL 1 1 IOM2 bus is in the active state DCLK is cloc...

Page 430: ... Buffer Available Interrupt Enable 3 4 MRxEOMIE Monitor Channel Receive End of Message Interrupt Enable 5 MRxABTIE Monitor Channel Receive Abort Interrupt Enable 6 MCOLIE Monitor Channel Collision Detected Interrupt Enable 7 MTxBAIE Monitor Channel Tx Buffer Available Interrupt Enable 8 MRxBAIE Monitor Channel Rx Buffer Available Interrupt Enable 9 MTxABTIE Monitor Channel Tx Abort Interrupt Enabl...

Page 431: ...er Available Interrupt Enable MTxBAIE 0 Disable 1 Enable 8 Monitor Receive Buffer Available Interrupt Enable MRxBAIE 0 Disable 1 Enable 9 Monitor Transmit Abort Detected Interrupt Enable MTxABTIE 0 Disable 1 Enable 10 IC Buffer Available Interrupt Enable ICBAIE 0 Disable 1 Enable 11 ALIVE Interrupt Enable ALIVEIE 0 Disable 1 Enable 12 NEWFSC Interrupt Enable NEWFSCIE 0 Disable 1 Enable 31 0 3 4 5 ...

Page 432: ...OM2TBA 0xF013000C R W TIC Bus Address 0x00000007 Bit Number Bit Name Description 2 0 TIC Bus Address TBA This field defines device specific address used to gain access to TIC bus for D and C I0 channel 31 3 Reserved 31 15 16 2 0 TIC Bus Address 0 18 17 12 13 14 9 10 11 6 7 8 3 4 5 2 TBA 19 21 20 22 23 24 25 26 27 28 29 30 Figure 9 10 IOM2 TIC Bus Address Register ...

Page 433: ...annel Transmit Data 0 18 17 12 13 14 9 10 11 7 8 ICTD 19 21 20 22 23 24 25 26 27 28 29 30 Figure 9 11 IOM2 IC Channel Transmit Data Register Table 9 8 IOM2ICRD IOM2 IC Channel Receive Data Register Register Address R W Description Reset Value IOM2ICRD 0xF0130014 R W IC Channel Receive Data 0x00000000 Bit Number Bit Name Description 7 0 ICRD Receive Data 31 8 Reserved 31 15 16 7 0 IC Channel Receiv...

Page 434: ...18 17 12 13 14 9 10 11 6 7 8 3 4 5 CITD0 19 21 20 22 23 24 25 26 27 28 29 30 Figure 9 13 IOM2 C I0 Channel Transmit Data Register Table 9 10 IOM2CIRD0 IOM2 C I0 Channel Receive Data Register Register Address R W Description Reset Value IOM2CIRD0 0xF013001C R W C I0 Channel Receive Data 0x00000000 Bit Number Bit Name Description 3 0 CIRD0 This field includes the data received on the C I0 channel Th...

Page 435: ...0 11 6 7 8 5 CITD1 19 21 20 22 23 24 25 26 27 28 29 30 Figure 9 15 IOM2 C I1 Channel Transmit Data Register 9 5 8 IOM2 C I1 CHANNEL RECEIVE DATA REGISTER Table 9 12 IOM2CIRD1 IOM2 C I1 Channel Receive Data Register Register Address R W Description Reset Value IOM2CIRD1 0xF0130024 R W C I1 Channel Receive Data 0x00000000 Bit Number Bit Name Description 5 0 CIRD1 This field includes the data receive...

Page 436: ... 25 26 27 28 29 30 Figure 9 17 IOM2 Monitor Channel Transmit Data Register 9 5 10 IOM2 MONITOR CHANNEL RECEIVE DATA REGISTER Table 9 14 IOM2MRD IOM2 Monitor Channel Receive Data Register Register Address R W Description Reset Value IOM2MRD 0xF013002C R W Monitor Channel Receive Data 0x00000000 Bit Number Bit Name Description 7 0 MRxD This field includes the data received on the monitor channel sel...

Page 437: ... time slot assigned to HDLCA 25 24 MODE 00 DCE 01 PCM highway non multiplexed 10 IOM2 11 PCM highway multiplexed 26 Divide 0 HDLC clock is the same clock as the external clock 1 HDLC clock is 1 2 times the external clock 31 27 Reserved 31 11 0 The location of START bit of time slot 23 12 The location of STOP bit of time slot 25 24 MODE 00 DCE 01 PCM Highway non multiplexed 10 IOM2 11 PCM Highway m...

Page 438: ... time slot assigned to HDLCB 25 24 MODE 00 DCE 01 PCM highway non multiplexed 10 IOM2 11 PCM highway multiplexed 26 Divide 0 HDLC clock is the same clock as the external clock 1 HDLC clock is 1 2 times the external clock 31 27 Reserved 31 11 0 The location of START bit of time slot 23 12 The location of STOP bit of time slot 25 24 MODE 00 DCE 01 PCM Highway non multiplexed 10 IOM2 11 PCM Highway m...

Page 439: ... time slot assigned to HDLCC 25 24 MODE 00 DCE 01 PCM highway non multiplexed 10 IOM2 11 PCM highway multiplexed 26 Divide 0 HDLC clock is the same clock as the external clock 1 HDLC clock is 1 2 times the external clock 31 27 Reserved 31 11 0 The location of START bit of time slot 23 12 The location of STOP bit of time slot 25 24 MODE 00 DCE 01 PCM Highway non multiplexed 10 IOM2 11 PCM Highway m...

Page 440: ...ster 0x00000000 Bit Number Bit Name Description 7 0 START The location of start bit of time slot assigned to STRB 15 8 STOP The location of stop bit of time slot assigned to STRB 31 16 Reserved 31 15 16 7 0 The location of START bit of time slot 15 8 The location of STOP bit of time slot 0 18 17 7 8 START 19 21 20 22 23 24 25 26 27 28 29 30 STOP Figure 9 22 IOM2 Strobe Register ...

Page 441: ... bits per sec to several Mbps This also supports multiple connections at the same time up to 127 physical devices including USB hub USB architecture can be used for real time data transfer such as audio and video with Isochronous transfer On the other hand asynchronous transfer type is supported over the same set of wires Other merits of USB architecture are listed below Wide range of packet size ...

Page 442: ...figuration Compatible with both OpenHCI and Intel UHCI Standards Support 5 Endpoints Control 2 Interrupt 2 Data Endpoints EP0 64 Bytes Control Status Endpoint EP1 2 32 Bytes Interrupt Endpoint In Out EP3 4 64 Bytes Data Endpoints In Out 32 64 Byte Data Endpoints support GDMA interface Supports Bulk Data Transfer CRC16 Generation and CRC5 CRC16 Checking Suspend Resume Control DISCONNECT state gener...

Page 443: ...ME GENERATION Frame divides time slot into 1ms units and the separators are SOFs Start of Frames Host broadcasts one SOF packet at a normal rate of once every 1 00ms 0 0005ms All ISO EPs in all devices can one IN OUT per 1ms time period The SOF packet consists of SYNC PID frame number CRC The host transmits the lower 11 bits of the current frame number in each SOF token transmission When requested...

Page 444: ...t The host and all functions must perform a complete decoding of all received PID fields Any PID received with a failed check field or which decodes to a non defined value is assumed to be corrupted and it as well as the remainder of the packet is ignored by the packet receiver If a function receives an otherwise valid PID for a transaction type or direction that it does not support the function m...

Page 445: ...ing with the Sync Pattern and throughout the entire transmission The data one that ends the Sync Pattern is counted as the first one in a sequence Bit stuffing by the transmitter is always enforced without exception If required by the bit stuffing rules a zero bit will be inserted even if it is the last bit before the end of packet EOP signal 10 3 5 BULK TRANSACTIONS The bulk transfer type is desi...

Page 446: ... the requester with the following Guaranteed access to USB bandwidth with bounded latency Guaranteed constant data rate through the pipe as long as data is provided to the pipe In the case of a delivery failure due to error no retrying of the attempt to deliver the data While the USB isochronous transfer type is designed to support isochronous sources and destinations it is not required that softw...

Page 447: ...I F APB BUS 32 Endpoint 0 FIFO Endpoint 1 FIFO Endpoint 2 FIFO Endpoint 3 FIFO Endpoint 4 FIFO General Function Interface Special Registers SIE 32 32 8 D out D out D in D in rxd Figure 10 4 USB Core Block Diagram 10 4 2 SIE SERIAL INTERFACE ENGINE BLOCK The SIE is the front end of this hardware and handles most of the protocol described in chapter 8 of the USB specification The SIE typically compr...

Page 448: ..._detect VPIN VMIN fun_dpll dpll_rxd rxd fun_eop_detect VPIN VMIN XRXD syn_VPIN rxd fun_pid_dec shiftreg_out 7 0 fun_shiftreg nrzi_dec_out dpll_rxd tx_mux_out 7 0 shiftreg_out 7 0 fun_bit_stuff VPOUT VMOUT data_in fun_tx_mux tx_mux_out 7 0 tx_buf_out 7 0 RX_DATA 7 0 TX_DATA Figure 10 5 SIE Block Diagram ...

Page 449: ...t 3 common status register 0x00000401 USBEP4CSR 0xF00E0028 R W USB endpoint 4 common status register 0x00000401 0xF00E002C Reserved USBWCEP0 0xF00E0030 R W USB write count register for endpoint 0 0x00000000 USBWCEP1 0xF00E0034 R W USB write count register for endpoint 1 0x00000000 USBWCEP2 0xF00E0038 R W USB write count register for endpoint 2 0x00000000 USBWCEP3 0xF00E003C R W USB write count reg...

Page 450: ...Reset Value USBFA 0xF00E0000 R W USB function address register 0x00000000 Table 10 3 USBFA Register Description Bit Number Bit Name MCU USB Description 6 0 USB Function Address Field USBFAF R W R The MCU write the address to these bits 7 USB Address UPdate USBAUP S R C The MCU sets this bit whenever it updates the USB Function Address Field USBFAF in this register The USBFAF is used after the Stat...

Page 451: ...S3C2500B USB CONTROLLER 10 11 31 0 7 FAF 6 0 Function Address Field FAF 7 Address UPdate AUP 31 8 Reserved A U P 6 8 Figure 10 6 USBFA Register ...

Page 452: ...gnaling The MCU reads USB Interrupt Register for the USB Resume Interrupt 2 ResUme RU R W R The MCU sets this bit for a duration of 10ms maximum of 15ms to initiate a resume signaling The USB generates resume signaling while this bit is set in suspend mode 3 ReSeT RST R S The USB set this bit if reset signaling is received from the host This bit remains set as long as reset signaling persists on t...

Page 453: ...te 1 Resume signal generation in suspend state 3 ReSeT RST 0 Normal operation 1 Reset received state 4 Tx Data Swap TDS 0 Normal operation 1 Transmit data swap 5 Rx Data Swap RDS 0 Normal operation 1 Receive data swap 6 Reserved 7 ISO Update ISOU 0 ISO data updated zero data packet send 1 ISO data updated 31 8 Reserved S U S E R S T I S O U S U S M R U T D S R D S 4 6 8 5 Figure 10 7 USBPM Registe...

Page 454: ...t number All interrupts corresponding to endpoints whose direction is programmable Mode IN OUT are mapped to this register This register maintains interrupt status of bus signaling condition viz Suspend Resume Reset Disconnect Table 10 6 USBINTR Register Register Address R W Description Reset Value USBINTR 0xF00E0008 R W USB interrupt register 0x00000000 ...

Page 455: ...et NOTE conditions 1 and 2 are mutually exclusive 7 5 Reserved 8 SUSpend Interrupt SUSI R C S The USB sets this bit when it receives suspend signaling This bit is set whenever there is no activity for 3ms on the bus Thus if the MCU does not stop the clock after the first suspend interrupt it will be continue to be interrupted every 3ms as long as there is no activity on the USB bus By default this...

Page 456: ...errupt EP4I 0 No EP4 interrupt 1 EP4 interrupt generated 7 5 Reserved 8 SUSpend Interrupt SUSI 0 No suspend interrupt 1 Suspend interrupt generated 9 RESume Interrupt RESI 0 No resume interrupt 1 Resume interrupt generated 10 ReSeT Interrupt RSTI 0 No reset interrupt 1 Reset interrupt generated 11 DISConnect Interrput DISCI 0 No interrupt 1 Interrupt generated after disconnect operation 31 12 Rese...

Page 457: ...CU USB Description 4 0 EP0 Interrupt ENable EP4 Interrupt ENable EP0IEN EP4IEN R W R If bit 0 the corresponding interrupt is disabled If bit 1 the corresponding interrupt is enabled 7 5 Reserved 8 SUSpend Interrupt ENable SUSIEN R W R If bit 0 the corresponding interrupt is disabled If bit 1 the corresponding interrupt is enabled 9 Reserved 10 ReSeT Interrupt ENable RSTIEN R W R If bit 0 the corre...

Page 458: ...nterrupt disable 1 Endpoint 3 interrupt enable 4 EndPoint 4 Interrupt ENable EP4IEN 0 Endpoint 4 interrupt disable 1 Endpoint 4 interrupt enable 7 5 Reserved 8 SUSpend Interrupt ENable SUSIEN 0 Suspend interrupt disable 1 Suspend interrupt enable 9 Reserved 10 ReSeT Interrupt ENable RSTIEN 0 Reset interrupt disable 1 Reset interrupt enable 11 DISConnect Interrupt ENable DISCIEN 0 Disconnect interr...

Page 459: ...1bits Table 10 10 USBFN Register Register Address R W Description Reset Value USBFN 0xF00E0010 R USB Frame Number register 0x00000000 Table 10 11 USBFN Register Descriptions Bit Number Bit Name MCU USB Description 10 0 Frame Number FN R W Frame Number from SOF packet 31 11 Reserved 31 0 10 10 0 Frame Number FN 31 11 Reserved 11 FN Figure 10 10 USBFN Register ...

Page 460: ...w CNTVLE Table Table 10 12 CNTVLE Table 22 21 2 1 0 Disconnect Time 2 CNTVLE 7 20 8333ns X X X X X 1 02 67 µs X X X X 1 0 05 33 µs X X X 1 0 0 10 67 µs X 1 0 0 0 0 05 59 s 1 0 0 0 0 0 11 18 s NOTE X means don t care Table 10 13 USBDISCONN Register Register Address R W Description Reset Value USBDISCONN 0xF00E0014 R W USB DISCONNect register 0x00000001 Table 10 14 USBDISCONN Register Description Bi...

Page 461: ...LER 10 21 31 0 22 22 0 CouNT VaLuE CNTVLE 23 30 Reserved 31 DISconnet operation STaRT DISSTRT 0 No operation 1 Both D D go to 0 and all USB registers R W blocked CNTVLE D I S S T R T 30 21 Figure 10 11 USBDISCONN Register ...

Page 462: ...en MAXPsize is 56 bytes If MAXP 3 0 is 1000 then MAXPsize is 64 bytes 6 4 Reserved 7 MAXP size SETtable MAXPSET W 0 USBEP0CSR 3 0 isn t overwritten when MCU writes a 32bit value to USBEP0CSR register 1 USBEP0CSR 3 0 is overwritten 23 8 Reserved 24 Out packet ReaDY ORDY R S This is a Read Only bit The USB sets this bit once a valid token is written to the FIFO An interrupt is generated when the USB...

Page 463: ... DEND is set The MCU clears this bit by writing a 1 to the SVSET bit When the USB sets this bit an interrupt is generated to the MCU When such a condition occurs the USB flushes the FIFO and invalidates MCU access to the FIFO When MCU access to the FIFO is invalidated this bit is cleared 29 SenD STALL SDSTALL S Clear The MCU writes a 1 to this bit at the same time it clears ORDY if it decodes a in...

Page 464: ... to EP0 FIFO completed 26 SenT STALL STSTALL 0 No stall token is transmitted 1 Control transaction is ended due to a protocol violation 27 Data END DEND 0 Not dataend stage 1 Dataend stage 28 SETup END SETEND 0 Normal operation state 1 Setup end stage 29 SenD STALL SDSTALL 0 Normal operation state 1 Go to stall token transmt state 30 SerViced Out ReaDY SVORDY 0 No operation 1 ORDY bit clear 31 Ser...

Page 465: ...2 0 is 100 then MAXPsize is 32 bytes 6 3 Reserved 7 MAXP size SET table MAXPSET W 0 USBEP1CSR 2 0 isn t overwritten when MCU writes a 32bit value to USBEP1CSR register 1 USBEP1CSR 2 0 is overwritten 8 Out mode ISO mode OISO R W This bit is valid only when endpoint 1 is set to OUT 0 Endpoint 1 will be Bulk mode 1 Endpoint 1 will be ISO mode Default 0 9 Out mode AuTo CLeaR OATCLR R W R This bit is v...

Page 466: ...the MCU reads the FIFO for the entire packet this bit should be cleared by MCU 17 Out mode Fifo FULL OFFULL R R W This bit is valid only when endpoint 1 is set to OUT Indicates no more packets can be accepted if USBEP1CSR 17 16 is 00 No packet in FIFO 01 1 packet in FIFO 11 2 packet of MAXP 1 2 FIFO size or 1 packet of MAXP FIFO size 18 Out mode fifo OVER run OOVER R R W This bit is valid only whe...

Page 467: ...ndshake to the host if it sends more than MAXP data for the OUT token 23 Out mode CLear data TOGgle OCLTOG R S This bit is valid only when endpoint 1 is set to OUT When the MCU writes a 1 to this bit the data toggle sequence bit is reset to DATA0 24 In mode IN packet ReaDY IINRDY R S C This bit is valid only when endpoint 1 is set to IN The MCU sets this bit after writing a packet of data into the...

Page 468: ...ntil the transmission is complete before the FIFO is flushed If two packets are loaded into the FIFO only the top most packet one that was intended to be sent to the host is flushed and the corresponding IINRDY bit for that packet is cleared 28 In mode SenD STALL ISDSTALL R W R This bit is valid only when endpoint 1 is set to IN The MCU writes a 1 to this register to issue a STALL handshake to the...

Page 469: ...L T O G O O R D Y O F F U L L O O V E R O D E R R O F F L U S H O S D S T A L L O S T S T A L L O C L T O G 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C S R 2 S E T I A T S E T I I S O M O D E O A T C L R O I S O M A X P S E T M A X P 15 12 11 10 9 8 7 19 OUT Data ERRor ODERR 0 Normal operation 1 Data error ISO 20 OUT Fifo FLUSH OFFLUSH 0 No operation 1 FIFO flush 21 OUT SenD STALL OSDSTALL 0 No...

Page 470: ...0 is 100 then MAXPsize is 32 bytes 6 3 Reserved 7 MAXP size SETtable MAXPSET W 0 USBEP2CSR 2 0 isn t overwritten when MCU writes a 32 bit value to USBEP2CSR register 1 USBEP2CSR 2 0 is overwritten 8 Out mode ISO mode OISO R W This bit is valid only when endpoint 2 is set to OUT 0 Endpoint 1 will be Bulk mode 1 Endpoint 1 will be ISO mode Default 0 9 Out mode AuTo CLeaR OATCLR R W R This bit is val...

Page 471: ...e the MCU reads the FIFO for the entire packet this bit should be cleared by MCU 17 Out mode Fifo FULL OFFULL R R W This bit is valid only when endpoint 2 is set to OUT Indicates no more packets can be accepted if USBEP2CSR 17 16 is 00 No packet in FIFO 01 1 packet in FIFO 11 2 packet of MAXP 1 2 FIFO size or 1 packet of MAXP FIFO size 18 Out mode fifo OVER run OOVER R R W This bit is valid only w...

Page 472: ... set to OUT When the MCU writes a 1 to this bit the data toggle sequence bit is reset to DATA0 24 In mode IN packet ReaDY IINRDY R S C This bit is valid only when endpoint 2 is set to IN The MCU sets this bit after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU c...

Page 473: ...e sent to the host is flushed and the corresponding IINRDY bit for that packet is cleared 28 In mode SenD STALL ISDSTALL R W R This bit is valid only when endpoint 2 is set to IN The MCU writes a 1 to this register to issue a STALL handshake to the USB The MCU clears this bit to end the STALL condition 29 In mode SenT STALL ISTSTALL R C S This bit is valid only when endpoint 2 is set to IN The USB...

Page 474: ...L T O G O O R D Y O F F U L L O O V E R O D E R R O F F L U S H O S D S T A L L O S T S T A L L O C L T O G 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C S R 2 S E T I A T S E T I I S O M O D E O A T C L R O I S O M A X P S E T M A X P 15 12 11 10 9 8 7 19 OUT Data ERRor ODERR 0 Normal operation 1 Data error ISO 20 OUT Fifo FLUSH OFFLUSH 0 No operation 1 FIFO flush 21 OUT SenD STALL OSDSTALL 0 No...

Page 475: ...3 0 is 0110 then MAXPsize is 48 bytes If MAXP 3 0 is 0111 then MAXPsize is 56 bytes If MAXP 3 0 is 1000 then MAXPsize is 64 bytes 6 4 Reserved 7 MAXP size SETtable MAXPSET W 0 USBEP3CSR 3 0 isn t overwritten when MCU writes a 32bit value to USBEP3CSR register 1 USBEP3CSR 3 0 is overwritten 8 Out mode ISO mode OISO R W This bit is valid only when endpoint 3 is set to OUT 0 Endpoint 1 will be Bulk m...

Page 476: ...e the MCU reads the FIFO for the entire packet this bit should be cleared by MCU 17 Out mode Fifo FULL OFFULL R R W This bit is valid only when endpoint 3 is set to OUT Indicates no more packets can be accepted if USBEP3CSR 17 16 is 00 No packet in FIFO 01 1 packet in FIFO 11 2 packet of MAXP 1 2 FIFO size or 1 packet of MAXP FIFO size 18 Out mode fifo OVER run OOVER R R W This bit is valid only w...

Page 477: ... set to OUT When the MCU writes a 1 to this bit the data toggle sequence bit is reset to DATA0 24 In mode IN packet ReaDY IINRDY R S C This bit is valid only when endpoint 3 is set to IN The MCU sets this bit after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU c...

Page 478: ...e sent to the host is flushed and the corresponding IINRDY bit for that packet is cleared 28 In mode SenD STALL ISDSTALL R W R This bit is valid only when endpoint 3 is set to IN The MCU writes a 1 to this register to issue a STALL handshake to the USB The MCU clears this bit to end the STALL condition 29 In mode SenT STALL ISTSTALL R C S This bit is valid only when endpoint 3 is set to IN The USB...

Page 479: ...L T O G O O R D Y O F F U L L O O V E R O D E R R O F F L U S H O S D S T A L L O S T S T A L L O C L T O G 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C S R 2 S E T I A T S E T I I S O M O D E O A T C L R O I S O M A X P S E T M A X P 15 12 11 10 9 8 7 19 OUT Data ERRor ODERR 0 Normal operation 1 Data error ISO 20 OUT Fifo FLUSH OFFLUSH 0 No operation 1 FIFO flush 21 OUT SenD STALL OSDSTALL 0 No...

Page 480: ...3 0 is 0110 then MAXPsize is 48 bytes If MAXP 3 0 is 0111 then MAXPsize is 56 bytes If MAXP 3 0 is 1000 then MAXPsize is 64 bytes 6 4 Reserved 7 MAXP size SETtable MAXPSET W 0 USBEP4CSR 3 0 isn t overwritten when MCU writes a 32bit value to USBEP4CSR register 1 USBEP4CSR 3 0 is overwritten 8 Out mode ISO mode OISO R W This bit is valid only when endpoint 4 is set to OUT 0 Endpoint 1 will be Bulk m...

Page 481: ... W This bit is valid only when endpoint 4 is set to OUT Indicates no more packets can be accepted if USBEP4CSR 17 16 is 00 No packet in FIFO 01 1 packet in FIFO 11 2 packet of MAXP 1 2 FIFO size or 1 packet of MAXP FIFO size 18 Out mode fifo OVER run OOVER R R W This bit is valid only when endpoint 4 is set to OUT ISO This bit is set if the core is not able to load an OUT ISO packet into the FIFO ...

Page 482: ...et ReaDY IINRDY R S C This bit is valid only when endpoint 4 is set to IN The MCU sets this bit after writing a packet of data into the FIFO The USB clears this bit once the packet has been successfully sent to the host An interrupt is generated when the USB clears this bit so the MCU can load the next packet While this bit is set the MCU will not be able to write to the FIFO If the SEND STALL bit...

Page 483: ...e sent to the host is flushed and the corresponding IINRDY bit for that packet is cleared 28 In mode SenD STALL ISDSTALL R W R This bit is valid only when endpoint 4 is set to IN The MCU writes a 1 to this register to issue a STALL handshake to the USB The MCU clears this bit to end the STALL condition 29 In mode SenT STALL ISTSTALL R C S This bit is valid only when endpoint 4 is set to IN The USB...

Page 484: ...L T O G O O R D Y O F F U L L O O V E R O D E R R O F F L U S H O S D S T A L L O S T S T A L L O C L T O G 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 C S R 2 S E T I A T S E T I I S O M O D E O A T C L R O I S O M A X P S E T M A X P 15 12 11 10 9 8 7 19 OUT Data ERRor ODERR 0 Normal operation 1 Data error ISO 20 OUT Fifo FLUSH OFFLUSH 0 No operation 1 FIFO flush 21 OUT SenD STALL OSDSTALL 0 No...

Page 485: ...ed into FIFO then write data into FIFO Table 10 25 USBWCEP0 Register Register Address R W Description Reset Value USBWCEP0 0xF00E0030 R W USB Write Count for Endpoint 0 Register 0x00000000 Table 10 26 USBWCEP0 Register Description Bit Number Bit Name MCU USB Description 6 0 CPU WRiTe CouNT CPUWRTCNT R W R the byte count number of data to be loaded into FIFO 15 7 Reserved 22 16 WRiTe CouNT WRTCNT R...

Page 486: ...USB CONTROLLER S3C2500B 10 46 31 22 0 6 6 0 ep0 CPU WRiTe CouNT CPUWRTCNT 15 7 Reserved 22 16 ep0 WRiTe CouNT WRTCNT 31 23 Reserved 16 15 23 7 WRTCNT CPUWRTCNT Figure 10 17 USBWCEP0 Register ...

Page 487: ...ed into FIFO then write data into FIFO Table 10 27 USBWCEP1 Register Register Address R W Description Reset Value USBWCEP1 0xF00E0034 R W USB Write Count for Endpoint 1 Register 0x00000000 Table 10 28 USBWCEP1 Register Description Bit Number Bit Name MCU USB Description 5 0 CPU WRiTe CouNT CPUWRTCNT R W R the byte count number of data to be loaded into FIFO 15 6 Reserved 21 16 WRiTe CouNT WRTCNT R...

Page 488: ...USB CONTROLLER S3C2500B 10 48 31 21 0 5 5 0 ep1 CPU WRiTe CouNT CPUWRTCNT 15 6 Reserved 21 16 ep1 WRiTe CouNT WRTCNT 31 22 Reserved 16 WRTCNT CPUWRTCNT 22 15 6 Figure 10 18 USBWCEP1 Register ...

Page 489: ...ed into FIFO then write data into FIFO Table 10 29 USBWCEP2 Register Register Address R W Description Reset Value USBWCEP2 0xF00E0038 R W USB Write Count for Endpoint 2 Register 0x00000000 Table 10 30 USBWCEP2 Register Description Bit Number Bit Name MCU USB Description 5 0 CPU WRiTe CouNT CPUWRTCNT R W R the byte count number of data to be loaded into FIFO 15 7 Reserved 21 16 WRiTe CouNT WRTCNT R...

Page 490: ...USB CONTROLLER S3C2500B 10 50 31 0 5 5 0 ep2 CPU WRiTe CouNT CPUWRTCNT 15 6 Reserved 21 16 ep2 WRiTe CouNT WRTCNT 31 22 Reserved 16 21 WRTCNT CPUWRTCNT 22 15 6 Figure 10 19 USBWCEP2 Register ...

Page 491: ...be loaded into FIFO then write data into FIFO Table 10 31 USBWCEP3 Register Register Address R W Description Reset Value USBWCEP3 0xF00E003C R W USB Write Count for Endpoint 3 Register 0x00000000 Table 10 32 USBWCEP3 Register Description Bit Number Bit Name MCU USB Description 6 0 CPU WRiTe CouNT CPUWRTCNT R W R the byte count number of data to be loaded into FIFO 15 7 Reserved 22 16 WRiTe CouNT W...

Page 492: ...USB CONTROLLER S3C2500B 10 52 31 0 6 6 0 ep3 CPU WRiTe CouNT CPUWRTCNT 15 7 Reserved 22 16 ep3 WRiTe CouNT WRTCNT 31 23 Reserved 16 22 WRTCNT CPUWRTCNT 23 15 7 Figure 10 20 USBWCEP3 Register ...

Page 493: ...be loaded into FIFO then write data into FIFO Table 10 33 USBWCEP4 Register Register Address R W Description Reset Value USBWCEP4 0xF00E0040 R W USB Write Count for Endpoint 4 Register 0x00000000 Table 10 34 USBWCEP4 Register Description Bit Number Bit Name MCU USB Description 6 0 CPU WRiTe CouNT CPUWRTCNT R W R the byte count number of data to be loaded into FIFO 15 7 Reserved 22 16 WRiTe CouNT W...

Page 494: ...USB CONTROLLER S3C2500B 10 54 31 22 0 6 6 0 ep4 CPU WRiTe CouNT CPUWRTCNT 15 7 Reserved 22 16 ep4 WRiTe CouNT WRTCNT 31 23 Reserved 16 WRTCNT CPUWRTCNT 23 15 7 Figure 10 21 USBWCEP4 Register ...

Page 495: ... must use these registers Table 10 35 USBEP0 1 2 3 4 Descriptions Register Address R W Description Reset Value USBEP0 USBEP1 USBEP2 USBEP3 USBEP4 0xF00E0080 0xF00E0084 0xF00E0088 0xF00E008C 0xF00E0090 R W R W R W R W R W USB EP0 FIFO USB EP1 FIFO USB EP2 FIFO USB EP3 FIFO USB EP4 FIFO 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX 0xXXXXXXXX ...

Page 496: ...EP0 FIFO 31 0 EndPoint 0 data FIFO 0 31 EP1 FIFO 31 0 EndPoint 1 data FIFO 0 31 EP2 FIFO 31 0 EndPoint 2 data FIFO 0 31 EP3 FIFO 31 0 EndPoint 3 data FIFO 0 31 EP4 FIFO 31 0 EndPoint 4 data FIFO Figure 10 22 USBEP0 1 2 3 4 FIFO Registers ...

Page 497: ...S3C2500B two modes are supported ECB and CBC The X9 52 standard Triple Data Encryption Algorithm Modes of Operation describes seven different modes for using TDEA Those are TECB TDEA electronic codebook mode of operation TCBC TDEA cipher block chaining mode of operation TCBC I TDEA cipher block chaining mode of operation interleaved TCFB TDEA cipher feedback mode of operation TCFB P TDEA cipher fe...

Page 498: ...PW DATA key write sig IV indata register PWDATA PADDR PENABLE PSELx PWRITE PWDATA PRDATA Register dreg64 pbox sbox exp Status des_mode wr_indata in_mode sig outdata register left side data left side data left side data in_mode sig FSM state machine key2 key1 keygen FSM state machine key48 left side data right side data S Y S T E M B U S PR DATA DES 3DES Figure 11 1 DES 3DES Block Diagram ...

Page 499: ...DESKEY1R 0xF0090014 R W Key 1 right half 0x00000000 DESKEY2L 0xF0090018 R W Key 2 left half Key 2 is the security key for the 2 nd DES of 3DES 0x00000000 DESKEY2R 0xF009001C R W Key 2 right half 0x00000000 DESKEY3L 0xF0090020 R W Key 3 left half Key 3 is the security key for the 3 rd DES of 3DES in the encryption mode or 1 st DES of 3DES in the decryption mode 0x00000000 DESKEY3R 0xF0090024 R W Ke...

Page 500: ... Encryption Mode ECB or CBC 0 DES 3DES will be running ECB Electronic Code Book mode 1 DES 3DES will be running CBC Cipher Block Chaining mode 7 2word_req 0 DES 3DES engine generates Available DESINFIFO bit in the status register to 1 when DESINFIFO is vacant more than 4 words and Valid DESOUTFIFO bit in the status register to 1 when DESOUTFIFO has more than 4 words valid data 1 DES 3DES engine ge...

Page 501: ...cant all 10 Full DESOUTFIFO DESOUTFIFO has 8 words valid data CPU have to read data immediately 11 3 3 DES 3DES INTERRUPT ENABLE REGISTER Table 11 4 DES 3DES Interrupt Enable Register Description Bit Number Bit Name Description 0 Int Idle Interrupt enable register for DES 3DES engine operation 0 Disable 1 Interrupt signal is generated when the status register 0 Idle bit goes to high which means th...

Page 502: ...scription 33 64 Key 1 Right Half The right half of the Key1 should be stored to this register The 8 th bit of each byte is parity bit and it isn t used for encryption decryption If users need to byte swapped key value they can control it by using DESCON 12 If DESCON 12 is set byte swapped key is written to DESKEY1R Otherwise original key is written to DESKEY1R 11 3 6 DES 3DES KEY 2 LEFT RIGHT SIDE...

Page 503: ...2500B DES 3DES 11 7 If users need to byte swapped key value they can control it by using DESCON 12 If DESCON 12 is set byte swapped key is written to DESKEY2R Otherwise original key is written to DESKEY2R ...

Page 504: ...DESCON 12 is set byte swapped key is written to DESKEY3R Otherwise original key is written to DESKEY3R 11 3 8 DES 3DES IV LEFT RIGHT SIDE REGISTER Table 11 12 DES 3DES IV Left Side Register Description Bit Number Bit Name Description 1 32 IV Left Half IV is only used for the CBC mode The left half of the 1 st IV should be stored in this register The IV for the next block is updated in this registe...

Page 505: ...ng DESCON 10 If DESCON 10 is set the written data to the DESINFIFO is automatically byte swapped Otherwise the written data have the original byte order Table 11 15 DES 3DES Output Data FIFO Description Bit Number Bit Name Description 31 0 DESOUTFIFO This FIFO can be read by CPU or DMA depends on control register value This FIFO consists of 8 words If data are transferred by DMA the 4 word burst t...

Page 506: ...r data receiving which is controlled by DESCON 7 When the DESCON 7 is set to 0 the Valid DESOUTFIFO status means that DESOUTFIFO has at least 4 word Valid data It is recommended when DMA mode is selected When the DESCON 7 is set to 1 the valid DESOUTFIFO status means that DESOUTFIFO has at least 2 word Valid data It is recommended when CPU mode is selected When the Available DESINFIFO or valid DES...

Page 507: ...n DES engine consumes fixed cycle per block 25 cycles for DES and 65 cycles for 3DES If the DES operating frequency is 133MHz and the DES has one block to be encrypted the DES performance is 341 Mbps for DES or 131 Mbps for 3DES For more real system condition the user have to consider how many cycles is needed for external memory access The memory access cycle should be included the performance ca...

Page 508: ...ion has been completed by software polling and or when it receives an appropriate internally generated GDMA interrupt The S3C2500B GDMA controller can increment or decrement source destination addresses and conduct 8 bit byte 16 bit half word or 32 bit word data transfer The GDMA does not check the cache coherency So software must ensure that source and destination addresses must be configured as ...

Page 509: ...MA_Req2 DES HUART0 xGDMA_Req3 DES HUART1 xGDMA_Req0 DES HUART1 xGDMA_Req1 DES HUART1 Mode Selection Mode Selection GDMA Channel 1 GDMA_Req GDMA_Ack GDMA Channel 2 GDMA_Req GDMA_Ack GDMA Channel 3 GDMA_Req GDMA_Ack GDMA Channel 4 GDMA_Req GDMA_Ack GDMA Channel 5 GDMA_Req GDMA_Ack GDMA Channel 0 GDMA_Req GDMA_Ack xGDMA_Ack1 xGDMA_Ack2 xGDMA_Ack3 IOPCON1 19 IOPCON1 20 IOPCON1 21 Figure 12 1 GDMA Cont...

Page 510: ...annel 2 control register GDMA channel 2 source address register GDMA channel 2 destination address register GDMA channel 2 transfer count register GDMA channel 2 run enable register GDMA channel 2 interrupt pending register 0 00000000 0x00000000 0x00000000 0x00000000 0x00000000 0x00000000 DCON3 DSAR3 DDAR3 DTCR3 DRER3 DIPR3 0xF0050060 0xF0050064 0xF0050068 0xF005006C 0xF0050070 0xF0050074 R W R W ...

Page 511: ...n DPRIC 0x1 and the DPRIF has the reset value For example DPRIC 0x1 and the DPRIF is 0x00431520 the fixed priority order from the highest to the lowest is GDMA channel 0 channel 2 channel 5 channel 1 channel 3 and channel 4 If the GDMA priority configuration register 0xF0051000 DPRIC 0x0 the programmable round robin priority is run by DPRIR register All GDMA channels own their respective field pos...

Page 512: ...el 3 3 DPRIR 15 12 channel 4 4 DPRIR 19 16 channel 5 5 DPRIR 23 20 DPRIF 16 15 12 11 8 7 4 3 0 19 20 23 24 31 dprif0 dprif1 dprif2 dprif3 dprif4 dprif5 Reserved DPRIR 16 15 12 11 8 7 4 3 0 19 20 23 24 31 dprir0 dprir1 dprir2 dprir3 dprir4 dprir5 Reserved 0 Priority configuration 0 Round robin 1 Fixed priority DPRIC 0 31 x 1 Figure 12 2 GDMA Programmable Priority Registers ...

Page 513: ...DMA 2 1 3 GDMA 2 1 6 4 0 Not used 0 GDMA 0 1 6 5 0 Not used 0 GDMA 0 1 6 6 0 Not used 0 GDMA 0 1 6 When DPRIR is 0x0 and only GDMA channel 0 1 and 2 are used the expected bus occupancy for each channel is 1 3 However S3C2500B does not work in that way instead GDMA channel 0 gets 4 6 of the bus occupancy GDMA 1 1 6 and GDMA 2 1 6 In short GDMA 0 is run four times more than GDMA 1 and 2 This is beca...

Page 514: ...oblem Solving by Method 1 Writing 0x000330 instead of 0x0 will give each channel of three GDMA with the same amount of bus occupancy 2 Method 2 DPRIR Channel Expected Bus Occupancy Real System Bus Occupancy DPRIR Channel Occupancy 0 GDMA 0 1 3 4 6 0 GDMA 0 1 3 0 GDMA 1 1 3 1 6 0 0 0 GDMA 2 1 3 1 6 0 GDMA 2 1 3 0 0 0 0 0 0 0 0 0 GDMA 4 1 3 0 0 0 0 0 Problem Problem Solving by Method 2 With leaving ...

Page 515: ...hod 2 0 3 or 1 4 or 2 5 3 Method 2 0 2 4 or 1 3 5 4 Method 1 N A 5 Method 1 N A 6 Method 2 1 2 3 4 5 and 6 This method works when 1 2 4 or 6 GDMA channels are needed but there is no solution when 4 or 5 GDMA channels are needed So we recommend that when you need 1 2 3 or 6 GDMA channels use Method 2 and when you need 4 or 5 GDMA channels use Method 1 ...

Page 516: ...rom memory 010 4 HUART RX mode HUART to memory 011 5 DES IN mode DES from memory 100 6 DES OUT mode DES to memory 101 4 Single Block mode This bit determines the number of external GDMA requests xGDMA_Req 0 3 that are required for a GDMA operation In Single mode when 4 0 the S3C2500B requires an external GDMA request for every GDMA operation In Block mode when 4 1 the S3C2500B requires only one ex...

Page 517: ...n You use this fixed feature when transferring data from multiple sources to a single destination When DCON MODE 3 1 is HUART TX mode HUART from memory 010 or DES IN mode DES from memory 100 these bits don t care 12 Interrupt enable If the interrupt enable bit is 1 a GDMA interrupt is generated when GDMA operation completes successfully If this bit is 0 the GDMA interrupt is not generated If you s...

Page 518: ...urce address direction SD 00 Increase source address 01 Decrease source address 10 Do not change source address fixed 11 Reserved 11 10 Destination address direction DD 00 Increase destination address 01 Decrease destination address 10 Do not change destination address fixed 11 Reserved 12 Interrupt enable IE 0 Do not generate a interrupt when GDMA completes 1 Generate a interrupt when GDMA comple...

Page 519: ... DDAR0 1 2 3 4 5 Registers Registers Address R W Description Reset Value DSAR0 0xF0050004 R W GDMA channel 0 source address register 0x00000000 DSAR1 0xF0050024 R W GDMA channel 1 source address register 0x00000000 DSAR2 0xF0050044 R W GDMA channel 2 source address register 0x00000000 DSAR3 0xF0050064 R W GDMA channel 3 source address register 0x00000000 DSAR4 0xF0050084 R W GDMA channel 4 source ...

Page 520: ...ansfer count register is not a multiple of 4 times transfer size the last misaligned data can be transferred by one transfer size Table 12 6 DTCR0 1 2 3 4 5 Registers Registers Address R W Description Reset Value DTCR0 0xF005000C R W GDMA channel 0 transfer count register 0x00000000 DTCR1 0xF005002C R W GDMA channel 1 transfer count register 0x00000000 DTCR2 0xF005004C R W GDMA channel 2 transfer ...

Page 521: ...escription Reset Value DRER0 0xF0050010 W GDMA channel 0 run enable register 0xXXXXXXX0 DRER1 0xF0050030 W GDMA channel 1 run enable register 0xXXXXXXX0 DRER2 0xF0050050 W GDMA channel 2 run enable register 0xXXXXXXX0 DRER3 0xF0050070 W GDMA channel 3 run enable register 0xXXXXXXX0 DRER4 0xF0050090 W GDMA channel 4 run enable register 0xXXXXXXX0 DRER5 0xF00500B0 W GDMA channel 5 run enable registe...

Page 522: ... beginning of the GDMA interrupt service routine Table 12 8 DIPR0 1 2 3 Registers Registers Address R W Description Reset Value DIPR0 0xF0050014 R WC GDMA channel 0 interrupt pending register 0xXXXXXXX0 DIPR1 0xF0050034 R WC GDMA channel 1 interrupt pending register 0xXXXXXXX0 DIPR2 0xF0050054 R WC GDMA channel 2 interrupt pending register 0xXXXXXXX0 DIPR3 0xF0050074 R WC GDMA channel 3 interrupt ...

Page 523: ... first external GDMA request xGDMA_Req0 can be serviced by GDMA channel 0 and 4 The second external GDMA request xGDMA_Req1 can be serviced by GDMA channel 1 and 5 The third external GDMA request xGDMA_Req2 can be serviced by GDMA channel 2 The fourth external GDMA request xGDMA_Req3 can be serviced by GDMA channel 3 If the slow external devices need the GDMA service the slow external devices can ...

Page 524: ... either the DDAR register In DES OUT mode you don t need to care the source address direction SD 9 8 of DCON register either the DSAR register 12 5 GDMA FUNCTION DESCRIPTION The following sections provide a functional description of the GDMA controller operations 12 5 1 GDMA TRANSFERS The GDMA transfers data directly between a requester and a target The requester and target can be memory HUART0 HU...

Page 525: ... asserted after checking that xGDMA_Ack has been asserted xGDMA_Req xGDMA_Ack RD WR Cycle Figure 12 8 External GDMA Requests Single Mode 12 5 3 2 Block Mode The assertion of only one GDMA request xGDMA_Req or an internal request causes all of the data as specified by the control register settings to be transmitted in a single operation The GDMA transfer is completed when the transfer counter value...

Page 526: ...ich memory banks are selected The S3C2500B has the internal clock HCLK as the operating clock The clock frequency of HCLK is 133MHz Internal Clk HCLK xGDMA_Req xGDMA_Ack tXDAr Min 2 cycle tXDRs tXDRh tXDAf Programmable by DCON 16 13 tXDRs setup time tXDRh hold time tXDAr delay rising tXDAf delay falling 6 5 nsec worst best 0 nsec 7 982 nsec 3 103 nsec 8 002 nsec 2 703 nsec Figure 12 10 External GD...

Page 527: ...s to destination address Current xGDMA_Req signal is idle state deasserted when xGDMA_Ack siganl is idle state high Otherwise GDMA recognizes current xGDMA_Req signal as next one and transfers next data I recommand that xGDMA_Req signal is deasserted when xGDMA_Ack signal is active 2 is minimum two cycles 3 can be programmed by setting DCON 16 13 can be between 1 and 16 cycles HCLK xGDMA_Req Recom...

Page 528: ...e transferred by one transfer size HCLK xGDMA_Req Recommand deasserted time xGDMA_Ack Address Data DTCR N N 4 NOTE Address order is source address0 source address1 source address 2 source address3 destination address0 destination address1 destination address2 destination address3 and Data order is source data0 source data1 source data2 source data3 destination data0 destination data1 destination d...

Page 529: ...K xGDMA_Req Recommand deasserted time xGDMA_Ack Address Data NOTE is in the block mode GDMA starts to operate with first xGDMA_Req signal So in the ideal case GDMA does not care the number of xGDMA_Req signal pulse But I recommand that xGDMA_Req siganl is deasserted when xGDMA_Ack signal is active state SA0 DA0 SD0 DD0 SA1 DA1 SD1 DD1 Programmable by DCON 16 13 Programmable by DCON 16 13 a a Figur...

Page 530: ...ammable by DCON 16 13 a SA2 SA3 SA1 SA0 DA0 DA1 DA2 DA3 a SD2 SD3 SD1 SD0 DD0 DD1 DD2 DD3 Figure 12 14 Block and Four Data Burst Timing one data burst source address0 and source data0 destination address0 and destination data0 four data burst source address0 and source data0 source address1 and source data1 source address2 and source data2 source address3 and source data3 destination address0 and ...

Page 531: ...GDMA CONTROLLER S3C2500B 12 24 NOTES ...

Page 532: ...unit has a baud rate generator transmitter receiver and a control unit as shown in Figure 13 1 The baud rate generator can be driven by the internal system clock PCLK2 or by the external clock EXT_UCLK The transmitter and receiver blocks have independent data registers and shifters Transmit data is written first to the transmit data register From there it is copied to the transmit shifter and then...

Page 533: ...gister CUSTAT UART Interrupt Enable CUINT UART Control Register CUCON Transmit Shift Register Transmit Data Register CUTXBUF Receive Shift Register Receive Data Register CURXBUF IR RX Decoder CURXD 0 1 IR TX Encoder 0 1 Baud Rate Divisor Baud Rate Generator CUTXD Figure 13 1 Console UART Block Diagram ...

Page 534: ... W Console UART status register W 0x00060800 CUINT 0xF0060008 R W Console UART interrupt enable register W 0x00000000 CUTXBUF 0xF006000C W Console UART transmit data register B CURXBUF 0xF0060010 R Console UART receive data register B CUBRD 0xF0060014 R W Console UART baud rate divisor register H 0x0000 CUCHAR1 0xF0060018 R W Console UART control character register 1 W 0x00000000 CUCHAR2 0xF006001...

Page 535: ...eak SBR Set this bit to one to cause the Console UART to send a break If this bit value is zero a break does not send A break is defined as a continuous Low level signal on the transmit data output with the duration of more than one frame transmission time 5 Serial Clock Select SCSEL This select bit specifies the clock source 0 Internal PCLK2 1 External EXT_UCLK 6 Reserved 7 Loop back mode LOOPB S...

Page 536: ...in normal mode In IR receive mode the receiver must detect the 3 16 pulsed period to recognize a zero value in the receiver data register CURXBUF as the IR receive data When this bit is 0 normal Console UART mode is selected When it is 1 infra red TX RX mode is selected NOTE Changing this bit while transmitting cause one Tx data losing Because level of infra red frame start bit and idle state of n...

Page 537: ... Send Break SBR 0 Send normal TxData 1 Send break signal 5 Serial Clock Select SCSEL 0 Internal PCLK2 1 External EXT_UCLK 6 Reserved This bit should be cleared 7 Loopback mode LOOPB 0 Normal operating mode 1 Enable Loopback mode only for test 10 8 Parity mode PMD 0xx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 11 Stop Bits STB 0 1 stop bit...

Page 538: ... 15 14 10 24 21 18 17 16 13 12 11 8 7 6 E C H O S C S E L 28 15 Reserved This bit should be cleared 29 Software Flow Control Enable SFEN 0 Disable Software Flow Control 1 Enable Software Flow Control 30 Echo Test Enable ECHO 0 Disable Echo Test 1 Enable Echo Test 31 Reserved This bit should be cleared Figure 13 3 Console UART Control Register ...

Page 539: ... to indicate that a break signal has been received in CURXBUF If the BKD interrupt enable bit CUINT 1 is 1 a interrupt is generated when a break occurs You have to clear this bit by writing 1 to this bit If not UART may be stopped 2 Frame Error FER This bit is automatically set to 1 whenever a frame error occurs during a serial data receiving operation A frame error occurs when a zero is detected ...

Page 540: ...rated when a control character is detected You can clear this bit by writing 1 to this bit NOTE Software flow control mode does not affects Tx Rx operation this bit This bit informs only whether UART receives control character or not Namely if user want to stop Tx Rx operation User must program that routine 10 6 Reserved 11 Receiver in idle RXIDLE This bit is only for CPU to monitor the receiver s...

Page 541: ...or Receive FIFO top or CURXBUF 1 Overrun Error occured 5 Control Character Detect CCD 0 No Control Character Receive FIFO top or CURXBUF 1 Control character present Receive FIFO top or CURXBUF 10 6 Reserved 11 Receiver in IDLE IDLE 0 Receiver is in active state 1 Receiver is in IDLE state 16 12 Reserved 17 Transmitter Idle TI 0 Transmit is in progress 1 Transmitter is in idle no data for Tx 18 Tra...

Page 542: ...ART Interrupt Enable Register Description Bit Number Bit Name Description 0 RDVIE Receive Data Valid interrupt enable 1 BKDIE Break Signal Detected interrupt enable 2 FERIE Frame Error interrupt enable 3 PERIE Parity Error interrupt enable 4 OERIE Overrun Error interrupt enable 5 CCDIE Control Character Detect interrupt enable 16 6 Reserved 17 TIIE Transmitter Idle interrupt enable 18 THEIE Transm...

Page 543: ... Interrupt Enable PERIE 4 Overrun Error Interrupt Enable OERIE 5 Control Character Detect Interrupt Enable CCDIE 16 6 Reserved 17 Transmitter Idle TIIE 18 Transmit Holding Register Empty Interrupt Enable THEIE 31 19 Reserved C C D I E O E R I E T H E I E T I I E F E R I E R D V I E B K D I E P E R I E 31 0 3 4 5 1 2 19 18 17 16 6 Figure 13 5 Console UART Interrupt Enable Register ...

Page 544: ... data This field contains the data to be transmitted over the single channel Console UART When this register is written the transmit data register empty bit in the status register CUSTAT 18 should be 1 This is to prevent overwriting of transmit data that may already be present in the CUTXBUF Whenever the CUTXBUF is written with a new value the transmit register empty bit CUSTAT 18 is automatically...

Page 545: ... Receive data This field contains the data received over the single channel Console UART When the Console UART finishes receiving a data frame the receive data ready bit in the Console UART status register CUSTAT 0 should be 1 This prevents reading invalid receive data that may already be present in the CURXBUF Whenever the CURXBUF is read the receive data valid bit CUSTAT 0 is automatically clear...

Page 546: ...GOUT PCLK2 or EXT_UCLK CNT0 1 16CNT1 16 Table 13 12 CUBRD Registers Register Address R W Description Size Reset Value CUBRD 0xF0060014 R W Console UART baud rate divisor register H 0x0000 3 0 Baud rate divisor value CNT1 xxx0 Divide by 1 xxx1 Divide by 16 15 4 Time constant value for CNT0 31 15 16 0 18 17 19 21 20 22 23 24 25 26 27 28 29 30 CNT0 4 3 CNT1 Figure 13 8 Console UART Baud Rate Divisor ...

Page 547: ...RD 3 0 Select Clock CUCON 5 Figure 13 9 Console UART Baud Rate Generator BRG Table 13 13 Typical Baud Rates Examples of Console UART Baud Rates PCLK2 66 5 MHz EXT_UCLK 29 4912 MHz BRGOUT CNT0 DEC HEX CNT1 Freq Dev CNT0 DEC HEX CNT1 Freq Dev 1200 3463 D87 0 1199 84 0 01 1535 5FF 0 1200 00 0 00 2400 1731 6C3 0 2399 68 0 01 767 2FF 0 2400 00 0 00 4800 865 361 0 4799 36 0 01 383 17F 0 4800 00 0 00 960...

Page 548: ...egister Address R W Description Size Reset Value CUCHAR1 0xF0060018 R W Console UART control character register 1 W 0x00000000 CUCHAR2 0xF006001C R W Console UART control character register 2 W 0x00000000 31 15 16 7 0 Control Character 0 15 8 Control Character 1 23 16 Control Character 2 31 24 Control Character 3 CHAR0 0 24 23 7 8 CHAR1 CHAR3 CHAR2 Figure 13 10 Console UART Control Character 1 Reg...

Page 549: ...E TRANSMIT CURXBUF INT_RXD CURXD INT_TXD THE CUTXD Parity Start Data Bits 5 8 Stop 1 2 Start Parity Data Bits 5 8 Stop 1 2 Start Start Data Bits Receive Data Receive Data Figure 13 12 Interrupt Based Serial I O Transmit and Receive Timing Diagram ...

Page 550: ... Start Bit Stop Bit Data Bits SIO Frame Figure 13 13 Serial I O Frame Timing Diagram Normal Console UART 0 1 0 1 0 0 1 1 0 1 Start Bit Stop Bit Data Bits IR Transmit Frame Bit frame T 3 16T 7 16T 6 16T Figure 13 14 Infra Red Transmit Mode Frame Timing Diagram ...

Page 551: ...SERIAL I O CONSOLE UART S3C2500B 13 20 0 1 0 1 0 0 1 1 0 1 Start Bit Stop Bit Data Bits IR Receive Frame Bit frame T 3 16T 13 16T Figure 13 15 Infra Red Receive Mode Frame Timing Diagram ...

Page 552: ...igure 14 1 The baud rate generator can be driven by the internal system clock divided by 2 PCLK2 or by the external clock EXT_UCLK Auto Baud Rate Generator tries to get the baud rate from input data in this mode The transmitter and receiver blocks have independent data buffer registers and data shifters And 32 byte transmit FIFO and 32 byte receive FIFO is also provided which include transmit and ...

Page 553: ...egister RxBuffer Register Receiver FIFO 32 Bytes IR Tx Encoder IR Rx Decoder 1 0 HUART TX pin HUART RX pin EXT_UCLK Baud Rate Divisor Transmit Data Receive Data Transmit Control Receive Control Receive Status Transmit Status Control Character Register PCLK2 HUCON UCLK HUCON IR S Y S T E M B U S 0 1 0 1 UART_CLK Receiver Shift Register Figure 14 1 High Speed UART Block Diagram ...

Page 554: ...070020 R W High Speed UART autobaud boundary register W 0x1F0F0703 HUABT 0xF0070024 R W High Speed UART autobaud table register W 0x170B0502 Table 14 2 High Speed UART 1 Special Registers Overview Register Address R W Description Size Reset Value HUCON 0xF0080000 R W High Speed UART control register W 0x00000000 HUSTAT 0xF0080004 R W High Speed UART status register W HUINT 0xF0080008 R W High Spee...

Page 555: ...ed High speed UART 0 can use only GDMA 0 1 2 channel and High speed UART 1 can use only GDMA 3 4 5 channel 4 Send Break SBR Set this bit to one to cause the High Speed UART to send a break If this bit value is zero a break does not send A break is defined as a continuous Low level signal on the transmit data output with the duration of more than one frame transmission time 5 Serial Clock Selection...

Page 556: ...ted NOTE Changing these bits while transmitting cause one Tx data losing Because level of infra red frame start bit and idle state of normal frame are identically high 15 Reserved This bit should be cleared by zero 16 Transmit FIFO enable TFEN S3C2500B High Speed UART block support 32 byte FIFO If this bit set to one transmit data moved to Tx FIFO and then sent 17 Receive FIFO enable RFEN S3C2500B...

Page 557: ...d UARTS pin goes Low level Otherwise it remains High level 27 26 Reserved This bit should be cleared by zero 28 Hardware Flow Control Enable HFEN This bit determines whether High Speed UART select hardware flow control or not If this bit set to one High Speed UART will control all pins concerning to hardware flow control 29 Software Flow Control Enable SFEN This bit determines whether High Speed U...

Page 558: ... Normal operating mode 1 Enable Loopback mode only for test 10 8 Parity mode PMD 0xx No parity 100 Odd parity 101 Even parity 110 Parity forced checked as 1 111 Parity forced checked as 0 11 Stop Bits STB 0 1 stop bit 1 2 stop bits 13 12 Word Length WL 00 5 bit 01 6 bit 10 7 bit 11 8 bit 14 Infra red mode IR 0 normal operating mode 1 Infra red Tx Rx mode 15 Reserved This bit should be cleared 31 0...

Page 559: ...Terminal Ready to pin DTR 0 UnDTR0 UnDTR1 goes high level 1 UnDTR0 UnDTR1 goes low level 25 Request To Send to pin RTS 0 UnRTS0 UnRTS1 goes high level 1 UnRTS0 UnRTS1 goes low level 27 26 Reserved This bit should be cleared 28 Hardware Flow Control Enable HFEN 0 Disable Hardware Flow Control 1 Enable Hardware Flow Control 29 Software Flow Control Enable SFEN 0 Disable Software Flow Control 1 Enabl...

Page 560: ...FIFO or HURXBUF NOTE Whether Receive FIFO top or HURXBUF depends on the HUCON 17 1 Break Signal Detected BKD This bit automatically set to one to indicate that a break signal has been received in Receive FIFO top or HURXBUF If the BKD interrupt enable bit HUINT 1 is 1 a interrupt is generated when a break occurs You have to clear this bit by writing 1 to this bit If not UART may be stopped 2 Frame...

Page 561: ...eiver checks a newly received data whether the data is good frame or not If the DCD interrupt enable bit HUINT 6 is 1 a interrupt is generated when a data carrier is detected This bit can be used for error check bit in hardware flow control mode 7 Receive FIFO Data trigger level reach RFREA In Receive FIFO mode this bit indicate Receive FIFO has valid data and reach Rx trigger level So High Speed ...

Page 562: ...ART When HUnCTS0 HUnCTS1 level is low this bit is set And HUnCTS0 HUnCTS1 high this bit is cleared 16 CTS Event occurred E_CTS This bit is set to 1 whenever HUnCTS0 HUnCTS1 level changed If the E_CTS interrupt enable bit HUINT 16 is 1 a interrupt is generated when a CTS event is occurred You can clear this bit by writing 1 to this bit 17 Transmitter Idle TI HUSTAT 17 is automatically set to 1 when...

Page 563: ...or HURXBUF 1 Overrun Error occured 5 Control Character Detect CCD 0 No Control Character Receive FIFO top or HURXBUF 1 Control character present Receive FIFO top or HURXBUF 6 Data Carrier Detect Lost DCDL 0 DCD pin is Low at the receiver checking time 1 DCD pin is High at the receiver checking time 7 Receive FIFO Data Trigger Level Reach RFREA 0 No valid data in HURXBUF or Not reached to trigger l...

Page 564: ...ansmitter Idle TI 0 Transmit is in progress 1 Transmitter is in idle no data for Tx 18 Transmit Holding Register Empty THE 0 TxFIFO at trigger level or tranmit holding register is not empty 1 In TxFIFO mode TxFIFO at trigger level is empty In non FIFO mode transmit holding register is empty 19 Transmit FIFO Empty TFEMT 0 Transmit FIFO is not empty 1 Transmit FIFO is empty 20 Transmit FIFO full TFF...

Page 565: ...ble 2 FERIE Frame Error interrupt enable 3 PERIE Parity Error interrupt enable 4 OERIE Overrun Error interrupt enable 5 CCDIE Control Character Detect interrupt enable 6 DCDLIE DCD High at receiver checking time interrupt enable 7 RFREAIE Receive FIFO Data trigger level reach interrupt enable 9 8 Reserved 10 OVFFIE Receive FIFO overrun interrupt enable 11 Reserved 12 E_RxTOIE Receive Event time ou...

Page 566: ...e OVFFIE 11 Reserved 12 Receive Event Time out Interrupt Enable E_RxTOIE 13 AutoBaud Rate Detection done interrupt enable AUBDDNIE 15 14 Reserved 16 CTS event occured Interrupt Enable E_CTSIE 17 Transmitter Idle TIIE 18 Transmit Holding Register Empty Interrupt Enable THEIE This bit used in FIFO mode for interrupt enable when transmit FIFO empty as much transmit data trigger level 31 19 Reserved 3...

Page 567: ...rs Registers Offset Address R W Description Reset Value HUTXBUF 0xF007000C 0xF008000C W High Speed UART transmit buffer register Table 14 10 High Speed UART Transmit Register Description Bit Number Bit Name Description 7 0 Transmit data This field contains the data to be transmitted over the single channel High Speed UART When this register is written the transmit buffer register empty bit in the ...

Page 568: ...s Offset Address R W Description Reset Value HURXBUF 0xF0070010 0xF0080010 R High Speed UART receive buffer register Table 14 12 High Speed UART Receive Register Description Bit Number Bit Name Description 7 0 Receive data This field contains the data received over the single channel High Speed UART When the High Speed UART finishes receiving a data frame the receive data ready bit in the High Spe...

Page 569: ...K2 or EXT_UCLK CNT0 1 16CNT1 16 Table 14 13 HUBRD0 and HUBRD0 Registers Registers Offset Address R W Description Reset Value HUBRD 0xF0070014 0xF0080014 R W High Speed UART baud rate divisor register 0x00 31 19 15 16 3 0 Baud reate divisor value CNT1 xxx0 divide by 1 xxx1 divide by 16 15 4 Time constant value for CNT0 CNT0 0 18 17 20 30 29 28 27 26 25 24 23 22 21 3 4 CNT1 Figure 14 7 High Speed UA...

Page 570: ...4 8 High Speed UART Baud Rate Generator BRG Table 14 14 Typical Baud Rates Examples of High Speed UART Baud Rates PCLK2 66 5 MHz EXT_UCLK 29 4912 MHz BRGOUT CNT0 DEC HEX CNT1 Freq Dev CNT0 DEC HEX CNT1 Freq Dev 1200 3463 D87 0 1199 84 0 01 1535 5FF 0 1200 00 0 00 2400 1731 6C3 0 2399 68 0 01 767 2FF 0 2400 00 0 00 4800 865 361 0 4799 36 0 01 383 17F 0 4800 00 0 00 9600 432 160 0 9598 73 0 01 191 B...

Page 571: ...character For example even if you want to use one control character all control characters will have same value with it Table 14 15 HUCHAR1 Registers Registers Offset Address R W Description Reset Value HUCHAR1 0xF0070018 0xF0080018 R W High Speed UART control character1 register 0x00 31 15 16 7 0 Control Character 0 15 8 Control Character 1 23 16 Control Character 2 31 24 Control Character 3 CONC...

Page 572: ...haracter For example even if you want to use one control character all control characters will have same value with it Table 14 16 HUCHAR2 Registers Registers Offset Address R W Description Reset Value HUCHAR2 0xF007001C 0xF008001C R W High Speed UART control character2 register 0x00 31 15 16 7 0 Control Character 4 15 8 Control Character 5 23 16 Control Character 6 31 24 Control Character 7 CONCH...

Page 573: ...the highest boundary value is ABT3 Refer figure 14 13 for detail range ABT3 ABB3 ABB1 ABT0 ABB0 ABT3 ABT0 Figure 14 11 AutoBaud Boundary Regsiter Range Table 14 17 HUABB Registers Registers Offset Address R W Description Reset Value HUABB 0xF0070020 0xF0080020 R W High Speed UART autobaud boundary register 0x1F0F0703 31 15 16 7 0 AutoBaud Boundary 0 15 8 AutoBaud Boundary 1 23 16 AutoBaud Boundary...

Page 574: ...is highest table value also ABT3 is highest boundary value of total range If out of range value is detected it will be written normally without modification If 0x1F was detected Rewrite 0x1F If 0x0B was detected If 0x04 was detected Rewrite 0x07 Rewrite 0x03 ABT3 0x1F ABB3 0x17 ABT2 0x0F ABB2 0x0B ABT1 0x07 ABB1 0x05 ABT0 0x03 ABB0 0x02 Figure 14 13 Example of AutoBaud Table Register Setting Table...

Page 575: ...ata on trigger level of TX FIFO High Speed UART generates interrupt INT_TXD or sends a request signal to GDMA During this operation trigger level should be 30 32 empty depth FIFO depth 24 32 16 32 or 8 32 CPU or GDMA fills data into TX FIFO by byte Rx FIFO Operation If received data are filled up to RX FIFO trigger level High Speed UART generate interrupt INT_RXD or send request signal to GDMA The...

Page 576: ... SPEED UART 14 25 Start Bit Data Size TXD RTS CTS Figure 14 15 When Signal is Asserted During Transmit Operation Start Bit Data Region TXD RTS CTS Stop Bit Figure 14 16 When CTS Signal is De asserted During Transmit Operation ...

Page 577: ...ed UART compares received data with control characters and if they are identical it sets 1 at state bit CCD HUSTAT 5 and generates interrupt which masked by Interrupt enable register 14 4 4 AUTO BAUD RATE DETECTION To use Auto Baud Rate Detection Set ABB AutoBaud rate Boundary ABT AutoBaud rate Table Register and Auto Baud Detect bit AUBD HUCON 6 When RXD level is low High Speed UART counts low le...

Page 578: ...E TRANSMIT HURXBUF INT_RXD RX DATA INT_TXD THE TX DATA Parity Start Data Bits 5 8 Stop 1 2 Start Parity Data Bits 5 8 Stop 1 2 Start Start Data Bits Receive Data Receive Data Figure 14 19 Interrupt Based Serial I O Transmit and Receive Timing Diagram ...

Page 579: ...rity Start Data Bits 5 8 Stop 1 2 Figure 14 20 DMA Based Serial I O Timing Diagram Tx Only RECEIVER HU_RXBUF uart_rx_req RX DATA Previous Receive Data Parity Data Bits 5 8 Stop 1 2 Start Start Data Bits Valid Receive Data RMODE Select DMA Mode uart_rx_ack Figure 14 21 DMA Based Serial I O Timing Diagram Rx Only ...

Page 580: ... Start Bit Stop Bit Data Bits SIO Frame Figure 14 22 Serial I O Frame Timing Diagram Normal High Speed UART 0 1 0 1 0 0 1 1 0 1 Start Bit Stop Bit Data Bits IR Transmit Frame Bit frame T 3 16T 7 16T 6 16T Figure 14 23 Infra Red Transmit Mode Frame Timing Diagram ...

Page 581: ...SERIAL I O HIGH SPEED UART S3C2500B 14 30 0 1 0 1 0 0 1 1 0 1 Start Bit Stop Bit Data Bits IR Transmit Frame Bit frame T 3 16T 13 16T Figure 14 24 Infra Red Receive Mode Frame Timing Diagram ...

Page 582: ...Output Mode If you select IOPCON1 14 for xGDMA Req 0 then the port is used for GDMA Req port mode I O port signal decision register IOPGDMA is used when IOPCON1 is selected for GDMA Req Ack IOPGDMA controls external GDMA Req Ack signals IOPEXTINTPND register is used for external interrupt status IOPEXTINTPND is set when external interrupt is generated and is cleared when IOPEXTINTPND register is r...

Page 583: ...ernal interrupt 0x00000000 IOPEXTINTPND 0xF0030018 R W I O port external Interrupt clear register 0x00000000 IOPDATA1 0xF003001C R W I O port data register Port 0 to 31 Undefined IOPDATA2 0xF0030020 R W I O port data register Port 32 to 63 Undefined IOPDRV1 0xF0030024 R W I O port drive control register Port 0 to 31 0x00000000 IOPDRV2 0xF0030028 R W I O port drive control register Port 32 to 63 0x...

Page 584: ...2 GPIO 21 GPIO 20 GPIO 19 GPIO 18 GPIO 17 GPIO 16 GPIO 15 GPIO 14 GPIO 13 GPIO 12 GPIO 11 GPIO 10 GPIO 9 GPIO 8 GPIO 7 GPIO 6 GPIO 5 GPIO 4 GPIO 3 GPIO 2 GPIO 1 GPIO 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 GPIO 63 GPIO 62 GPIO 61 GPIO 60 GPIO 59 GPIO 58 GPIO 57 GPIO 56 GPIO 55 GPIO 54 GPIO 53 GPIO 52 GPIO 51 GPIO 50 GPIO 49 GPIO 48 GPIO 47 GPIO 46 GPIO 45 GPIO 44 GPIO 43 ...

Page 585: ...hen port14 is used for GDMA Req port If you set the IOPGDMA 14 to 1 then port14 is used for GPIO NOTE If the port is used for a function s port such as an external interrupt request or an external GDMA Req Ack signal its signal function is determined by IOPGDMA or IOPEXTINT register Table 15 3 IOPCON1 2 Register Register Address R W Description Reset Value IOPCON1 0xF0030008 R W I O port function ...

Page 586: ... 3 GPIO 21 xGDMA Ack 2 GPIO 20 xGDMA Ack 1 GPIO 19 xGDMA Ack 0 GPIO 18 xGDMA Req 3 GPIO 17 xGDMA Req 2 GPIO 16 xGDMA Req 1 GPIO 15 xGDMA Req 0 GPIO 14 External Interrupt xINT 5 GPIO 13 External Interrupt xINT 4 GPIO 12 External Interrupt xINT 3 GPIO 11 External Interrupt xINT 2 GPIO 10 External Interrupt xINT 1 GPIO 9 External Interrupt xINT 0 GPIO 8 HUARTnDSR0 HUARTnDTR0 HUARTTXD0 HUARTRXD0 GPIO ...

Page 587: ...IO 42 High speed UART nDCD1 HUARTnDCD1 GPIO 41 High speed UART nCTS1 HUARTnCTS1 GPIO 40 High speed UART nRTS1 HUARTnRTS1 GPIO 39 High speed UART nDSR1 HUARTnDSR1 GPIO 38 High speed UART nDTR1 HUARTnDTR1 GPIO 37 High speed UART TXD1 HUARTTXD1 GPIO 36 High speed UART RXD1 HUARTRXD1 GPIO 35 High speed UART nDCD0 HUARTnDCD0 GPIO 34 High speed UART nCTS0 HUARTnCTS0 GPIO 33 High speed UART nRTS0 HUARTnR...

Page 588: ...rol external GDMA Acknowledge2 output for port 20 xGDMA_Ack2 10 0 active low 1 active high 9 Control external GDMA Acknowledge1 output for port 19 xGDMA_Ack1 9 0 active low 1 active high 8 Control external GDMA Acknowledge0 output for port 18 xGDMA_Ack0 8 0 active low 1 active high 7 6 Control external GDMA Request3 input for port 17 xGDMA_Req3 7 0 filtering off 1 filtering on 6 0 active low 1 act...

Page 589: ...t provides level or rising or falling edge detection If you set rising or falling edge detection rising or falling edge interrupt makes interrupt status high You can clear the interrupt by writing IOPEXTINTPND register to 1 If you set level detection then external interrupt level goes direct to interrupt controller External signals can be active high or low so you must set the active high or low b...

Page 590: ...ing edge detection 11 8 Control external interrupt request2 input for port 10 xINT2 11 0 active low 1 active high 10 0 filtering off 1 filtering on 9 8 00 level detection 01 rising edge detection 10 falling edge detection 7 4 Control external interrupt request1 input for port 9 xINT1 7 0 active low 1 active high 6 0 filtering off 1 filtering on 5 4 00 level detection 01 rising edge detection 10 fa...

Page 591: ...PEXTINTPND Register Register Address R W Description Reset Value IOPEXTINTPND 0xF0030018 R W I O port external interrupt clear register 0x00000000 NOTE IOPEXTINTPND is set when external interrupt is generated and is cleared by writing 1 to the appropriate bit of IOPEXTINTPND register 5 EXTINTCLR5 4 EXTINTCLR4 3 EXTINTCLR3 2 EXTINTCLR2 1 EXTINTCLR1 0 EXTINTCLR0 31 0 6 3 4 5 1 2 X X X X X X IOPEXTIN...

Page 592: ... R W I O port data register for port 32 to 63 Undefined 15 3 7 I O PORT DRIVE CONTROL REGISTER IOPDRV1 2 The I O port drive control registers IOPDRV1 2 control the pad type for which is operating as a tri state output mode or an open drain output mode This register s each bit value programmed as write 1 value for open drain output mode or write 0 value for tri state output mode Table 15 8 IOPDRV1 ...

Page 593: ...I O PORTS S3C2500B 15 12 NOTES ...

Page 594: ...tten to the pre defined interrupt priority register field to obtain that priority The interrupt priorities are pre defined from 0x0 to 0x26 Interrupt mode register INTMOD EXTMOD Defines the interrupt mode IRQ or FIQ for each interrupt source Interrupt mask register INTMASK EXTMASK Indicates that the current interrupt has been disabled if the corresponding mask bit is 1 If an interrupt mask bit is ...

Page 595: ...mer 0 interrupt 24 GDMA channel 5 interrupt 23 GDMA channel 4 interrupt 22 GDMA channel 3 interrupt 21 GDMA channel 2 interrupt 20 GDMA channel 1 interrupt 19 GDMA channel 0 interrupt 18 DES interrupt 17 Ethernet 1 RX interrupt 16 Ethernet 1 TX interrupt 15 Ethernet 0 RX interrupt 14 Ethernet 0 TX interrupt 13 HDLC 2 RX interrupt 12 HDLC 2 TX interrupt 11 HDLC 1 RX interrupt 10 HDLC 1 TX interrupt...

Page 596: ...l interrupt 0 16 4 INTERRUPT CONTROLLER SPECIAL REGISTERS 16 4 1 INTERRUPT MODE REGISTERS Bit settings in the interrupt mode registers INTMOD and EXTMOD specify if an interrupt is to be serviced as a fast interrupt FIQ or a normal interrupt IRQ Table 16 3 INTMOD EXTMOD Register Register Address R W Description Reset Value INTMOD 0xF0140000 R W Internal interrupt mode register 0x00000000 EXTMOD 0xF...

Page 597: ...imer 0 interrupt 24 GDMA channel 5 interrupt 23 GDMA channel 4 interrupt 22 GDMA channel 3 interrupt 21 GDMA channel 2 interrupt 20 GDMA channel 1 interrupt 19 GDMA channel 0 interrupt 18 DES interrupt 17 Ethernet 1 RX interrupt 16 Ethernet 1 TX interrupt 15 Ethernet 0 RX interrupt 14 Ethernet 0 TX interrupt 13 HDLC 2 RX interrupt 12 HDLC 2 TX interrupt 11 HDLC 1 RX interrupt 10 HDLC 1 TX interrup...

Page 598: ...errupt mode 1 FIQ interrupt mode 5 EXT 5 interrupt 4 EXT 4 interrupt 3 EXT 3 interrupt 2 EXT 2 interrupt 1 EXT 1 interrupt 0 EXT 0 interrupt 31 0 12 13 14 9 10 11 6 7 8 3 4 5 1 2 X X X X X X EXTMOD 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 X Figure 16 2 External Interrupt Mode Register EXTMOD 16 4 2 INTERRUPT MASK REGISTERS The interrupt mask registers INTMASK and EXTMASK contain interrupt m...

Page 599: ...t Timer 0 interrupt 24 GDMA channel 5 interrupt 23 GDMA channel 4 interrupt 22 GDMA channel 3 interrupt 21 GDMA channel 2 interrupt 20 GDMA channel 1 interrupt 19 GDMA channel 0 interrupt 18 DES interrupt 17 Ethernet 1 RX interrupt 16 Ethernet 1 TX interrupt 15 Ethernet 0 RX interrupt 14 Ethernet 0 TX interrupt 13 HDLC 2 RX interrupt 12 HDLC 2 TX interrupt 11 HDLC 1 RX interrupt 10 HDLC 1 TX inter...

Page 600: ...uest And if global mask bit bit 31 is 1 no interrupts include internal and external interrupts are serviced After the global mask bit is cleared the interrupt is serviced The 7 interrupt sources are mapped as follows 6 IOM2 interrupt 0 non Masking 1 Masking 5 EXT 5 interrupt 4 EXT 4 interrupt 3 EXT 3 interrupt 2 EXT 2 interrupt 1 EXT 1 interrupt 0 EXT 0 interrupt 31 Global interrupt mask bit 0 Ena...

Page 601: ...ster 4 0x13121110 INTPRIOR5 0xF0140034 R W Interrupt priority register 5 0x17161514 INTPRIOR6 0xF0140038 R W Interrupt priority register 6 0x1B1A1918 INTPRIOR7 0xF014003C R W Interrupt priority register 7 0x1F1E1D1C INTPRIOR8 0xF0140040 R W Interrupt priority register 8 0x23222120 INTPRIOR9 0xF0140044 R W Interrupt priority register 9 0x00262524 INTPRIOR0 30 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 ...

Page 602: ... is 0x00000027 This register is valid only under the IRQ or FIQ mode in the ARM940T In the interrupt service routine you should read this register before changing the CPU mode NOTE If the lowest interrupt priority priority 0 is pending the INTOFFSET value will be 0x00000000 The reset value will therefore be changed to 0x00000027 to be different from interrupt pending priority 0 Table 16 6 INTOFFSE...

Page 603: ...hannel 4 interrupt 0 x 1E 29 GDMA channel 3 interrupt 0 x 1D 28 GDMA channel 2 interrupt 0 x 1C 27 GDMA channel 1 interrupt 0 x 1B 26 GDMA channel 0 interrupt 0 x 1A 25 DES interrupt 0 x 19 24 Ethernet 1 RX interrupt 0 x 18 23 Ethernet 1 TX interrupt 0 x 17 22 Ethernet 0 RX interrupt 0 x 16 21 Ethernet 0 TX interrupt 0 x 15 20 HDLC 2 RX interrupt 0 x 14 19 HDLC 2 TX interrupt 0 x 13 18 HDLC 1 RX i...

Page 604: ...t Sources Returned Default Offset Value Hex 9 HUART 0 RX interrupt 0 x 9 8 HUART 0 TX interrupt 0 x 8 7 IIC interrupt 0 x 7 6 IOM2 interrupt 0 x 6 5 External interrupt 5 0 x 5 4 External interrupt 4 0 x 4 3 External interrupt 3 0 x 3 2 External interrupt 2 0 x 2 1 External interrupt 1 0 x 1 0 External interrupt 0 0 x 0 ...

Page 605: ...et register INTOFFSET Table 16 8 IPRIORHI IPRIORLO Register Register Address R W Description Reset Value IPRIORHI 0xF0140010 R High bits 38 32 bit Interrupt by priority register 0x00000000 IPRIORLO 0xF0140014 R Low bits 31 0 bit Interrupt by priority register 0x00000000 16 4 6 INTERRUPT TEST REGISTER The interrupt test registers INTTSTHI and INTTSTLO are used to monitor a interrupt pending status ...

Page 606: ...ue registers and Timer Interrupt Clear register TIC which is used to clear the current interrupt These timers can operate in interval mode or in toggle mode The output signals are TOUTn The user can enable or disable timers by setting control bits in Timer Mode register TMOD An interrupt request is generated whenever a timer count out down count occurs Watchdog Timer WDT has Watchdog Timer registe...

Page 607: ...4 TOGGLE MODE OPERATION In toggle mode the timer pulse continues to toggle whenever a time out occurs An interrupt request is generated whenever the level of the timer output signal is inverted that is when the level toggles The toggle pulse is output directly at the configured output pin Using toggle mode you can achieve a flexible timer clock range with 50 duty In toggle mode the timer frequency...

Page 608: ...he associated interrupt is generated The base value TDATA is then reloaded to the count register TCNT and the timer continues decrement of its count register value TCNT If a timer is disabled you can write a new base value into its registers TDATA If the timer is halted while it is running the base value is not automatically re loaded fSYSCLK 32 Bit Timer Count Register TCNTn Down Counter 32 Bit T...

Page 609: ...ODE REGISTER The timer mode register TMOD is used to control the operation of the six 32 bit timers TMOD register settings are described in Figure 17 3 Table 17 1 TMOD Register Register Address R W Description Reset Value TMOD 0xF0040000 R W Timer mode register 0x00000000 ...

Page 610: ... 6 3 4 5 1 2 T M D 0 T E 1 T E 0 T M D 1 T C L R 1 T C L R 0 T E 2 T M D 2 T C L R 2 T E 3 T M D 3 T C L R 3 T E 4 T M D 4 T C L R 4 T E 5 T M D 5 T C L R 5 7 13 10 11 12 8 9 17 14 15 16 9 Timer 3 enable TE3 0 Disable timer 3 1 Enable timer 3 10 Timer 3 mode selection TMD3 0 Interval mode 1 Toggle mode 11 Timer 3 initial TOUT3 value TCLR3 0 Initial TOUT3 is 0 in toggle mode 1 Initial TOUT3 is 1 in...

Page 611: ...s the specific time to reach interrupt service routine after time out takes place The elapsed time from time out to interrupt service routine is approximately 27 cycles 200n sec at 133 MHz Therefore TDATA should be set to the bigger value than 0x1A to avoid another time out while it is carrying out the process between time out and interrupt routine Table 17 2 TDATA0 TDATA5 Registers Register Addre...

Page 612: ...iption Reset Value TCNT0 0xF0040014 R W Timer 0 count register 0xFFFFFFFF TCNT1 0xF004001C R W Timer 1 count register 0xFFFFFFFF TCNT2 0xF0040024 R W Timer 2 count register 0xFFFFFFFF TCNT3 0xF004002C R W Timer 3 count register 0xFFFFFFFF TCNT4 0xF0040034 R W Timer 4 count register 0xFFFFFFFF TCNT5 0xF004003C R W Timer 5 count register 0xFFFFFFFF 31 0 Timer Count 31 0 Timer 0 5 count value Figure ...

Page 613: ... clear 1 interrupt clear 1 Timer0 interrupt clear TIC0 0 no interrupt clear 1 interrupt clear 2 Timer1 interrupt clear TIC1 0 no interrupt clear 1 interrupt clear 3 Timer2 interrupt clear TIC2 0 no interrupt clear 1 interrupt clear 4 Timer3 interrupt clear TIC3 0 no interrupt clear 1 interrupt clear 5 Timer4 interrupt clear TIC4 0 no interrupt clear 1 interrupt clear 6 Timer5 interrupt clear TIC5 ...

Page 614: ...er set two or more bits of WDTVAL the lowest significant bit of those let the watch dog timer time out Table 17 5 WDT Register Register Address R W Description Reset Value WDT 0xF0040008 R W Watchdog Timer Register 0x00000000 Watchdog Timer Timeout Value WDTVAL 17 0 Watchdog Timer Timeout Value WDTVAL 29 Watchdog Timer Counter Reset RST When set to 1 Watchdog Timer Counter is reset 30 Watchdog Tim...

Page 615: ... X X X X 1 0 0 0 0 217 983 0us X X X X X X X X X X X X 1 0 0 0 0 0 218 1 97ms X X X X X X X X X X X 1 0 0 0 0 0 0 219 3 93ms X X X X X X X X X X 1 0 0 0 0 0 0 0 220 7 86ms X X X X X X X X X 1 0 0 0 0 0 0 0 0 221 15 72ms X X X X X X X X 1 0 0 0 0 0 0 0 0 0 222 31 45ms X X X X X X X 1 0 0 0 0 0 0 0 0 0 0 223 62 91ms X X X X X X 1 0 0 0 0 0 0 0 0 0 0 0 224 125 82ms X X X X X 1 0 0 0 0 0 0 0 0 0 0 0 0...

Page 616: ...e 3 3V input buffer 3 8 VOUT DC output voltage 3 3V input buffer 3 8 ILATCH Latch up current 200 mA TSTG Storage termperature 65 to 150 C 18 3 RECOMMENDED OPERATING CONDITIONS Table 18 2 Recommended Operating Conditions Symbol Parameter Rating Unit VDD DC supply voltage 1 8V Core 1 8 5 V 3 3V I O 3 3 5 PLL DC supply voltage 1 8V Core 1 8 5 VIN DC input voltage 3 3V input buffer 3 0 3 6 VOUT DC out...

Page 617: ...trigger positive going threshold CMOS 2 0 V VT_ Schmitt trigger negative going threshold CMOS 0 8 V IIH High level input current µA Input buffer VIN VDD 10 10 Input buffer with pull down 10 33 60 IIL Low level input current µA Input buffer VIN VSS 10 10 Input buffer with pull up 60 33 10 VOH High level output voltage V Type B1 to B12 IOH 1 µA VDD 0 05 Type B1 IOH 1 mA 2 4 Type B2 IOH 2 mA Type B4 ...

Page 618: ...2 mA Type B4 IOL 4 mA Type B8 IOL 8 mA Type B12 IOL 12 mA Type B16 IOL 16 mA Type B20 IOL 20 mA Type B24 IOL 24 mA IOZ Tri state output leakage current VOUT VSS or VDD 10 10 µA IDS Quiescent supply current 100 µA IDD Maximum operating current VDD 3 3 V 1 8 V Frequency 133MHz note mA CIN Input capacitance Any Input Bi directional Buffers 4 pF COUT Output capacitance Any Output Buffer 4 pF NOTE Late...

Page 619: ...agnostic Test All Test Remap Mode I Cache On D Cache On 5 Samsung Diagnostic Test Idle Remap Mode I Cache On D Cache Table 18 4 MAX Power Consumption Voltage Temperature MAX Power Consumption 3 3 V 95 C 760 2 mW 1 8 V 3 3 V 80 C 740 4 mW 1 8 V 3 3 V 25 C 741 3 mW 1 8 V 3 3 V 0 C 738 mW 1 8 V 3 3 V 30 C 748 5 mW 1 8 V 3 3 V 50 C 737 1 mW 1 8 V 3 3 V Idle 25 C 664 2 mW 1 8 V The output can differ un...

Page 620: ...ency 33 166 MHz System bus frequency 33 133 MHz USB Frequency 48 48 MHz Table 18 5 Clock AC timing specification Characteristic Min Max Units Internal PLL lock time 150 µs Frequency of operation XCLK 133 MHz XCLK cycle time 7 5 ns XCLK duty cycle 45 55 Frequency of operation HCLKO 133 MHz HCLKO cycle Time 7 5 ns HCLKO duty cycle 45 55 ...

Page 621: ...xed bus address hold time 1 09 2 72 ns tnWAITd ROM SRAM WAIT signal delay time 1 5 11 ns tnWAITh ROM SRAM WAIT signalhold time 1 5 11 ns tCC SDRAM Clock Cycle Time 7 5 7 5 ps tCH SDRAM Clock High Pulse Width 4 1 4 5 ps tCL SDRAM Clock Low Pulse Width 3 4 3 5 ps tCASd SDRAM Column Address Strobe Delay Time 2 0 4 7 ps tCASh SDRAM Column Address Strobe Hold Time 2 0 4 6 ps tRASd SDRAM Row Address Str...

Page 622: ...S3C2500B MECHANICAL DATA 19 1 19 MECHANICAL DATA 19 1 OVERVIEW The S3C2500B is available in a 272 pin BGA package 272 BGA 2727 AN ...

Page 623: ... 6 7 8 9 10 11 12 13 14 K J H G F E D C B A N M L 1 17 0 05 0 36 0 56 0 10 2 13 2 33 0 20 0 15 MAX 272 BGA 2727 AN φ 0 38 MAX 18 19 20 1 27 Y W V U 272 φ0 76 0 015 15 16 17 1 27 T R P 27 00 0 10 24 00 0 10 A1 Corner A1 Corner Figure 19 1 272 BGA 2727 AN Package Dimensions ...

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