Samsung S3C2500B, User Manual

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S3C2500B PROGRAMMER
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S MODEL
2-29
2.16.1.8 Register 7: Cache operations
A write to this register can be used to perform the following operations:
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Flush ICache and Dcache
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Prefetch an ICache line
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Wait for interrupt
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Drain the write buffer
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Clean and flush the DCache.
The ARM940T uses a subset of the architecture V4 functions (defined in the ARM Architecture Reference
Manual). The available operations are summarized in Table 2-18 and described below.
Table 2-18. Cache Operations Writing to Register 7
ARM instruction
Data
Protection region register
MCR p15, 0, Rd, c7, c5, 0 should be zero Flush ICache
MCR p15, 0, Rd, c7, c5, 2 Index/segment Flush ICache single entry
MCR p15, 0, Rd, c7, c6, 0 should be zero Flush DCache
MCR p15, 0, Rd, c7, c6, 2 Index/segment Flush DCache single entry
MCR p15, 0, Rd, c7, c10, 2 Index/segment Clean DCache single entry
MCR p15, 0, Rd, c7, c13, 1 Address Prefetch ICache line
MCR p15, 0, Rd, c7, c14, 2 Index/segment Clean and flush DCache single entry
MCR p15, 0, Rd, c7, c8, 2 should be zero Wait for interrupt
MCR p15, 0, Rd, c7, c10, 4 should be zero Drain write buffer
"Should be zero" means the value transferred in the Rd.
A read from this register returns an unpredictable value.