Samsung S3C2500B, User Manual

Page: 225 / 623

S3C2500B SYSTEM CONFIGURATION
4-13
NOTES:
1. CPU PLL block can generate eight clock frequencies between 166MHz and 33MHz according to the
CPU_FREQ[2:0] pins out of the 10MHz XCLK input clock frequency.
2. USB PLL block can generate only 48MHz clock frequency out of the 10MHz USB_XCLK input clock frequency.
3. If CLKSEL, or USB_CLKSEL is 1, the CPU PLL, BUS PLL, or USB PLL go into the state of power down.
4. Three pins of CPU_FREQ[2:0] can control the multiplication factor of the CPU PLL block.
5. The PHY_FREQ pin controls the frequency of the PHY PLL.
6. The system configuration register CLKCON[15:0] can divide the ARM9 clock and the system clock. If all bits are 0,
non-divided clock is used.Only one bit can be set in CLKCON[15:0]. That is, the clock dividing value is defined as
1, 2, 4, 8, 16, .... The internal clock is (PLL output clock between 166MHz and 33MHz) / (1).
7. The CLKCON[15:0] register, CLKMOD[1:0] pins and CPU_FREQ[2:0] pins can control the AMBA clock divider.
The CLKMOD[1:0] pins and BUS_FREQ[2:0] pins can generate the various AMBA bus clock frequecies referring
to the Table 3. The CLKCON[15:0] register can divide the various AMBA clock frequecies of the Table 4-3.
8. All PLL can be controlled by either pin setting or register setting.
{CLKCON[15:0], CLKMOD[1:0],
BUS_FREQ[2:0]}
CPU PLL
166-33
MHz
0
1
ARM940T
Block
ARM
Clock
Divider
CPU_FREQ[2:0] or
CPLLCON
pdown
CLKSEL
XCLK
CLKCON[15:0]
BUS PLL
System
Block
AMBA
Clock
Divider
BUS_FREQ[2:0] or
SPLLCON
pdown
CLKSEL
XCLK 0
1
0
1
PLL_TEST
PLL
Clock
Divider
HCLKO
pin
PLL_TEST & PP[1:0]
CLKMOD[0]
USB PLL
0
1
USB
Block
USB
Clock
Divider
UPLLCON
pdown
USB_CLKSEL
USB_SCLK
PHY PLL
20/25
MHz
0
1
PHY_FREQ or
PPLLCON
pdown
PHY_CLKSEL
XCLK
48MHz
PHY_CLKO
48MHz 48MHz
133-33
MHz
Figure 4-5. Shows the Clock Generation Logic of the S3C2500B