S3C2500B
MEMORY CONTROLLER
5-53
5.7.9.4 Write Buffer Time-out Register
The write buffer time-out register works with the merging write buffer (if write buffer is enabled). This 16-bit
read/write field of register sets the cycles for a forced flush of the write buffer.
Table 5-28. SDRAM Write Buffer Time-out Register
Registers
Address
R/W
Description
Reset value
WBTOREG
0xF002000C
R/W
Write buffer time-out register
0x00000000
WBTOREG
Bit
Description
R/W
Default value
WBTO
[15:0]
Write buffer time-out delay time
R/W
0x00000000
[31:16]
Reserved
–
A write to a merging write buffer loads the value in the timeout register into the time-out down counter of the
buffer. When the time-out counter reaches 0 the merging write buffer contents is written(flushed) to the external
memory. The down counter is clocked by system bus clock. Storing a value of 0 in the timeout register disables
the write buffer timeout function.
[15:0] Write buffer time-out delay time:
[31:16] Reserved
31
0
15
16
RESERVED
WBTO
Figure 5-26. SDRAM Write Buffer Time-out Register
Summary of Contents for S3C2500B
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