Renesas SuperH SH-4A, Software Manual

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Rev. 1.50, 10/04, page 230 of 448
10.1.17 DIV1 (Divide 1 Step): Arithmetic Instruction
Format Operation Instruction Code Cycle T Bit
DIV1 Rm,Rn
1-step division
(Rn ÷ Rm)
0011nnnnmmmm0100
1
Result of
calculation
Description: This instruction performs 1-digit division (1-step division) of the 32-bit contents of
general register Rn (dividend) by the contents of Rm (divisor). The quotient is obtained by
repeated execution of this instruction alone or in combination with other instructions. The
specified registers and the M, Q, and T bits must not be modified during these repeated
executions.
In 1-step division, the dividend is shifted 1 bit to the left, the divisor is subtracted from this, and
the quotient bit is reflected in the Q bit according to whether the result is positive or negative.
The remainder can be found as follows after first finding the quotient using the DIV1 instruction:
(Remainder) = (dividend) – (divisor)
×
(quotient)
Detection of division by zero or overflow is not provided. Check for division by zero and overflow
division before executing the division. A remainder operation is not provided. Find the remainder
by finding the product of the divisor and the obtained quotient, and subtracting this value from the
dividend.
Initial settings should first be made with the DIV0S or DIV0U instruction. DIV1 is executed once
for each bit of the divisor. If a quotient of more than 17 bits is required, place an ROTCL
instruction before the DIV1 instruction. See the examples for details of the division sequence.
Notes: None
Operation:
DIV1(long m, long n) /* DIV1 Rm,Rn */
{
unsigned long tmp0, tmp2;
unsigned char old_q, tmp1;
old_q = Q;
Q = (unsigned char)((0x80000000 & R[n])!=0);
tmp2 = R[m];
R[n] <<= 1;
R[n] |= (unsigned long)T;