Renesas SuperH SH-4A, Software Manual

Page: 29 / 472

Rev. 1.50, 10/04, page 9 of 448
Floating-Point Registers and System Registers Related to FPU: There are thirty-two floating-
point registers, FR0–FR15 and XF0–XF15. FR0–FR15 and XF0–XF15 can be assigned to either
of two banks (FPR0_BANK0–FPR15_BANK0 or FPR0_BANK1–FPR15_BANK1).
FR0–FR15 can be used as the eight registers DR0/2/4/6/8/10/12/14 (double-precision floating-
point registers, or pair registers) or the four registers FV0/4/8/12 (register vectors), while XF0–
XF15 can be used as the eight registers XD0/2/4/6/8/10/12/14 (register pairs) or register matrix
XMTRX.
System registers related to the FPU comprise the floating-point communication register (FPUL)
and the floating-point status/control register (FPSCR). These registers are used for communication
between the FPU and the CPU, and the exception handling setting.
Register values after a reset are shown in table 2.1.
Table 2.1 Initial Register Values
Type Registers Initial Value
*
General registers R0_BANK0 to R7_BANK0,
R0_BANK1 to R7_BANK1,
R8 to R15
Undefined
SR MD bit = 1, RB bit = 1, BL bit = 1, FD bit = 0,
IMASK = B'1111, reserved bits = 0,
others = undefined
GBR, SSR, SPC, SGR, DBR Undefined
Control registers
VBR H'00000000
MACH, MACL, PR Undefined System registers
PC H'A0000000
FR0 to FR15, XF0 to XF15,
FPUL Undefined Floating-point
registers
FPSCR H'00040001
Note:
*
Initialized by a power-on reset and manual reset.
The CPU register configuration in each processing mode is shown in figure 2.2.
User mode and privileged mode are switched by the processing mode bit (MD) in the status
register.