Renesas SuperH SH-4A, Software Manual

Page: 351 / 472

Rev. 1.50, 10/04, page 331 of 448
10.1.75 SWAP (Swap Register Halves): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
SWAP.B Rm,Rn
Rm
→
lower-2-byte upper/
lower-byte swap
→
Rn
0110nnnnmmmm1000
1 —
SWAP.W Rm,Rn
Rm
→
upper-/lower-word
swap
→
Rn
0110nnnnmmmm1001
1
Description: This instruction swaps the upper and lower parts of the contents of general register
Rm, and stores the result in Rn.
In the case of a byte specification, the 8 bits from bit 15 to bit 8 of Rm are swapped with the 8 bits
from bit 7 to bit 0. The upper 16 bits of Rm are transferred directly to the upper 16 bits of Rn.
In the case of a word specification, the 16 bits from bit 31 to bit 16 of Rm are swapped with the 16
bits from bit 15 to bit 0.
Notes: None
Operation:
SWAPB(long m, long n) /* SWAP.B Rm,Rn */
{
unsigned long temp0,temp1;
temp0 = R[m] & 0xFFFF0000;
temp1 = (R[m] & 0x000000FF) << 8;
R[n] = (R[m] & 0x0000FF00) >> 8;
R[n] = R[n] | temp1 | temp0;
PC += 2;
}
SWAPW(long m, long n) /* SWAP.W Rm,Rn */
{
unsigned long temp;