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Renesas SuperH SH-4A, Software Manual

The Renesas SuperH SH-4A, a powerful semiconductor microprocessor, is accompanied by a comprehensive Software Manual providing detailed instructions and insights. This invaluable manual is available for free download at manualshive.com. Get ready to explore the full potential of this exceptional product with our user-friendly manual.

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Rev. 1.50, 10/04, page 170 of 448 

 

8.3.2 Prefetch 

Operation 

When the Operand Cache (OC) is enabled (OCE = 1 in CCR) and data is prefetched from a 
cacheable area, the cache operates as follows: 

1.  The tag, V bit, U bit, and LRU bits on each way are read from the cache line indexed by virtual 

address bits [12:5]. 

2.  The tag, read from each way, is compared with bits [28:10] of the physical address resulting 

from virtual address translation by the MMU: 

• 

If there is a way whose tag matches and its V bit is 1, see No. 3. 

• 

If there is no way whose tag matches and the V bit is 1, and the U bit of  the way which is 
selected to replace using the LRU bits is 0, see No. 4. 

• 

If there is no way whose tag matches and the V bit is 1, and the U bit of  the way which is 
selected to replace using the LRU bits is 1, see No. 5. 

3. Cache hit 

Then the LRU bits are updated to indicate the hitted way is the latest one. 

4.  Cache miss (no write-back) 

Data is read into the cache line on the way, which is selected to replace, from the physical 
address space corresponding to the virtual address. Data reading is performed, using the 
wraparound method, in order from the quad-word data (8 bytes) including the cache-missed 
data. In the prefetch operation the CPU doesn't wait the data arrives. While the one cache line 
of data is being read, the CPU can execute the next processing. When reading of one line of 
data is completed, the tag corresponding to the physical address is recorded in the cache, 1 is 
written to the V bit and 0 is written to the U bit on the way. And the LRU bit is updated to 
indicate the way is latest one. 

5.  Cache miss (with write-back) 

The tag and data field of the cache line on the way which is selected to replace are saved in the 
write-back buffer. Then data is read into the cache line on the way which is selected to replace 
from the physical address space corresponding to the virtual address. Data reading is 
performed, using the wraparound method, in order from the quad-word data (8 bytes) 
including the cache-missed data. In the prefetch operation the CPU doesn't wait the data 
arrives. While the one cache line of data is being read, the CPU can execute the next 
processing. And the LRU bits are updated to indicate the way is latest one. The data in the 
write-back buffer is then written back to external memory. 

 

Summary of Contents for SuperH SH-4A

Page 1: ... Microcomputer SuperH RISC engine Family Rev 1 50 REJ09B0003 0150Z The revision list can be viewed directly by clicking the title page The revision list summarizes the locations of revisions and additions Details should always be checked by referring to the relevant text ...

Page 2: ...Rev 1 50 10 04 page ii of xx ...

Page 3: ... total system before making a final decision on the applicability of the information and products Renesas Technology Corp assumes no responsibility for any damage liability or other loss resulting from the information contained herein 5 Renesas Technology Corp semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is poten...

Page 4: ...gister settings and the output state of each pin are also undefined Design your system so that it does not malfunction because of processing while it is in this undefined state For those products which have a reset function reset the LSI immediately after the power supply has been turned on 4 Prohibition of Access to Undefined or Reserved Addresses Note Access to undefined or reserved addresses is...

Page 5: ...dules The configuration of the functional description of each module differs according to the module However the generic style includes the following items i Feature ii Input Output Pin iii Register Description iv Operation v Usage Note When designing an application system that includes this LSI take notes into account Each section includes notes in relation to the descriptions given and usage not...

Page 6: ...This manual can be roughly categorized into parts on the CPU system control functions and instructions In order to understand the instructions The instruction format and basic operation are explained in section 3 Instruction Set For details on each instruction operation read section 10 Instruction Descriptions Rules Register name The following notation is used for cases when the same or a similar ...

Page 7: ...SID Address Space Identifier CPU Central Processing Unit FPU Floating Point Unit LRU Least Recently Used LSB Least Significant Bit MMU Memory Management Unit MSB Most Significant Bit PC Program Counter RISC Reduced Instruction Set Computer TLB Translation Lookaside Buffer ...

Page 8: ...Rev 1 50 10 04 page viii of xx ...

Page 9: ...s 21 2 7 Usage Notes 22 2 7 1 Notes on Self Modified Codes 22 Section 3 Instruction Set 23 3 1 Execution Environment 23 3 2 Addressing Modes 25 3 3 Instruction Set 29 Section 4 Pipelining 43 4 1 Pipelines 43 4 2 Parallel Executability 54 4 3 Issue Rates and Execution Cycles 56 Section 5 Exception Handling 65 5 1 Summary of Exception Handling 65 5 2 Register Descriptions 65 5 2 1 TRAPA Exception Re...

Page 10: ... 3 Floating Point Communication Register FPUL 107 6 4 Rounding 108 6 5 Floating Point Exceptions 109 6 5 1 General FPU Disable Exceptions and Slot FPU Disable Exceptions 109 6 5 2 FPU Exception Sources 109 6 5 3 FPU Exception Handling 110 6 6 Graphics Support Functions 111 6 6 1 Geometric Operation Instructions 111 6 6 2 Pair Single Precision Data Transfer 112 Section 7 Memory Management Unit MMU ...

Page 11: ... Memory Mapped TLB Configuration 146 7 6 1 ITLB Address Array 147 7 6 2 ITLB Data Array 148 7 6 3 UTLB Address Array 149 7 6 4 UTLB Data Array 150 7 7 32 Bit Address Extended Mode 151 7 7 1 Overview of 32 Bit Address Extended Mode 152 7 7 2 Transition to 32 Bit Address Extended Mode 152 7 7 3 Privileged Space Mapping Buffer PMB Configuration 152 7 7 4 PMB Function 154 7 7 5 Memory Mapped PMB Confi...

Page 12: ...ing 32 Bit Address Extended Mode 185 Section 9 L Memory 187 9 1 Features 187 9 2 Register Descriptions 188 9 2 1 On Chip Memory Control Register RAMCR 189 9 2 2 L Memory Transfer Source Address Register 0 LSA0 190 9 2 3 L Memory Transfer Source Address Register 1 LSA1 191 9 2 4 L Memory Transfer Destination Address Register 0 LDA0 193 9 2 5 L Memory Transfer Destination Address Register 1 LDA1 195...

Page 13: ...ed Arithmetic Instruction 240 10 1 22 EXTU Extend as Unsigned Arithmetic Instruction 242 10 1 23 ICBI Instruction Cache Block Invalidate Data Transfer Instruction 243 10 1 24 JMP Jump Branch Instruction 244 10 1 25 LDC Load to Control Register System Control Instruction 245 10 1 26 LDS Load to System Register System Control Instruction 249 10 1 27 LDTLB Load PTEH PTEL to TLB System Control Instruc...

Page 14: ...hift Arithmetic Left Shift Instruction 310 10 1 63 SHAR Shift Arithmetic Right Shift Instruction 311 10 1 64 SHLD Shift Logical Dynamically Shift Instruction 312 10 1 65 SHLL Shift Logical Left Shift Instruction 314 10 1 66 SHLLn n bits Shift Logical Left Shift Instruction 315 10 1 67 SHLR Shift Logical Right Shift Instruction 317 10 1 68 SHLRn n bits Shift Logical Right Shift Instruction 318 10 1...

Page 15: ...84 10 3 9 FLDI1 Floating point Load Immediate 1 0 Floating Point Instruction 385 10 3 10 FLDS Floating point Load to System register Floating Point Instruction 386 10 3 11 FLOAT Floating point Convert from Integer Floating Point Instruction 387 10 3 12 FMAC Floating point Multiply and Accumulate Floating Point Instruction 389 10 3 13 FMOV Floating point Move Floating Point Instruction 395 10 3 14 ...

Page 16: ...orresponding section numbers 428 11 2 Register States in Each Operating Mode 430 Appendix 431 A CPU Operation Mode Register CPUOPM 431 B Instruction Prefetching and Its Side Effects 433 C Speculative Execution for Subroutine Return 434 D Version Registers PVR PRR 435 Main Revisions and Additions in this Edition 437 Index 445 ...

Page 17: ... Figure 4 2 Instruction Execution Patterns 7 51 Figure 4 2 Instruction Execution Patterns 8 52 Figure 4 2 Instruction Execution Patterns 9 53 Section 5 Exception Handling Figure 5 1 Instruction Execution and Exception Handling 72 Figure 5 2 Example of General Exception Acceptance Order 73 Section 6 Floating Point Unit FPU Figure 6 1 Format of Single Precision Floating Point Number 98 Figure 6 2 Fo...

Page 18: ...xtended Mode 151 Figure 7 17 PMB Configuration 152 Figure 7 18 Memory Mapped PMB Address Array 155 Figure 7 19 Memory Mapped PMB Data Array 156 Section 8 Caches Figure 8 1 Configuration of Operand Cache OC 160 Figure 8 2 Configuration of Instruction Cache IC 161 Figure 8 3 Configuration of Write Back Buffer 172 Figure 8 4 Configuration of Write Through Buffer 172 Figure 8 5 Memory Mapped IC Addres...

Page 19: ... Single Precision Instructions 40 Table 3 11 Floating Point Double Precision Instructions 41 Table 3 12 Floating Point Control Instructions 41 Table 3 13 Floating Point Graphics Acceleration Instructions 42 Section 4 Pipelining Table 4 1 Representations of Instruction Execution Patterns 44 Table 4 2 Instruction Groups 54 Table 4 3 Combination of Preceding and Following Instructions 55 Table 4 4 Is...

Page 20: ...r Configuration 162 Table 8 4 Register States in Each Processing State 162 Section 9 L Memory Table 9 1 L Memory Addresses 187 Table 9 2 Register Configuration 188 Table 9 3 Register Status in Each Processing State 188 Table 9 4 Protective Function Exceptions to Access L Memory 199 Appendix Table D 1 Register Configuration 435 ...

Page 21: ...al data bus General register files Sixteen 32 bit general registers eight 32 bit shadow registers Seven 32 bit control registers Four 32 bit system registers RISC type instruction set upward compatible with the SH 1 SH 2 SH 3 and SH 4 microcomputers Instruction length 16 bit fixed length for improved code efficiency Load store architecture Delayed branch instructions Instructions executed with con...

Page 22: ...atency FMAC FMUL 5 cycles single precision 7 cycles double precision Pitch FADD FSUB 1 cycle single precision double precision Pitch FMAC FMUL 1 cycle single precision 3 cycles double precision Note FMAC is supported for single precision only 3 D graphics instructions single precision only 4 dimensional vector conversion and matrix operations FTRV 4 cycles pitch 8 cycles latency 4 dimensional vect...

Page 23: ...write method copy back or write through Storage queue 32 bytes 2 entries Note For the size of instruction cash and operand cash see corresponding hardware manual on the product L memory Two independent read write ports 8 16 32 64 bit access from the CPU 8 16 32 64 bit and 16 32 byte access from the external devices Note For the size of L memory see the hardware manual of the target product ...

Page 24: ... are added as CPU instructions 3 Instruction Set 3 3 Instruction Set 3 instructions are added as FPU instructions 4 1 Pipelines The number of stages in the pipeline is changed from five to seven 9 instructions are added as CPU instructions 3 instructions are added as FPU instructions 4 2 Parallel Executability Instruction group and parallel execution combinations are modified 4 Pipelining 4 3 Exec...

Page 25: ...ts are modified according to the cache size change and the index mode deletion 7 5 1 7 5 4 Instruction TLB Multiple Hit Exception and Data TLB Multiple Hit Exception Multiple hits during the UTLB search caused by ITLB mishandling are changed to be handled as a TLB multiple hit instruction exception 7 6 Memory Mapped TLB Configuration Data array 2 in the ITLB and UTLB is deleted Associative writes ...

Page 26: ...tion RAM mode and OC index mode are deleted 8 3 6 OC Two Way Mode Newly added 8 4 Instruction Cache Operation IC index mode is deleted 8 4 3 IC Two Way Mode Newly added 8 5 1 Coherency between Cache and External Memory The ICBI PREFI and SYNCO instructions are added 8 Caches 8 6 Memory Mapped Cache Configuration The entry bits and the way bits are modified according to the size modification and ch...

Page 27: ...a formats as shown below 2 1 Data Formats The data formats supported in the SH 4A are shown in figure 2 1 Byte 8 bits Word 16 bits Longword 32 bits Single precision floating point 32 bits Double precision floating point 64 bits 0 7 0 15 0 31 0 31 30 22 s e f 0 63 62 51 s e f Legend s e f Sign field Exponent field Fraction field Figure 2 1 Data Formats ...

Page 28: ...s comprising bank 0 general registers R0_BANK0 to R7_BANK0 are accessed by the LDC STC instructions When the RB bit is 0 that is when bank 0 is selected the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non banked general registers R8 to R15 can be accessed as general registers R0 to R15 In this case the eight registers comprising bank 1 general registers R0_BANK1 to R7...

Page 29: ...loating point status control register FPSCR These registers are used for communication between the FPU and the CPU and the exception handling setting Register values after a reset are shown in table 2 1 Table 2 1 Initial Register Values Type Registers Initial Value General registers R0_BANK0 to R7_BANK0 R0_BANK1 to R7_BANK1 R8 to R15 Undefined SR MD bit 1 RB bit 1 BL bit 1 FD bit 0 IMASK B 1111 re...

Page 30: ...NK1 3 R5_BANK1 3 R6_BANK1 3 R7_BANK1 3 R8 R9 R10 R11 R12 R13 R14 R15 R0_BANK0 1 4 R1_BANK0 4 R2_BANK0 4 R3_BANK0 4 R4_BANK0 4 R5_BANK0 4 R6_BANK0 4 R7_BANK0 4 c Register configuration in privileged mode RB 0 GBR MACH MACL VBR PR SR SSR PC SPC SGR DBR SGR DBR R0 is used as the index register in indexed register indirect addressing mode and indexed GBR indirect addressing mode Banked registers Banke...

Page 31: ...o R7 when SR RB 1 in privileged mode SR MD 0 or SR MD 1 SR RB 0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK0 R1_BANK0 R2_BANK0 R3_BANK0 R4_BANK0 R5_BANK0 R6_BANK0 R7_BANK0 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0_BANK1 R1_BANK1 R2_BANK1 R3_BANK1 R4_BANK1 R5_BANK1 R6_BANK1 R7_BANK1 R0 R1 R2 R3 R4 R5 R6 R7 R0 R1 R2 R3 R4 R5 R6 R7 ...

Page 32: ...registers or single precision floating point registers DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 4 Single precision floating point vector registers FVi 4 registers An FV register comprises four FR registers FV0 FR0 FR1 FR2 FR3 FV4 FR4 FR5 FR6 FR7 FV8 FR8 FR9 FR10 FR11 FV12 FR12 F...

Page 33: ...2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0_BANK1 FPR1_BANK1 FPR2_BANK1 FPR3_BANK1 FPR4_BANK1 FPR5_BANK1 FPR6_BANK1 FPR7_BANK1 FPR8_BANK1 FPR9_BANK1 FPR10_BANK1 FPR11_BANK1 FPR12_BANK1 FPR13_BANK1 FPR14_BANK1 FPR15_BANK1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF10 XF11 XF12 XF13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 F...

Page 34: ... cannot be accessed 1 Privileged mode This bit is set to 1 by an exception or interrupt 29 RB 1 R W Privileged Mode General Register Bank Specification Bit 0 R0_BANK0 to R7_BANK0 are accessed as general registers R0 to R7 and R0_BANK1 to R7_BANK1 can be accessed using LDC STC instructions 1 R0_BANK1 to R7_BANK1 are accessed as general registers R0 to R7 and R0_BANK0 R7_BANK0 can be accessed using ...

Page 35: ...IMASK bits is masked It can be chosen by CPU operation mode register CPUOPM whether the level of IMASK is changed to accept an interrupt or not when an interrupt is occurred For details see Appendix A CPU Operation Mode Register CPUOPM 3 2 All 0 R Reserved For details on reading writing this bit see General Precautions on Handling of Product 1 S 0 R W S Bit Used by the MAC instruction 0 T 0 R W T ...

Page 36: ...reak debugging function is enabled CBCR UBDE 1 DBR is referenced as the branch destination address of the user break handler instead of VBR 2 2 5 System Registers Multiply and Accumulate Registers MACH and MACL 32 bits Initial Value Undefined MACH and MACL are used for the added value in a MAC instruction and to store the operation result of a MAC or MUL instruction Procedure Register PR 32 bits I...

Page 37: ...0 to FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1 FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 20 SZ 0 R W Transfer Size Mode 0 Data size of FMOV instruction is 32 bits 1 Data size of FMOV instruction is a 32 bit register pair 64 bits For relationship between the SZ bit PR bit ...

Page 38: ...able 2 2 1 0 RM 01 R W Rounding Mode These bits select the rounding mode 00 Round to Nearest 01 Round to Zero 10 Reserved 11 Reserved Big endian DR 2i FR 2i FR 2i 1 8n 4 8n 7 8n 8n 3 63 0 63 32 31 0 Floating point register Memory area 63 0 Little endian Floating point register Memory area DR 2i FR 2i FR 2i 1 4n 4m 4n 3 4m 3 63 0 63 32 31 0 DR 2i FR 2i 1 FR 2i 8n 4 8n 7 8n 3 8n 63 0 63 32 31 0 1 SZ...

Page 39: ... to H FFFF FFFF These two areas are used as follows H 1C00 0000 to H 1FFF FFFF This area must be accessed using the address translation function of the MMU Setting the page number of this area to the corresponding field of the TLB enables access to a memory mapped register The operation of an access to this area without using the address translation function of the MMU is not guaranteed H FC00 000...

Page 40: ...loaded into a register A word operand must be accessed starting from a word boundary even address of a 2 byte unit address 2n and a longword operand starting from a longword boundary even address of a 4 byte unit address 4n An address error will result if this rule is not observed A byte operand can be accessed from any address Big endian or little endian byte order can be selected for the data fo...

Page 41: ... and the on chip peripheral module registers are initialized In the manual reset state the internal state of the CPU and some registers of on chip peripheral modules are initialized For details see register descriptions for each section Instruction Execution State In this state the CPU executes program instructions in sequence The Instruction execution state has the normal program execution state ...

Page 42: ...uction can be any address within the range where no address error exception occurs In Case the Modified Codes are in Cacheable Area Write Through SYNCO ICBI Rn All instruction cache areas corresponding to the modified codes should be invalidated by the ICBI instruction The ICBI instruction should be issued to each cache line One cache line is 32 bytes In Case the Modified Codes are in Cacheable Ar...

Page 43: ...es memory access are loaded into registers and the operation is executed between the registers Delayed Branches Except for the two branch instructions BF and BT the SH 4A s branch instructions and RTE are delayed branches In a delayed branch the instruction following the branch is executed before the branch destination instruction Delay Slot This execution slot following a delayed branch is called...

Page 44: ...n are used for delay slot instruction execution The STC and STC L SR instructions access all SR bits after modification Constant Values An 8 bit constant value can be specified by the instruction code and an immediate value 16 bit and 32 bit constant values can be defined as literal constant values in memory and can be referenced by a PC relative load instruction MOV W disp PC Rn MOV L disp PC Rn ...

Page 45: ... is register Rn Operand is register Rn contents Register indirect Rn Effective address is register Rn contents Rn Rn Rn EA EA effective address Register indirect with post increment Rn Effective address is register Rn contents A constant is added to Rn after instruction execution 1 for a byte operand 2 for a word operand 4 for a longword operand 8 for a quadword operand Rn Rn 1 2 4 Rn 1 2 4 Rn EA ...

Page 46: ... Rn disp EA Word Rn disp 2 EA Longword Rn disp 4 EA Indexed register indirect R0 Rn Effective address is sum of register Rn and R0 contents Rn R0 Rn R0 Rn R0 EA GBR indirect with displace ment disp 8 GBR Effective address is register GBR contents with 8 bit displacement disp added After disp is zero extended it is multiplied by 1 byte 2 word or 4 longword according to the operand size GBR 1 2 4 GB...

Page 47: ...plied by 2 word or 4 longword according to the operand size With a longword operand the lower 2 bits of PC are masked PC H FFFF FFFC PC 4 disp 2 or PC H FFFF FFFC 4 disp 4 4 2 4 disp zero extended With longword operand Word PC 4 disp 2 EA Longword PC H FFFF FFFC 4 disp 4 EA PC relative disp 8 Effective address is PC 4 with 8 bit displacement disp added after being sign extended and multiplied by 2...

Page 48: ...on is zero extended imm 8 8 bit immediate data imm of MOV ADD or CMP EQ instruction is sign extended imm 8 8 bit immediate data imm of TRAPA instruction is zero extended and multiplied by 4 Note For the addressing modes below that use a displacement disp the assembler descriptions in this manual show the value before scaling 1 2 or 4 is performed according to the operand size This is done to clari...

Page 49: ...ion xx Memory operand M Q T SR flag bits Logical AND of individual bits Logical OR of individual bits Logical exclusive OR of individual bits Logical NOT of individual bits n n n bit shift Instruction code MSB LSB mmmm Register number Rm FRm nnnn Register number Rn FRn 0000 R0 FR0 0001 R1 FR1 1111 R15 FR15 mmm Register number DRm XDm Rm_BANK nnn Register number DRn XDn Rn_BANK 000 DR0 XD0 R0_BANK ...

Page 50: ... Item Format Description T bit Value of T bit after instruction execution No change New New means the instruction which is newly added in this LSI Note Scaling 1 2 4 or 8 is executed according to the size of the instruction operand ...

Page 51: ...OV W Rm Rn Rn 2 Rn Rm Rn 0010nnnnmmmm0101 MOV L Rm Rn Rn 4 Rn Rm Rn 0010nnnnmmmm0110 MOV B Rm Rn Rm sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 MOV W Rm Rn Rm sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnnmmmm0110 MOV B R0 disp Rn R0 disp Rn 10000000nnnndddd MOV W R0 disp Rn R0 disp 2 Rn 10000001nnnndddd MOV L Rm disp Rn Rm disp 4 Rn 0001nnnnmmmmdddd MOV B disp Rm R0 ...

Page 52: ... H FFFF FFFC 4 R0 11000111dddddddd MOVCO L R0 Rn LDST T If T 1 R0 Rn 0 LDST 0000nnnn01110011 LDST New MOVLI L Rm R0 1 LDST Rm R0 When interrupt exception occurred 0 LDST 0000mmmm01100011 New MOVUA L Rm R0 Rm R0 Load non boundary alignment data 0100mmmm10101001 New MOVUA L Rm R0 Rm R0 Rm 4 Rm Load non boundary alignment data 0100mmmm11101001 New MOVT Rn T Rn 0000nnnn00101001 SWAP B Rm Rn Rm swap lo...

Page 53: ...Rn Rm signed 1 T Otherwise 0 T 0011nnnnmmmm0011 Comparison result CMP HI Rm Rn When Rn Rm unsigned 1 T Otherwise 0 T 0011nnnnmmmm0110 Comparison result CMP GT Rm Rn When Rn Rm signed 1 T Otherwise 0 T 0011nnnnmmmm0111 Comparison result CMP PZ Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010001 Comparison result CMP PL Rn When Rn 0 1 T Otherwise 0 T 0100nnnn00010101 Comparison result CMP STR Rm Rn When...

Page 54: ...nnnmmmm1101 MAC L Rm Rn Signed Rn Rm MAC MAC Rn 4 Rn Rm 4 Rm 32 32 64 64 bits 0000nnnnmmmm1111 MAC W Rm Rn Signed Rn Rm MAC MAC Rn 2 Rn Rm 2 Rm 16 16 64 64 bits 0100nnnnmmmm1111 MUL L Rm Rn Rn Rm MACL 32 32 32 bits 0000nnnnmmmm0111 MULS W Rm Rn Signed Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1111 MULU W Rm Rn Unsigned Rn Rm MACL 16 16 32 bits 0010nnnnmmmm1110 NEG Rm Rn 0 Rm Rn 0110nnnnmmmm1011 NEGC Rm...

Page 55: ...imm R0 11001011iiiiiiii OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii TAS B Rn When Rn 0 1 T Otherwise 0 T In both cases 1 MSB of Rn 0100nnnn00011011 Test result TST Rm Rn Rn Rm when result 0 1 T Otherwise 0 T 0010nnnnmmmm1000 Test result TST imm R0 R0 imm when result 0 1 T Otherwise 0 T 11001000iiiiiiii Test result TST B imm R0 GBR R0 GBR imm when result 0 1 T Otherwise 0 T 11001100iiiiiiii ...

Page 56: ... When Rm 0 Rn Rm Rn When Rm 0 Rn Rm MSB Rn 0100nnnnmmmm1100 SHAL Rn T Rn 0 0100nnnn00100000 MSB SHAR Rn MSB Rn T 0100nnnn00100001 LSB SHLD Rm Rn When Rm 0 Rn Rm Rn When Rm 0 Rn Rm 0 Rn 0100nnnnmmmm1101 SHLL Rn T Rn 0 0100nnnn00000000 MSB SHLR Rn 0 Rn T 0100nnnn00000001 LSB SHLL2 Rn Rn 2 Rn 0100nnnn00001000 SHLR2 Rn Rn 2 Rn 0100nnnn00001001 SHLL8 Rn Rn 8 Rn 0100nnnn00011000 SHLR8 Rn Rn 8 Rn 0100nnn...

Page 57: ...PC 4 PR disp 2 PC 4 PC 1011dddddddddddd BSRF Rn Delayed branch PC 4 PR Rn PC 4 PC 0000nnnn00000011 JMP Rn Delayed branch Rn PC 0100nnnn00101011 JSR Rn Delayed branch PC 4 PR Rn PC 0100nnnn00001011 RTS Delayed branch PR PC 0000000000001011 Table 3 9 System Control Instructions Instruction Operation Instruction Code Privileged T Bit New CLRMAC 0 MACH MACL 0000000000101000 CLRS 0 S 0000000001001000 C...

Page 58: ...0001010 LDS Rm MACL Rm MACL 0100mmmm00011010 LDS Rm PR Rm PR 0100mmmm00101010 LDS L Rm MACH Rm MACH Rm 4 Rm 0100mmmm00000110 LDS L Rm MACL Rm MACL Rm 4 Rm 0100mmmm00010110 LDS L Rm PR Rm PR Rm 4 Rm 0100mmmm00100110 LDTLB PTEH PTEL TLB 0000000000111000 Privileged MOVCA L R0 Rn R0 Rn without fetching cache block 0000nnnn11000011 NOP No operation 0000000000001001 OCBI Rn Invalidates operand cache blo...

Page 59: ...Rn 4 Rn SSR Rn 0100nnnn00110011 Privileged STC L SPC Rn Rn 4 Rn SPC Rn 0100nnnn01000011 Privileged STC L SGR Rn Rn 4 Rn SGR Rn 0100nnnn00110010 Privileged STC L DBR Rn Rn 4 Rn DBR Rn 0100nnnn11110010 Privileged STC L Rm_BANK Rn Rn 4 Rn Rm_BANK Rn m 0 to 7 0100nnnn1mmm0011 Privileged STS MACH Rn MACH Rn 0000nnnn00001010 STS MACL Rn MACL Rn 0000nnnn00011010 STS PR Rn PR Rn 0000nnnn00101010 STS L MAC...

Page 60: ...OV Rm DRn Rm DRn Rm 8 Rm 1111nnn0mmmm1001 FMOV DRm Rn DRm Rn 1111nnnnmmm01010 FMOV DRm Rn Rn 8 Rn DRm Rn 1111nnnnmmm01011 FMOV DRm R0 Rn DRm R0 Rn 1111nnnnmmm00111 FLDS FRm FPUL FRm FPUL 1111mmmm00011101 FSTS FPUL FRn FPUL FRn 1111nnnn00001101 FABS FRn FRn H 7FFF FFFF FRn 1111nnnn01011101 FADD FRm FRn FRn FRm FRn 1111nnnnmmmm0000 FCMP EQ FRm FRn When FRn FRm 1 T Otherwise 0 T 1111nnnnmmmm0100 Comp...

Page 61: ...FPUL DRn 1111nnn010101101 FLOAT FPUL DRn float FPUL DRn 1111nnn000101101 FMUL DRm DRn DRn DRm DRn 1111nnn0mmm00010 FNEG DRn DRn H 8000 0000 0000 0000 DRn 1111nnn001001101 FSQRT DRn DRn DRn 1111nnn001101101 FSUB DRm DRn DRn DRm DRn 1111nnn0mmm00001 FTRC DRm FPUL long DRm FPUL 1111mmm000111101 Table 3 12 Floating Point Control Instructions Instruction Operation Instruction Code Privileged T Bit New ...

Page 62: ...Rm XDn R0 Rm XDn 1111nnn1mmmm0110 FMOV XDm Rn XDm Rn 1111nnnnmmm11010 FMOV XDm Rn Rn 8 Rn XDm Rn 1111nnnnmmm11011 FMOV XDm R0 Rn XDm R0 Rn 1111nnnnmmm10111 FIPR FVm FVn inner_product FVm FVn FR n 3 1111nnmm11101101 FTRV XMTRX FVn transform_vector XMTRX FVn FVn 1111nn0111111101 FRCHG FPSCR FR FPSCR FR 1111101111111101 FSCHG FPSCR SZ FPSCR SZ 1111001111111101 FPCHG FPSCR PR FPSCR PR 1111011111111101...

Page 63: ... I2 ID E1 E2 E3 WB 2 General Load Store Pipeline 3 Special Pipeline 4 Special Load Store Pipeline 5 Floating Point Pipeline 6 Floating Point Extended Pipeline Instruction fetch Instruction decode Issue Operation Write back Operation Operation Register read Forwarding I1 I2 ID FS1 FS2 FS4 FS3 FS Operation Instruction fetch Instruction decode Issue Register read Forwarding Operation Operation Operat...

Page 64: ...E2 E3 WB CPU EX pipe is occupied S1 S2 S3 WB CPU LS pipe is occupied with memory access s1 s2 s3 WB CPU LS pipe is occupied without memory access E1 S1 Either CPU EX pipe or CPU LS pipe is occupied E1S1 E1s1 Both CPU EX pipe and CPU LS pipe are occupied M2 M3 MS CPU MULT operation unit is occupied FE1 FE2 FE3 FE4 FE5 FE6 FS FPU EX pipe is occupied FS1 FS2 FS3 FS4 FS FPU LS pipe is occupied ID ID s...

Page 65: ...t constant cycles to the clock halted period 1 6 SLEEP 2 issue cycles I1 ID I2 Branch destination instruction Branch destination instruction I1 ID I2 Branch destination instruction In branch instructions that are categorized as 1 1 the number of branch cycles may be reduced by prefetching Note Note I1 I2 ID s1 s2 s3 WB E2s2 ID E3s3 ID WB ID I1 ID I2 E1s1 I1 I2 ID S1 S2 S3 WB E1s1 E3s3 E2s2 E1s1 E1...

Page 66: ... 2 2 1 step operation LS type 1 issue cycle 2 3 1 step operation MT type 1 issue cycle 2 4 MOV MT type 1 issue cycle EXT SU BW MOVT SWAP XTRCT ADD CMP DIV DT NEG SUB AND AND NOT OR OR TST TST XOR XOR ROT SHA SHL CLRS CLRT SETS SETT MOV NOP MOVA MOV Note Except for AND OR TST and XOR instructions using GBR relative addressing mode Figure 4 2 Instruction Execution Patterns 2 ...

Page 67: ...cycles 3 branch cycle 3 8 MOVLI L 1 issue cycle I1 I2 ID S1 S2 S3 WB 3 9 MOVCO L 1 issue cycle I1 I2 ID S1 S2 S3 WB 3 10 MOVUA L 2 issue cycles I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB Branch to the next instruction of ICBI E2S2 E3S3 WB E1S1 ID ID E2S2 E3S3 WB E1S1 E2S2 E3S3 WB E1S1 ID ID ID I1 I2 ID s1 s2 s3 WB E1s1 E1s1 E1s1 E2s2 E2s2 E2s2 E3s3 E3s3 E3s3 WB WB WB I1 ID I2 ID ID ID ID ID ID ID 5 cycles m...

Page 68: ...1 s2 s3 WB I1 I2 ID S1 S2 S3 WB 4 5 LDC L to Rp_BANK SSR SPC VBR 1 issue cycle I1 I2 ID E1s1 E2s2 E3s3 WB ID ID ID 4 6 LDC L to DBR SGR 4 issue cycles 4 7 LDC L to GBR 1 issue cycle I1 I2 ID S1 S2 S3 WB ID ID ID I1 I2 ID E1S1 E2S2 E3S3 WB ID ID ID ID ID I1 I2 ID S1 S2 S3 WB 4 8 LDC L to SR 6 issue cycles 3 branch cycles I1 ID I2 Branch to the next instruction Branch to the next instruction I1 ID I...

Page 69: ...e I1 I2 ID WB I1 I2 ID S1 S2 S3 E1S1 E2S2 E3S3 WB I1 I2 ID s1 s2 s3 WB 4 14 LDS L to PR 1 issue cycle I1 I2 ID s1 s2 s3 WB 4 15 STS from PR 1 issue cycle I1 I2 ID S1 S2 S3 WB 4 16 STS L from PR 1 issue cycle I1 I2 ID 1 2 3 WB 4 17 BSRF BSR JSR delay slot instructions PR set 0 issue cycle The value of PR is changed in the E3 stage of delay slot instruction When the STS and STS L instructions from P...

Page 70: ... E1 M2 M3 MS E1 M2 M3 MS M2 M3 MS 5 5 MULS W MULU W 1 issue cycle 5 6 DMULS L DMULU L MUL L 1 issue cycle 5 7 CLRMAC 1 issue cycle I1 I2 ID I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB I1 I2 ID 5 8 MAC W 2 issue cycle 5 9 MAC L 2 issue cycle I1 I2 ID s1 s2 s3 WB MS I1 I2 ID S1 S2 S3 WB MS I1 I2 ID S1 S2 S3 WB MS M2 M3 MS M2 M3 MS M2 M3 I1 I2 ID S1 S2 S3 WB S1 S2 S3 WB ID ID Figure 4 2 Instruction Execution Pa...

Page 71: ... 6 4 STS L from FPUL 1 issue cycle 6 5 LDS to FPSCR 1 issue cycle 6 6 STS from FPSCR 1 issue cycle 6 7 LDS L to FPSCR 1 issue cycle 6 8 STS L from FPSCR 1 issue cycle 6 9 FPU load store instruction FMOV 1 issue cycle I1 I2 ID I1 I2 ID S1 S2 S3 WB S1 S2 S3 S1 S2 S3 WB I1 I2 ID s1 s2 s3 I1 I2 ID WB S1 S2 S3 WB FS3 S1 S2 S3 WB FS1 FS2 FS3 FS4 FS s1 s2 s3 WB I1 I2 ID 6 10 FLDS 1 issue cycle I1 I2 ID I...

Page 72: ... cycle 6 18 Double precision FDIV FSQRT 1 issue cycle I1 I2 ID s1 s2 s3 FS1 FS2 FS3 FS4 I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS FEDS Divider occupied cycle FS FCMP EQ FCMP GT FADD FLOAT FMAC FMUL FSUB FTRC FRCHG FSCHG FPCHG FCMP EQ FCMP GT FADD FLOAT FSUB FTRC FCNVSD FCNVDS FMUL FEDS Divider occupied cycle I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 F...

Page 73: ...nction computing unit occupied cycle I1 I2 ID FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS I1 I2 ID FE1 FE2 FE3 FEPL FE4 FE5 FE6 FS FEPL I1 I2 ID FE1 FE2 FE1 FE2 FE3 FE4 FE5 FE6 FS FE3 FE4 FE5 FE6 FS FE1 FE2 FE3 FE4 FE5 FE6 FS Figure 4 2 Instruction Execution Patterns 9 ...

Page 74: ...ULS W MULU W NEG NEGC NOT OR imm R0 OR Rm Rn ROTCL ROTCR ROTL ROTR SETS SETT SHAD SHAL SHAR SHLD SHLL SHLL2 SHLL8 SHLL16 SHLR SHLR2 SHLR8 SHLR16 SUB SUBC SUBV SWAP TST imm R0 TST Rm Rn XOR imm R0 XOR Rm Rn XTRCT MT MOV imm Rn MOV Rm Rn NOP BR BF BF S BRA BRAF BSR BSRF BT BT S JMP JSR RTS LS FABS FNEG FLDI0 FLDI1 FLDS FMOV adr FR FMOV FR adr FMOV FR FR FMOV S adr FR FMOV S FR adr FSTS LDC Rm CR1 LD...

Page 75: ...Both addr preceding instruction and addr 2 following instruction are specified within the minimum page size 1 Kbyte 2 The execution of these two instructions is supported in table 4 3 Combination of Preceding and Following Instructions 3 Data used by an instruction of addr does not conflict with data used by a previous instruction 4 Data used by an instruction of addr 2 does not conflict with data...

Page 76: ...2 S3 WB MS S2 S3 WB S1 ID ID ID I1 ID I2 Next instruction M3 M2 Issue rate 2 I1 ID I2 E g MAC W instruction Execution cycles indicates the cycle counts an instruction occupied the pipeline based on the next rules CPU instruction E g AND B instruction I1 I2 ID S1 S2 S3 WB Execution Cycles 3 E2S2 E3S3 WB E1S1 ID ID I1 I2 ID S1 S2 S3 WB MS S2 S3 WB S1 ID M3 M2 E g MAC W instruction Execution Cycles 4...

Page 77: ...S 1 1 3 1 11 MOV W Rm Rn LS 1 1 3 1 12 MOV L Rm Rn LS 1 1 3 1 13 MOV B Rm Rn LS 1 1 3 1 14 MOV W Rm Rn LS 1 1 3 1 15 MOV L Rm Rn LS 1 1 3 1 16 MOV B disp Rm R0 LS 1 1 3 1 17 MOV W disp Rm R0 LS 1 1 3 1 18 MOV L disp Rm Rn LS 1 1 3 1 19 MOV B R0 Rm Rn LS 1 1 3 1 20 MOV W R0 Rm Rn LS 1 1 3 1 21 MOV L R0 Rm Rn LS 1 1 3 1 22 MOV B disp GBR R0 LS 1 1 3 1 23 MOV W disp GBR R0 LS 1 1 3 1 24 MOV L disp GB...

Page 78: ... Rn CO 1 1 3 9 42 MOVLI L Rm R0 CO 1 1 3 8 43 MOVUA L Rm R0 LS 2 2 3 10 44 MOVUA L Rm R0 LS 2 2 3 10 45 MOVT Rn EX 1 1 2 1 46 OCBI Rn LS 1 1 3 4 47 OCBP Rn LS 1 1 3 4 48 OCBWB Rn LS 1 1 3 4 49 PREF Rn LS 1 1 3 4 50 SWAP B Rm Rn EX 1 1 2 1 51 SWAP W Rm Rn EX 1 1 2 1 Data transfer instructions 52 XTRCT Rm Rn EX 1 1 2 1 53 ADD Rm Rn EX 1 1 2 1 54 ADD imm Rn EX 1 1 2 1 55 ADDC Rm Rn EX 1 1 2 1 56 ADDV...

Page 79: ... 4 5 8 74 MUL L Rm Rn EX 1 2 5 6 75 MULS W Rm Rn EX 1 1 5 5 76 MULU W Rm Rn EX 1 1 5 5 77 NEG Rm Rn EX 1 1 2 1 78 NEGC Rm Rn EX 1 1 2 1 79 SUB Rm Rn EX 1 1 2 1 80 SUBC Rm Rn EX 1 1 2 1 Fixed point arithmetic instructions 81 SUBV Rm Rn EX 1 1 2 1 82 AND Rm Rn EX 1 1 2 1 83 AND imm R0 EX 1 1 2 1 84 AND B imm R0 GBR CO 3 3 3 2 85 NOT Rm Rn EX 1 1 2 1 86 OR Rm Rn EX 1 1 2 1 87 OR imm R0 EX 1 1 2 1 88 ...

Page 80: ...LL2 Rn EX 1 1 2 1 106 SHLL8 Rn EX 1 1 2 1 107 SHLL16 Rn EX 1 1 2 1 108 SHLR Rn EX 1 1 2 1 109 SHLR2 Rn EX 1 1 2 1 110 SHLR8 Rn EX 1 1 2 1 Shift instructions 111 SHLR16 Rn EX 1 1 2 1 112 BF disp BR 1 0 to 2 1 1 1 113 BF S disp BR 1 0 to 2 1 1 1 114 BT disp BR 1 0 to 2 1 1 1 115 BT S disp BR 1 0 to 2 1 1 1 116 BRA disp BR 1 0 to 2 1 1 1 117 BRAF Rm BR 1 3 1 1 2 118 BSR disp BR 1 0 to 2 1 1 1 119 BSR...

Page 81: ... 4 2 137 LDC Rm SGR CO 4 4 4 2 138 LDC Rm GBR LS 1 1 4 3 139 LDC Rm Rp_BANK LS 1 1 4 1 140 LDC Rm SR CO 4 3 4 4 4 141 LDC Rm SSR LS 1 1 4 1 142 LDC Rm SPC LS 1 1 4 1 143 LDC Rm VBR LS 1 1 4 1 144 LDC L Rm DBR CO 4 4 4 6 145 LDC L Rm SGR CO 4 4 4 6 146 LDC L Rm GBR LS 1 1 4 7 147 LDC L Rm Rp_BANK LS 1 1 4 5 148 LDC L Rm SR CO 6 3 4 4 8 149 LDC L Rm SSR LS 1 1 4 5 150 LDC L Rm SPC LS 1 1 4 5 151 LDC...

Page 82: ...L Rp_BANK Rn LS 1 1 4 11 170 STC L SR Rn CO 1 1 4 12 171 STC L SSR Rn LS 1 1 4 11 172 STC L SPC Rn LS 1 1 4 11 173 STC L VBR Rn LS 1 1 4 11 174 STS MACH Rn LS 1 1 5 3 175 STS MACL Rn LS 1 1 5 3 176 STS PR Rn LS 1 1 4 15 177 STS L MACH Rn LS 1 1 5 4 178 STS L MACL Rn LS 1 1 5 4 System control instructions 179 STS L PR Rn LS 1 1 4 16 180 FLDI0 FRn LS 1 1 6 13 181 FLDI1 FRn LS 1 1 6 13 182 FMOV FRm F...

Page 83: ...QRT FRn FE 1 30 6 15 201 FSUB FRm FRn FE 1 1 6 14 202 FTRC FRm FPUL FE 1 1 6 14 203 FMOV DRm DRn LS 1 1 6 9 204 FMOV Rm DRn LS 1 1 6 9 205 FMOV Rm DRn LS 1 1 6 9 206 FMOV R0 Rm DRn LS 1 1 6 9 207 FMOV DRm Rn LS 1 1 6 9 208 FMOV DRm Rn LS 1 1 6 9 Single precision floating point instructions 209 FMOV DRm R0 Rn LS 1 1 6 9 210 FABS DRn LS 1 1 6 12 211 FADD DRm DRn FE 1 1 6 16 212 FCMP EQ DRm DRn FE 1 ...

Page 84: ...1 1 6 2 228 STS FPSCR Rn LS 1 1 6 6 229 STS L FPUL Rn LS 1 1 6 4 FPU system control instructions 230 STS L FPSCR Rn LS 1 1 6 8 231 FMOV DRm XDn LS 1 1 6 9 232 FMOV XDm DRn LS 1 1 6 9 233 FMOV XDm XDn LS 1 1 6 9 234 FMOV Rm XDn LS 1 1 6 9 235 FMOV Rm XDn LS 1 1 6 9 236 FMOV R0 Rm XDn LS 1 1 6 9 237 FMOV XDm Rn LS 1 1 6 9 238 FMOV XDm Rn LS 1 1 6 9 239 FMOV XDm R0 Rn LS 1 1 6 9 240 FIPR FVm FVn FE 1...

Page 85: ... three kinds resets general exceptions and interrupts 5 2 Register Descriptions Table 5 1 lists the configuration of registers related exception handling Table 5 1 Register Configuration Register Name Abbr R W P4 Address Area 7 Address Access Size TRAPA exception register TRA R W H FF00 0020 H 1F00 0020 32 Exception event register EXPEVT R W H FF00 0024 H 1F00 0024 32 Interrupt event register INTE...

Page 86: ... 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W R W R W TRACODE R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 R R R R R R R W R W Bit Bit Name Initial Value R W Description 31 to 10 All 0 R Reserved For details on reading writing this bit see General Precautions on Handling of Product 9 to 2 TRACODE Undefine d R W TRAPA Code 8 bit imme...

Page 87: ...4 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W R W EXPCODE R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 R R R R R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 12 All 0 R Reserved For details on reading writing this bit see General Precautio...

Page 88: ... 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R W INTCODE R W R W R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 R R R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 14 All 0 R Reserved For details on reading writing this bit see General Precautions on Handling of Product 13 to 0 INTCODE ...

Page 89: ... SR and R15 contents are saved in SPC SSR and SGR respectively 2 The block bit BL in SR is set to 1 3 The mode bit MD in SR is set to 1 4 The register bank bit RB in SR is set to 1 5 In a reset the FPU disable bit FD in SR is cleared to 0 6 The exception code is written to bits 11 to 0 of the exception event register EXPEVT or interrupt event register INTEVT 7 The CPU branches to the determined ex...

Page 90: ... H 0E0 Instruction TLB miss exception 2 2 VBR H 400 H 040 Instruction TLB protection violation exception 2 3 VBR H 100 H 0A0 General illegal instruction exception 2 4 VBR H 100 H 180 Slot illegal instruction exception 2 4 VBR H 100 H 1A0 General FPU disable exception 2 4 VBR H 100 H 800 Slot FPU disable exception 2 4 VBR H 100 H 820 Data address error read 2 5 VBR H 100 H 0E0 Data address error wr...

Page 91: ...Interrupt Completion type General interrupt request 4 VBR H 600 Note 1 When UBDE in CBCR 1 PC DBR In other cases PC VBR H 100 2 Priority is first assigned by priority level then by priority order within each level the lowest number represents the highest priority 3 Control passes to H A000 0000 in a reset and to VBR offset in other cases 4 Stored in EXPEVT for a reset or general exception and in I...

Page 92: ...tion of Exceptions Also see section 5 6 4 Priority Order with Multiple Exceptions for exception handling during execution of a delayed branch instruction and a delay slot instruction or in the case of instructions in which two data accesses are performed Execute next instruction Is highest priority exception re exception type Cancel instruction execution result Yes Yes Yes No No No No Yes SSR SR S...

Page 93: ... accepted before that for a later instruction An example of the order of acceptance for general exceptions is shown in figure 5 2 I1 I1 ID ID E3 WB WB TLB miss data access Pipeline flow Order of detection Instruction n Instruction n 1 General illegal instruction exception instruction n 1 and TLB miss instruction n 2 are detected simultaneously Order of exception handling TLB miss instruction n Pro...

Page 94: ...terrupt request is held pending and is accepted after the BL bit has been cleared to 0 by software If a nonmaskable interrupt NMI occurs it can be held pending or accepted according to the setting made by software Thus normally SPC and SSR are saved and then the BL bit in SR is cleared to 0 to enable multiple exception state acceptance 5 5 4 Return from Exception Handling The RTE instruction is us...

Page 95: ...r is supplied Manual Reset Condition Manual reset request Operations Exception code H 020 is set in EXPEVT initialization of the CPU and on chip peripheral module is carried out and then a branch is made to the branch vector H A0000000 The registers initialized by a power on reset and manual reset are different For details see the register descriptions in the relevant sections H UDI Reset Source S...

Page 96: ...l reset For details see the register descriptions in the relevant sections of the hardware manual of the target product Data TLB Multiple Hit Exception Source Multiple UTLB address matches Transition address H A0000000 Transition operations The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH ...

Page 97: ...on occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 040 for a read access or H 060 for a write access is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate from that of other exc...

Page 98: ...es the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 40 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0400 To speed up TLB miss processing the offset is separate from that of other exceptions ITLB_miss_...

Page 99: ...s set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 080 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Initial_write_exception TEA EXCEPTION_ADDRESS PTEH VPN...

Page 100: ...ts at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 for a read access or H 0C0 for a write access is ...

Page 101: ...curred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0A0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made...

Page 102: ...n operations The virtual address 32 bits at which this exception occurred is set in TEA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 for a read ...

Page 103: ...EA and the corresponding virtual page number 22 bits is set in PTEH 31 10 ASID in PTEH indicates the ASID when this exception occurred The PC and SR contents for the instruction at which this exception occurred are saved in the SPC and SSR The R15 contents at this time are saved in SGR Exception code H 0E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0...

Page 104: ... instruction are saved in SPC The value of SR and R15 when the TRAPA instruction is executed are saved in SSR and SGR The 8 bit immediate value in the TRAPA instruction is multiplied by 4 and the result is set in TRA 9 0 Exception code H 160 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 TRAPA_exception SPC PC 2 SSR SR SGR R15 TRA imm 2 EXPEVT H 000...

Page 105: ...ding LDC STC instructions that access GBR Transition address VBR H 00000100 Transition operations The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 180 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Operation is not guaranteed if an und...

Page 106: ...uctions LDC STC RTE LDTLB SLEEP but excluding LDC STC instructions that access GBR Decoding of a PC relative MOV instruction or MOVA instruction in a delay slot Transition address VBR H 000 0100 Transition operations The PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 1A0 is set...

Page 107: ...he R15 contents at this time are saved in SGR Exception code H 800 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Note FPU instructions are instructions in which the first 4 bits of the instruction code are F but excluding undefined instruction H FFFD and the LDS STS LDS L and STS L instructions corresponding to FPUL and FPSCR General_fpu_disable_ex...

Page 108: ...e PC contents for the preceding delayed branch instruction are saved in SPC The SR and R15 contents when this exception occurred are saved in SSR and SGR Exception code H 820 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 Slot_fpu_disable_exception SPC PC 2 SSR SR SGR R15 EXPEVT H 0000 0820 SR MD 1 SR RB 1 SR BL 1 PC VBR H 0000 0100 ...

Page 109: ...reak the PC contents for the instruction at which the breakpoint is set are set in SPC The SR and R15 contents when the break occurred are saved in SSR and SGR Exception code H 1E0 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 It is also possible to branch to PC DBR For details of PC etc when a data break is set see the User Break Controller UBC se...

Page 110: ...s The PC and SR contents for the instruction at which this exception occurred are saved in SPC and SSR The R15 contents at this time are saved in SGR Exception code H 120 is set in EXPEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0100 FPU_exception SPC PC SSR SR SGR R15 EXPEVT H 0000 0120 SR MD 1 SR RB 1 SR BL 1 PC VBR H 0000 0100 ...

Page 111: ...ode H 1C0 is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to PC VBR H 0600 When the BL bit in SR is 0 this interrupt is not masked by the interrupt mask bits in SR and is accepted at the highest priority level When the BL bit in SR is 1 a software setting can specify whether this interrupt is to be masked or accepted For details see the Interrupt Controller section o...

Page 112: ...rupt source is set in INTEVT The BL MD and RB bits are set to 1 in SR and a branch is made to VBR H 0600 For details see the Interrupt Controller section of the hardware manual of the target product Module_interruption SPC PC SSR SR SGR R15 INTEVT H 0000 0400 H 0000 3FE0 SR MD 1 SR RB 1 SR BL 1 if cond SR IMASK level_of accepted_interrupt PC VBR H 0000 0600 5 6 4 Priority Order with Multiple Excep...

Page 113: ...ion has only one data transfer 1 A check is performed for the interrupt type and re execution type exceptions of priority levels 1 and 2 in the delayed branch instruction 2 A check is performed for the interrupt type and re execution type exceptions of priority levels 1 and 2 in the delay slot instruction 3 A check is performed for the completion type exception of priority level 2 in the delayed b...

Page 114: ...ruction at which the exception occurred is set in SPC and the instruction is re executed after returning from the exception handling routine If an exception occurs in a delay slot instruction however the PC value for the delayed branch instruction is saved in SPC regardless of whether or not the preceding delay slot instruction condition is satisfied B Completion type exception or interrupt The PC...

Page 115: ...changed SR value starting from the next instruction In the completion type exception an exception is accepted after the next instruction has been executed However an interrupt of completion type exception is accepted before the next instruction is executed Note When the LDC instruction for SR is executed following instructions are fetched again and the instruction fetch exception is evaluated agai...

Page 116: ...Rev 1 50 10 04 page 96 of 448 ...

Page 117: ...n modes Flush to Zero and Treat Denormalized Number Six exception sources FPU Error Invalid Operation Divide By Zero Overflow Underflow and Inexact Comprehensive instructions Single precision double precision graphics support and system control Following three instructions are added in the SH 4A FSRRA FSCA and FPCHG When the FD bit in SR is set to 1 the FPU cannot be used and an attempt to execute...

Page 118: ...3 22 0 Figure 6 1 Format of Single Precision Floating Point Number 63 s e f 62 52 51 0 Figure 6 2 Format of Double Precision Floating Point Number The exponent is expressed in biased form as follows e E bias The range of unbiased exponent E is Emin 1 to Emax 1 The two values Emin 1 and Emax 1 are distinguished as follows Emin 1 indicates zero both positive and negative sign and a denormalized numb...

Page 119: ...e v is determined as follows If E Emax 1 and f 0 v is a non number NaN irrespective of sign s If E Emax 1 and f 0 v 1 s infinity positive or negative infinity If Emin E Emax v 1 s 2E 1 f normalized number If E Emin 1 and f 0 v 1 s 2Emin 0 f denormalized number If E Emin 1 and f 0 v 1 s 0 positive or negative zero Table 6 2 shows the ranges of the various numbers in hexadecimal notation For the sig...

Page 120: ... Positive denormalized number H 007F FFFF to H 0000 0001 H 000F FFFF FFFF FFFF to H 0000 0000 0000 0001 Positive zero H 0000 0000 H 0000 0000 0000 0000 Negative zero H 8000 0000 H 8000 0000 0000 0000 Negative denormalized number H 8000 0001 to H 807F FFFF H 8000 0000 0000 0001 to H 800F FFFF FFFF FFFF Negative normalized number H 8080 0000 to H FF7F FFFF H 8010 0000 0000 0000 to H FFEF FFFF FFFF F...

Page 121: ... FPSCR is 0 the operation result output is a qNaN When the EN V bit in FPSCR is 1 an invalid operation exception will be generated In this case the contents of the operation destination register are unchanged Following three instructions are used as transfer instructions between registers FMOV FRm FRn FLDS FRm FPUL FSTS FPUL FRn If a qNaN is input in an operation that generates a floating point va...

Page 122: ...ized number source operand or operation result is always positive or negative zero in a floating point operation that generates a value an operation other than transfer instructions between registers FNEG or FABS When the DN bit in FPSCR is 0 a denormalized number source operand or operation result is processed as it is See section 10 Instruction Descriptions for details of floating point operatio...

Page 123: ... allocated to FPR0_BANK0 to FPR15_BANK0 when FPSCR FR 1 FR0 to FR15 are allocated to FPR0_BANK1 to FPR15_BANK1 3 Double precision floating point registers DRi 8 registers A DR register comprises two FR registers DR0 FR0 FR1 DR2 FR2 FR3 DR4 FR4 FR5 DR6 FR6 FR7 DR8 FR8 FR9 DR10 FR10 FR11 DR12 FR12 FR13 DR14 FR14 FR15 4 Single precision floating point vector registers FVi 4 registers An FV register c...

Page 124: ...13 XF14 XF15 FR0 FR1 FR2 FR3 FR4 FR5 FR6 FR7 FR8 FR9 FR10 FR11 FR12 FR13 FR14 FR15 DR0 DR2 DR4 DR6 DR8 DR10 DR12 DR14 FV0 FV4 FV8 FV12 XD0 XMTRX XD2 XD4 XD6 XD8 XD10 XD12 XD14 FPR0 BANK1 FPR1 BANK1 FPR2 BANK1 FPR3 BANK1 FPR4 BANK1 FPR5 BANK1 FPR6 BANK1 FPR7 BANK1 FPR8 BANK1 FPR9 BANK1 FPR10 BANK1 FPR11 BANK1 FPR12 BANK1 FPR13 BANK1 FPR14 BANK1 FPR15 BANK1 XF0 XF1 XF2 XF3 XF4 XF5 XF6 XF7 XF8 XF9 XF...

Page 125: ... FPR15_BANK0 are assigned to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 are assigned to XF0 to XF15 1 FPR0_BANK0 to FPR15_BANK0 are assigned to XF0 to XF15 and FPR0_BANK1 to FPR15_BANK1 are assigned to FR0 to FR15 20 SZ 0 R W Transfer Size Mode 0 Data size of FMOV instruction is 32 bits 1 Data size of FMOV instruction is a 32 bit register pair 64 bits For relations between endian and the SZ and PR ...

Page 126: ... 6 3 1 0 RM1 RM0 0 1 R W R W Rounding Mode These bits select the rounding mode 00 Round to Nearest 01 Round to Zero 10 Reserved 11 Reserved Big endian DR 2i FR 2i FR 2i 1 8n 4 8n 7 8n 8n 3 63 0 63 32 31 0 Floating point register Memory area 63 0 Little endian Floating point register Memory area DR 2i FR 2i FR 2i 1 4n 4m 4n 3 4m 3 63 0 63 32 31 0 DR 2i FR 2i 1 FR 2i 8n 4 8n 7 8n 3 8n 63 0 63 32 31 ...

Page 127: ...10 Bit 9 Bit 8 Bit 7 Flag FPU exception flag field None Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 6 3 3 Floating Point Communication Register FPUL Information is transferred between the FPU and CPU via FPUL FPUL is a 32 bit system register that is accessed from the CPU side by means of LDS and STS instructions For example to convert the integer stored in general register R1 to a single precision floating poin...

Page 128: ... 00 Round to Nearest FPSCR RM 1 0 01 Round to Zero Round to Nearest The operation result is rounded to the nearest expressible value If there are two nearest expressible values the one with an LSB of 0 is selected If the unrounded value is 2Emax 2 2 P or more the result will be infinity with the same sign as the unrounded value The values of Emax and P respectively are 127 and 24 for single precis...

Page 129: ...vision by zero Z Division with a zero divisor Overflow O When the operation result overflows Underflow U When the operation result underflows Inexact exception I When overflow underflow or rounding occurs The FPU exception cause field in FPSCR contains bits corresponding to all of above sources E V Z O U and I and the FPU exception flag and enable fields in FPSCR contain bits corresponding to sour...

Page 130: ...ned by software by reading from FPSCR and interpreting the information it contains Also the destination register is not changed by any FPU exception handling operation If the FPU exception sources except for above are generated the bit corresponding to source V Z O U or I is set to 1 and a default value is generated as the operation result Invalid operation V qNaN is generated as the result Divisi...

Page 131: ... error is guaranteed but the same result between different processor cores is not guaranteed FIPR FVm FVn m n 0 4 8 12 This instruction is basically used for the following purposes Inner product m n This operation is generally used for surface rear surface determination for polygon surfaces Sum of square of elements m n This operation is generally used to find the length of a vector Since an inexa...

Page 132: ...ranslation matrix it is easier to use registers in the foreground bank When the LDS instruction is used on FPSCR this instruction takes four to five cycles in order to maintain the FPU state With the FRCHG instruction the FR bit in FPSCR can be changed in one cycle 6 6 2 Pair Single Precision Data Transfer In addition to the powerful new geometric operation instructions the SH 4A also supports hig...

Page 133: ...aving this mapping onto physical memory executed consciously by the process itself imposes a heavy burden on the process The virtual memory system was devised as a means of handling all physical memory mapping to reduce this burden 2 in figure 7 1 With a virtual memory system the size of the available virtual memory is much larger than the actual physical memory and processes are mapped onto this ...

Page 134: ...vided by hardware and frequently used address translation information is placed here The TLB can be described as a cache for address translation information However unlike a cache if address translation fails that is if an exception occurs switching of the address translation information is normally performed by software Thus memory management can be performed in a flexible manner by software Ther...

Page 135: ...r mode a 2 Gbyte space in the U0 area can be accessed When the SQMD bit in the MMU control register MMUCR is 0 a 64 Mbyte space in the store queue area can be accessed When the RMD bit in the on chip memory control register RAMCR is 1 a 16 Mbyte space in on chip memory area can be accessed Accessing areas other than the U0 area store queue area and on chip memory area in user mode will cause an ad...

Page 136: ...Space AT in MMUCR 0 Area 0 Area 1 Area 2 Area 3 Area 4 Area 5 Area 6 Area 7 Physical address space 256 256 U0 area Cacheable Address translation possible Address error Address error On chip memory area Address error Store queue area P0 area Cacheable Address translation possible User mode Privileged mode P1 area Cacheable Address translation not possible P2 area Non cacheable Address translation n...

Page 137: ...e mapped onto the control register area which is allocated in the area 7 in physical address space by means of the TLB the C bit for the corresponding page must be cleared to 0 P1 Area The P1 area does not allow address translation using the TLB but can be accessed using the cache Regardless of whether the MMU is enabled or disabled clearing the upper 3 bits of an address to 0 gives the correspond...

Page 138: ... Store Queues The area from H E500 0000 to H E5FF FFFF comprises addresses for accessing the on chip memory In user mode the access right is specified by the RMD bit in RAMCR For details see section 9 L Memory The area from H F000 0000 to H F0FF FFFF is used for direct access to the instruction cache address array For details see section 8 6 1 IC Address Array The area from H F100 0000 to H F1FF F...

Page 139: ...PMB Configuration The area from H FC00 0000 to H FFFF FFFF is the on chip peripheral module control register area For details see register descriptions in each section of the hardware manual of the target product Physical Address Space The SH 4A supports a 29 bit physical address space The physical address space is divided into eight areas as shown in figure 7 5 Area 7 is a reserved area For detai...

Page 140: ...return from the exception handling routine the instruction which caused the TLB miss exception is re executed Single Virtual Memory Mode and Multiple Virtual Memory Mode There are two virtual memory systems single virtual memory and multiple virtual memory either of which can be selected with the SV bit in MMUCR In the single virtual memory system a number of processes run simultaneously using vir...

Page 141: ...W H FF00 0078 H 1F00 0078 32 Note These P4 addresses are for the P4 area in the virtual address space These area 7 addresses are accessed from area 7 in the physical address space by means of the TLB Table 7 2 Register States in Each Processing State Register Name Abbreviation Power on Reset Manual Reset Sleep Standby Page table entry high register PTEH Undefined Undefined Retained Retained Page t...

Page 142: ...In this case the branch destination may be the P0 P3 or U0 area 2 Execute the ICBI instruction for any address including non cacheable area 3 If the R2 bit in IRMCR is 0 initial value before updating the ASID field the specific instruction does not need to be executed However note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next inst...

Page 143: ... W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 28 to 10 PPN R W Physical Page Number 9 0 R Reserved For details on reading from or writing to this bit see des...

Page 144: ...W TTB TTB R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R W R W R W R W R W R W R W R W 7 2 4 TLB Exception Address Register TEA After an MMU exception or address error exception occurs the virtual address at which the exception occurred is stored The contents of this register can be changed by software 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0...

Page 145: ...c instruction does not need to be executed However note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after MMUCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series...

Page 146: ...ted by an ITLB miss Ensure that values for which Setting prohibited is indicated below are not set at the discretion of software After a power on or manual reset the LRUI bits are initialized to 0 and therefore a prohibited setting is never made by a hardware update x means don t care 111xxx ITLB entry 0 is updated 0xx11x ITLB entry 1 is updated x0x0x1 ITLB entry 2 is updated xx0x00 ITLB entry 3 i...

Page 147: ... access possible address error exception in case of user access 8 SV 0 R W Single Virtual Memory Mode Multiple Virtual Memory Mode Switching Bit When this bit is changed ensure that 1 is also written to the TI bit 0 Multiple virtual memory mode 1 Single virtual memory mode 7 to 3 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handlin...

Page 148: ...s see description in General Precautions on Handling of Product 7 to 0 UB All 0 R W Buffered Write Control for Each Area 64 Mbytes When writing is performed without using the cache or in the cache write through mode these bits specify whether the next bus access from the CPU waits for the end of writing for each area 0 The CPU does not wait for the end of writing bus access and starts the next bus...

Page 149: ...s on the specific sequence see descriptions in each resource 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Initial value R R R R R R R R R R R R R R R R R R2 R1 LT MT MC R R R W R W R W R W R W R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 R R R R R R R R Bit Bit Name Initial Value R W Description 31 to 5 All 0...

Page 150: ... W Re Fetch Inhibit after Writing Memory Mapped TLB This bit controls whether re fetch is performed for the next instruction after writing memory mapped ITLB UTLB while the AT bit in MMUCR is set to 1 0 Re fetch is performed 1 Re fetch is not performed 0 MC 0 R W Re Fetch Inhibit after Writing Memory Mapped IC This bit controls whether re fetch is performed for the next instruction after writing m...

Page 151: ... of 64 fully associative type entries Figure 7 7 shows the relationship between the page size and address format PPN 28 10 PPN 28 10 PPN 28 10 SZ 1 0 SZ 1 0 SZ 1 0 SH SH SH C C C PR 1 0 PR 1 0 PR 1 0 ASID 7 0 ASID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 V V V Entry 0 Entry 1 Entry 2 D D D WT WT WT PPN 28 10 SZ 1 0 SH C PR 1 0 ASID 7 0 VPN 31 10 V Entry 63 D WT Figure 7 6 UTLB Configuration Lege...

Page 152: ...re valid With a 4 Kbyte page PPN 28 12 are valid With a 64 Kbyte page PPN 28 16 are valid With a 1 Mbyte page PPN 28 20 are valid The synonym problem must be taken into account when setting the PPN see section 7 4 5 Avoiding Synonym Problems PR 1 0 Protection key data 2 bit data expressing the page access right as a code 00 Can be read from only in privileged mode 01 Can be read from and written t...

Page 153: ...et PPN Offset PPN Offset Figure 7 7 Relationship between Page Size and Address Format 7 3 2 Instruction TLB ITLB Configuration The ITLB is used to translate a virtual address to a physical address in an instruction access Information in the address translation table located in the UTLB is cached into the ITLB Figure 7 8 shows the ITLB configuration The ITLB consists of four fully associative type ...

Page 154: ...al address VA VA is in P4 area VA is in P2 area VA is in P1 area VA is in P0 U0 or P3 area MMUCR AT 1 SH 0 and MMUCR SV 0 or SR MD 0 VPNs match ASIDs match and V 1 Only one entry matches 1 Privileged Data TLB multiple hit exception Data TLB protection violation exception Data TLB miss exception 0 User VPNs match and V 1 Data TLB protection violation exception Initial page write exception Cache acc...

Page 155: ...in P1 area VA is in P0 U0 or P3 area MMUCR AT 1 SH 0 and MMUCR SV 0 or SR MD 0 VPNs match and V 1 VPNs match ASIDs match and V 1 Only one entry matches SR MD Instruction TLB multiple hit exception 0 User 1 Privileged PR C 1 and CCR ICE 1 Cache access Memory access Non cacheable Instruction TLB protection violation exception Instruction TLB miss exception Hardware ITLB miss handling Search UTLB Mat...

Page 156: ...tion access the MMU searches the UTLB If the necessary address translation information is recorded in the UTLB the MMU copies this information into the ITLB in accordance with the LRUI bit setting in MMUCR 7 4 2 MMU Software Management Software processing for the MMU consists of the following 1 Setting of MMU related registers Some registers are also partially updated by hardware automatically 2 R...

Page 157: ... methods before an access include an instruction fetch the area where TLB is used to translate the address is performed 1 Execute a branch using the RTE instruction In this case the branch destination may be the area where TLB is used to translate the address 2 Execute the ICBI instruction for any address including non cacheable area 3 If the LT bit in IRMCR is 0 initial value before executing the...

Page 158: ...ID 7 0 ASID 7 0 VPN 31 10 VPN 31 10 VPN 31 10 V V V Entry 0 Entry 1 Entry 2 D D D WT WT WT PPN 28 10 SZ 1 0 SH C PR 1 0 ASID 7 0 VPN 31 10 V Entry 63 D WT 31 2928 9 8 7 6 5 4 3 2 1 0 V SZ1 PR 1 0 SZ0 C D SH WT PTEL Write UTLB 31 10 9 8 7 0 ASID PTEH 31 26252423 18171615 10 9 8 7 3 2 1 0 LRUI URB URC SV TI AT MMUCR VPN 10 PPN Entry specification SQMD Figure 7 11 Operation of LDTLB Instruction ...

Page 159: ... of the virtual address in the case of a 1 Kbyte page and bit 12 of the virtual address in the case of a 4 Kbyte page are subject to address translation As a result bits 12 to 10 of the physical address after translation may differ from bits 12 to 10 of the virtual address Consequently the following restrictions apply to the recording of address translation information in UTLB entries When address...

Page 160: ...ction access has been made If multiple hits occur when the UTLB is searched by hardware in hardware ITLB miss handling an instruction TLB multiple hit exception will result When an instruction TLB multiple hit exception occurs a reset is executed and cache coherency is not guaranteed Hardware Processing In the event of an instruction TLB multiple hit exception hardware carries out the following pr...

Page 161: ...t in SR to 1 and switches to privileged mode 7 Sets the BL bit in SR to 1 and masks subsequent exception requests 8 Sets the RB bit in SR to 1 9 Branches to the address obtained by adding offset H 0000 0400 to the contents of VBR and starts the instruction TLB miss exception handling routine Software Processing Instruction TLB Miss Exception Handling Routine Software is responsible for searching t...

Page 162: ...he PC value indicating the address of the instruction at which the exception occurred in SPC If the exception occurred at a delay slot sets the PC value indicating the address of the delayed branch instruction in SPC 5 Sets the SR contents at the time of the exception in SSR The R15 contents at this time are saved in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bi...

Page 163: ...r the virtual address to which a data access is made is not found in the UTLB entries The data TLB miss exception processing carried out by hardware and software is shown below Hardware Processing In the event of a data TLB miss exception hardware carries out the following processing 1 Sets the VPN of the virtual address at which the exception occurred in PTEH 2 Sets the virtual address at which t...

Page 164: ...LB entry contains address translation information matching the virtual address to which a data access is made the actual access type is not permitted by the access right specified by the PR bit The data TLB protection violation exception processing carried out by hardware and software is shown below Hardware Processing In the event of a data TLB protection violation exception hardware carries out ...

Page 165: ...uction at which the exception occurred in SPC If the exception occurred at a delay slot sets the PC value indicating the address of the delayed branch instruction in SPC 5 Sets the SR contents at the time of the exception in SSR The R15 contents at this time are saved in SGR 6 Sets the MD bit in SR to 1 and switches to privileged mode 7 Sets the BL bit in SR to 1 and masks subsequent exception req...

Page 166: ...ruction for any address including non cacheable area 3 If the MT bit in IRMCR is 0 initial value before accessing the memory mapped TLB the specific instruction does not need to be executed However note that the CPU processing performance will be lowered because the instruction fetch is performed again for the next instruction after MMUCR has been updated Note that the method 3 may not be guarante...

Page 167: ...s is used 0 should be specified for address field bits 1 0 In the data field bits 31 10 indicate VPN bit 8 indicates V and bits 7 0 indicate ASID The following two kinds of operation can be used on the ITLB address array 1 ITLB address array read VPN V and ASID are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB address array write VPN V and ...

Page 168: ...V bits 7 and 4 indicate SZ bit 6 indicates PR bit 3 indicates C and bit 1 indicates SH The following two kinds of operation can be used on ITLB data array 1 ITLB data array read PPN V SZ PR C and SH are read into the data field from the ITLB entry corresponding to the entry set in the address field 2 ITLB data array write PPN V SZ PR C and SH specified in the data field are written to the ITLB ent...

Page 169: ...e address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 UTLB address array write non associative VPN D V and ASID specified in the data field are written to the UTLB entry corresponding to the entry set in the address field The A bit in the address field should be cleared to 0 3 UTLB address array write a...

Page 170: ...electing the entry to be accessed is specified in the address field and PPN V SZ PR C D SH and WT to be written to data array are specified in the data field In the address field bits 31 20 have the value H F70 indicating UTLB data array and the entry is specified by bits 13 8 In the data field bits 28 10 indicate PPN bit 8 indicates V bits 7 and 4 indicate SZ bits 6 5 indicate PR bit 3 indicates ...

Page 171: ...ed UTLB Data Array 7 7 32 Bit Address Extended Mode Setting the SE bit in PASCR to 1 changes mode from 29 bit address mode which handles the 29 bit physical address space to 32 bit address extended mode which handles the 32 bit physical address space P1 0 5 Gbyte P1 P2 1 Gbyte 0 5 Gbyte 4 Gbytes U0 P0 2 Gbytes U0 P0 2 Gbytes P2 0 5 Gbyte P3 0 5 Gbyte P3 0 5 Gbyte P4 0 5 Gbyte P4 0 5 Gbyte Virtual ...

Page 172: ...MU operates as follows 1 When the AT bit in MMUCR is 0 virtual addresses in the U0 P0 or P3 area become 32 bit physical addresses Addresses in the P1 or P2 area are translated according to the PMB mapping information 2 When the AT bit in MMUCR is 1 virtual addresses in the U0 P0 or P3 area are translated to 32 bit physical addresses according to the TLB conversion information Addresses in the P1 o...

Page 173: ... page V Validity bit Indicates whether the entry is valid 0 Invalid 1 Valid Cleared to 0 by a power on reset Not affected by a manual reset PPN Physical page number Upper 8 bits of the physical address of the physical page number With a 16 Mbyte page PPN 31 24 are valid With a 64 Mbyte page PPN 31 26 are valid With a 128 Mbyte page PPN 31 27 are valid With a 512 Mbyte page PPN 31 29 are valid C Ca...

Page 174: ... associative write function 5 Since there is no PR field in the PMB read write protection cannot be preformed The address translation target of the PMB is the P1 or P2 address In user mode access an address error exception occurs 6 Both entries from the UTLB and PMB are mixed and recorded in the ITLB by means of the hardware ITLB miss handling However these entries can be identified by checking wh...

Page 175: ...ata array and bits 11 to 8 in the address field as an entry bits 31 to 24 in the data field are read as PPN bit 9 in the data field as UB bit 8 in the data field as V bits 7 and 4 in the data field as SZ bit 3 in the data field as C and bit 0 in the data field as WT 4 PMB data array write When memory writing is performed while bits 31 to 20 in the address field are specified as H F71 which indicat...

Page 176: ... to the P1 or P2 area the UB bit in the PMB controls whether a buffered write is performed or not When the MMU is enabled the UB bit in the TLB controls writing to the P0 P3 or U0 area When the MMU is disabled writing to the P0 P3 or U0 area is always performed as a buffered write Bit Bit Name Initial Value R W Description 31 SE 0 R W 0 29 bit address mode 1 32 bit address extended mode 30 to 8 Al...

Page 177: ...rol Register 0 QACR0 and 8 2 3 Queue Address Control Register 1 QACR1 LSA0 LSA1 LDA0 LDA1 L0SADR L1SADR L0DADR and L1DADR fields are extended to bits 31 to 10 See section 9 2 2 L Memory Transfer Source Address Register 0 LSA0 section 9 2 3 L Memory Transfer Source Address Register 1 LSA1 section 9 2 4 L Memory Transfer Destination Address Register 0 LDA0 and section 9 2 5 L Memory Transfer Destina...

Page 178: ...Rev 1 50 10 04 page 158 of 448 ...

Page 179: ... Table 8 1 Cache Features Item Instruction Cache Operand Cache Capacity 32 Kbyte cache 32 Kbyte cache Type 4 way set associative virtual address index physical address tag 4 way set associative virtual address index physical address tag Line size 32 bytes 32 bytes Entries 256 entries way 256 entries way Write method Copy back write through selectable Replacement method LRU least recently used algo...

Page 180: ...e lines Figure 8 2 shows the configuration of the instruction cache 31 5 4 2 LW0 32 bits LW1 32 bits LW2 32 bits LW3 32 bits LW4 32 bits LW5 32 bits LW6 32 bits LW7 32 bits 6 bits MMU 12 5 255 19 bits 1 bit 1 bit Tag U V Address array way 0 to way 3 Data array way 0 to way3 LRU Entry selection Longword LW selection Virtual address 3 8 22 19 0 Write data Read data Hit signal Way 0 to way 3 12 10 0 ...

Page 181: ...on or manual reset V bit validity bit Indicates that valid data is stored in the cache line When this bit is 1 the cache line data is valid The V bit is initialized to 0 by a power on reset but retains its value in a manual reset U bit dirty bit The U bit is set to 1 if data is written to the cache line while the cache is being used in copy back mode That is the U bit indicates a mismatch between ...

Page 182: ...ed to cache Table 8 3 Register Configuration Register Name Abbreviation R W P4 Address Area 7 Address Size Cache control register CCR R W H FF00 001C H 1F00 001C 32 Queue address control register 0 QACR0 R W H FF00 0038 H 1F00 0038 32 Queue address control register 1 QACR1 R W H FF00 003C H 1F00 003C 32 On chip memory control register RAMCR R W H FF00 0074 H 1F00 0074 32 Note These P4 addresses ar...

Page 183: ...performance will be lowered because the instruction fetch is performed again for the next instruction after CCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 184: ...eral Precautions on Handling of Product 3 OCI 0 R W OC Invalidation Bit When 1 is written to this bit the V and U bits of all OC entries are cleared to 0 This bit is always read as 0 2 CB 0 R W Copy Back Bit Indicates the P1 area cache write mode 0 Write through mode 1 Copy back mode 1 WT 0 R W Write Through Mode Indicates the P0 U0 and P3 area cache write mode When address translation is performe...

Page 185: ...R R R R R R R R R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AREA0 Bit Bit Name Initial Value R W Description 31 to 5 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 4 to 2 AREA0 Undefined R W When the MMU is disabled these bits generate physical address bits 28 26 for SQ0 1 0 All...

Page 186: ...R R R R R R R R R W R W R W R R R W Bit Initial value R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AREA1 Bit Bit Name Initial Value R W Description 31 to 5 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 4 to 2 AREA1 Undefined R W When the MMU is disabled these bits generate physical address bits 28 26 for SQ1 1 0 All...

Page 187: ...ered because the instruction fetch is performed again for the next instruction after RAMCR has been updated Note that the method 3 may not be guaranteed in the future SuperH Series Therefore it is recommended that the method 1 or 2 should be used for being compatible with the future SuperH Series 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit Initial value R R R R R R R R R R RMD RP IC2W OC2W...

Page 188: ...is a two way operation For details see section 8 4 3 IC Two Way Mode 6 OC2W 0 R W OC Two Way Mode bit 0 OC is a four way operation 1 OC is a two way operation For details see section 8 3 6 OC Two Way Mode 5 to 0 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product ...

Page 189: ...ing the wraparound method in order from the quad word data 8 bytes including the cache missed data When the corresponding data arrives in the cache the read data is returned to the CPU While the remaining data on the cache line is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to the physical address is recorded in the cache 1...

Page 190: ...ess Data reading is performed using the wraparound method in order from the quad word data 8 bytes including the cache missed data In the prefetch operation the CPU doesn t wait the data arrives While the one cache line of data is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to the physical address is recorded in the cache 1...

Page 191: ...tten to the U bit The LRU bits are updated to indicate the way is the latest one 4 Cache hit write through A data write in accordance with the access size is performed for the data field on the hit way which is indexed by virtual address bits 4 0 A write is also performed to external memory corresponding to the virtual address Then the LRU bits are updated to indicate the way is the latest one In ...

Page 192: ...is latest one Then the data in the write back buffer is then written back to external memory 7 Cache miss write through A write of the specified access size is performed to the external memory corresponding to the virtual address In this case a write to cache is not performed 8 3 4 Write Back Buffer In order to give priority to data reads to the cache and improve performance the SH 4A has a write ...

Page 193: ...mpared with bits 28 10 of the physical address resulting from virtual address translation by the MMU If there is a way whose tag matches and the V bit is 1 see No 3 If there is no way whose tag matches and the V bit is 1 see No 4 3 Cache hit The data indexed by virtual address bits 4 2 is read as an instruction from the data field on the hit way The LRU bits are updated to indicate the way is the ...

Page 194: ...e virtual address Data reading is performed using the wraparound method in order from the quad word data 8 bytes including the cache missed data In the prefetch operation the CPU doesn t wait the data arrived While the one cache line of data is being read the CPU can execute the next processing When reading of one line of data is completed the tag corresponding to the physical address is recorded ...

Page 195: ... allocate instruction MOVCA L R0 Rn Operand cache allocation Instruction cache invalidate instruction ICBI Rn Instruction cache invalidation Operand access synchronization instruction SYNCO Wait for data transfer completion The operand cache can receive PURGE and FLUSH transaction from SuperHyway bus to control the cache coherency Since the address used by the PURGE and FLUSH transaction is a phys...

Page 196: ...vileged mode Operation is not guaranteed if access is made from a program in another area In this case execute one of the following three methods for executing a branch to the P0 U0 P1 or P3 area 1 Execute a branch using the RTE instruction 2 Execute a branch to the P0 U0 P1 or P3 area after executing the ICBI instruction for any address including non cacheable area 3 If the MC bit in IRMCR is 0 i...

Page 197: ...nding to the way and entry set in the address field In a read associative operation is not performed regardless of whether the association bit specified in the address field is 1 or 0 2 IC address array write non associative The tag and V bit specified in the data field are written to the IC entry corresponding to the way and entry set in the address field The A bit in the address field should be ...

Page 198: ...ss field bits 31 24 have the value H F1 indicating the IC data array and the way is specified by bits 14 13 and the entry by bits 12 5 Address field bits 4 2 are used for the longword data specification in the entry As only longword access is used 0 should be specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation can be ...

Page 199: ...ts 1 0 In the data field the tag is indicated by bits 31 10 the U bit by bit 1 and the V bit by bit 0 As the OC address array tag is 19 bits in length data field bits 31 29 are not used in the case of a write in which association is not performed Data field bits 31 29 are used for the virtual address specification only in the case of a write in which association is performed The following three ki...

Page 200: ...es no operation is performed This operation is used to invalidate a specific OC entry If the OC entry U bit is 1 and 0 is written to the V bit or to the U bit write back is performed If a UTLB miss occurs during address translation or the comparison shows a mismatch an exception is not generated no operation is performed and the write is not executed Note This function may not be supported in the ...

Page 201: ... specified for address field bits 1 0 The data field is used for the longword data specification The following two kinds of operation can be used on the OC data array 1 OC data array read Longword data is read into the data field from the data specified by the longword specification bits in the address field in the OC entry corresponding to the way and entry set in the address field 2 OC data arra...

Page 202: ...4 SQ1 5 SQ1 6 SQ1 7 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte 4 byte Figure 8 9 Store Queue Configuration 8 7 2 Writing to SQ A write to the SQs can be performed using a store instruction for addresses H E000 0000 to H E3FF FFFC in the P4 area A longword or quadword access size can be used The meanings of the address bits are as follows 31 26 111000 Store queue specification 25 6 Don t care...

Page 203: ...its have no meaning with regard to this page When a prefetch instruction is issued for the SQ area address translation is performed and physical address bits 28 10 are generated in accordance with the SZ bit specification For physical address bits 9 5 the address prior to address translation is generated in the same way as when the MMU is disabled Physical address bits 4 0 are fixed at 0 Transfer ...

Page 204: ... memory using a PREF instruction As a result a TLB miss exception or protection violation exception is generated as required However if SQ access is enabled in privileged mode only by the SQMD bit in MMUCR an address error will occur even if address translation is successful in user mode When MMU is disabled AT 0 in MMUCR Operation is in accordance with the SQMD bit in MMUCR 0 Privileged user mode...

Page 205: ...ts 28 10 19 bits in the IC and OC are extended to bits 31 10 22 bits 2 An instruction which operates the IC a memory mapped IC access and writing to the ICI bit in CCR should be located in the P1 or P2 area The cacheable bit C bit in the corresponding entry in the PMB should be 0 3 Bits 4 2 3 bits for the AREA0 bit in QACR0 and the AREA1 bit in QACR1 are extended to bits 7 2 6 bits ...

Page 206: ...Rev 1 50 10 04 page 186 of 448 ...

Page 207: ...bytes 128 Kbytes Page 0 of L memory H E500E000 to H E500FFFF H E500C000 to H E500FFFF H E5008000 to H E500FFFF H E5000000 to H E500FFFF Page 1 of L memory H E5010000 to H E5011FFF H E5010000 to H E5013FFF H E5010000 to H E5017FFF H E5010000 to H E501FFFF Ports Each page has three independent read write ports and is connected to each bus The instruction bus is used when L memory is accessed through...

Page 208: ...F00005C H 1F00005C 32 Note The P4 address is the address used when using P4 area in the virtual address space The area 7 address is the address used when accessing from area 7 in the physical address space using the TLB Table 9 3 Register Status in Each Processing State Name Abbreviation Power On Reset Manual Reset Sleep Standby On chip memory control register RAMCR H 00000000 H 00000000 Retained ...

Page 209: ...cifies the right of access to the L memory from the virtual address space 0 An access in privileged mode is allowed An address error exception occurs in user mode 1 An access in user privileged mode is allowed 8 RP 0 R W On Chip Memory Protection Enable Selects whether or not to use the protective functions using ITLB and UTLB for accessing the L memory from the virtual address space 0 Protective ...

Page 210: ... 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer General Precautions on Handling of Product 28 to 10 L0SADR Undefined R W L Memory Page 0 Block Transfer Source Address When MMUCR AT 0 or RAMCR RP 0 these bits specify the trans...

Page 211: ...ied in 2 Kbyte units 111100 Transfer source physical address is specified in 4 Kbyte units 111000 Transfer source physical address is specified in 8 Kbyte units 110000 Transfer source physical address is specified in 16 Kbyte units 100000 Transfer source physical address is specified in 32 Kbyte units 000000 Transfer source physical address is specified in 64 Kbyte units Settings other than the on...

Page 212: ...s bits 15 to 10 of the transfer source physical address for block transfer to page 1 in the L memory L1SSZ bits 5 0 correspond to the transfer source physical addresses 15 10 0 The operand address is used as the transfer source physical address 1 The L1SADR value is used as the transfer source physical address Settable values 111111 Transfer source physical address is specified in 1 Kbyte units 11...

Page 213: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer to General Precautions on Handling of Product 28 to 10 L0DADR Undefined R W L Memory Page 0 Block Transfer Destination Address When MMUCR AT 0 or RAMCR RP 0 these bits specify tr...

Page 214: ...destination physical address 1 The L0DADR value is used as the transfer destination physical address Settable values 111111 Transfer destination physical address is specified in 1 Kbyte units 111110 Transfer destination physical address is specified in 2 Kbyte units 111100 Transfer destination physical address is specified in 4 Kbyte units 111000 Transfer destination physical address is specified ...

Page 215: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 Bit 0 0 0 0 Initial value R W R W R W R W R W R W R R R R R W R W R W R W R W R W R W Bit Bit Name Initial Value R W Description 31 to 29 All 0 R Reserved For read write in these bits refer to General Precautions on Handling of Product 28 to 10 L1DADR Undefined R W L Memory Page 1 Block Transfer Destination Address When MMUCR AT 0 or RAMCR RP 0 these bits specify tr...

Page 216: ...stination physical address 1 The L1DADR value is used as the transfer destination physical address Settable values 111111 Transfer destination physical address is specified in 1 Kbyte units 111110 Transfer destination physical address is specified in 2 Kbyte units 111100 Transfer destination physical address is specified in 4 Kbyte units 111000 Transfer destination physical address is specified in...

Page 217: ...ernal memory through a write back instruction OCBWB Block transfer from the L memory to the external memory begins when the OCBWB instruction is issued to the address in the L memory area in the virtual address space In either case transfer rate is fixed to 32 bytes Since the start address is always limited to a 32 byte boundary the lower five bits of the address indicated by Rn are ignored and ar...

Page 218: ...bits in the LSA0 register choose either the virtual addresses specified through the PRFF instruction or the L0SADR values as bits 15 to 10 of the transfer source physical address In other words the transfer source area can be specified in units of 1 Kbyte to 64 Kbytes The transfer destination physical address in block transfer from page 0 in the L memory is set in the L0DADR bits of the LDA0 regis...

Page 219: ...d in user mode it is determined to be an address error exception When MMUCR AT 1 and RAMCR RP 1 MMU exception and address error exception are checked in the L memory area which is a part of area P4 as with the area P0 P3 U0 The above descriptions are summarized in table 9 4 Table 9 4 Protective Function Exceptions to Access L Memory MMUCR AT RAMCR RP SR MD RAMCR RMD Always Occurring Exceptions Pos...

Page 220: ...cate instructions in the L memory write an instruction to the L memory execute the following sequence then branch to the rewritten instruction SYNCO ICBI Rn In this case the target for the ICBI instruction can be any address L memory address may be possible within the range where no address error exception occurs and cache hit miss is possible 9 5 3 Sleep Mode The SuperHyway bus master module such...

Page 221: ...ignment 32 byte boundary alignment 16 times repeat expansion 32 times repeat expansion Count specification repeat expansion end Possible Exceptions A list of exceptions that may occur when an instruction is executed is shown bellow But Instruction TLB multiple hit exception Instruction TLB miss exception Instruction TLB protection exception and Instruction address error are omitted because these e...

Page 222: ...unsigned long Addr unsigned short Read_Word unsigned long Addr unsigned long Read_Long unsigned long Addr These reflect the respective sizes of address Addr A word read from other than a 2n address or a longword read from other than a 4n address will be detected as an address error unsigned char Write_Byte unsigned long Addr unsigned long Data unsigned short Write_Word unsigned long Addr unsigned ...

Page 223: ...signed long Q0 1 unsigned long I0 4 unsigned long dummy1 2 unsigned long S0 1 unsigned long T0 1 SR structure definitions define M struct SR0 SR M0 define Q struct SR0 SR Q0 define S struct SR0 SR S0 define T struct SR0 SR T0 Definitions of bits in SR Error char er Error display function ...

Page 224: ...an also be added to the contents of general register Rn 8 bit immediate data is sign extended to 32 bits allowing use in decrement operations Notes None Operation ADD long m long n ADD Rm Rn R n R m PC 2 ADDI long i long n ADD imm Rn if i 0x80 0 R n 0x000000FF long i else R n 0xFFFFFF00 long i PC 2 Example ADD R0 R1 Before execution R0 H 7FFFFFFF R1 H 00000001 After execution R1 H 80000000 ADD H 0...

Page 225: ...carry resulting from the operation is reflected in the T bit This instruction is used for additions exceeding 32 bits Notes None Operation ADDC long m long n ADDC Rm Rn unsigned long tmp0 tmp1 tmp1 R n R m tmp0 R n R n tmp1 T if tmp0 tmp1 T 1 else T 0 if tmp1 R n T 1 PC 2 Example CLRT R0 R1 64 bits R2 R3 64 bits R0 R1 64 bits ADDC R3 R1 Before execution T 0 R1 H 00000001 R3 H FFFFFFFF After execut...

Page 226: ...rflow Description This instruction adds together the contents of general registers Rn and Rm and stores the result in Rn If overflow occurs the T bit is set Notes None Operation ADDV long m long n ADDV Rm Rn long dest src ans if long R n 0 dest 0 else dest 1 if long R m 0 src 0 else src 1 src dest R n R m if long R n 0 ans 0 else ans 1 ans dest if src 0 src 2 if ans 1 T 1 else T 0 else T 0 PC 2 ...

Page 227: ...04 page 207 of 448 Example ADDV R0 R1 Before execution R0 H 00000001 R1 H 7FFFFFFE T 0 After execution R1 H 7FFFFFFF T 0 ADDV R0 R1 Before execution R0 H 00000002 R1 H 7FFFFFFE T 0 After execution R1 H 80000000 T 1 ...

Page 228: ...ral registers Rn and Rm and stores the result in Rn This instruction can be used to AND general register R0 contents with zero extended 8 bit immediate data or in indexed GBR indirect addressing mode to AND 8 bit memory with 8 bit immediate data Notes With AND imm R0 the upper 24 bits of R0 are always cleared as a result of the operation Operation AND long m long n AND Rm Rn R n R m PC 2 ANDI long...

Page 229: ...After execution R0 H 0000000F AND B H 80 R0 GBR Before execution R0 GBR H A5 After execution R0 GBR H 80 Possible Exceptions Exceptions may occur when AND B instruction is executed Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Initial page write exception Data address error Exceptions are checked taking a data access by this instruction as a byte l...

Page 230: ...truction address As the 8 bit displacement is multiplied by two after sign extension the branch destination can be located in the range from 256 to 254 bytes from the BF instruction Notes If the branch destination cannot be reached the branch must be handled by using BF in combination with a BRA or JMP instruction for example Operation BF int d BF disp int disp if d 0x80 0 disp 0x000000FF d else d...

Page 231: ...Rev 1 50 10 04 page 211 of 448 Possible Exceptions Slot illegal instruction exception ...

Page 232: ...wo after sign extension the branch destination can be located in the range from 256 to 254 bytes from the BF S instruction Notes As this is a delayed branch instruction when the branch condition is satisfied the instruction following this instruction is executed before the branch destination instruction Interrupts are not accepted between this instruction and the following instruction If the follo...

Page 233: ...0FF d else disp 0xFFFFFF00 d if T 0 PC PC 4 disp 1 else PC 4 Delay_Slot temp 2 Example CLRT Normally T 0 BT S TRGET_T T 0 so branch is not taken NOP BF S TRGET_F T 0 so branch to TRGET ADD R0 R1 Executed before branch NOP TRGET_F BF S instruction branch destination Possible Exceptions Slot illegal instruction exception ...

Page 234: ... If the branch destination cannot be reached this branch can be performed with a JMP instruction Notes As this is a delayed branch instruction the instruction following this instruction is executed before the branch destination instruction Interrupts are not accepted between this instruction and the following instruction If the following instruction is a branch instruction it is identified as a sl...

Page 235: ...Rev 1 50 10 04 page 215 of 448 Possible Exceptions Slot illegal instruction exception ...

Page 236: ...a delayed branch instruction the instruction following this instruction is executed before the branch destination instruction Interrupts are not accepted between this instruction and the following instruction If the following instruction is a branch instruction it is identified as a slot illegal instruction Operation BRAF int n BRAF Rn unsigned int temp temp PC PC PC 4 R n Delay_Slot temp 2 Exampl...

Page 237: ...truction address As the 8 bit displacement is multiplied by two after sign extension the branch destination can be located in the range from 256 to 254 bytes from the BT instruction Notes If the branch destination cannot be reached the branch must be handled by using BT in combination with a BRA or JMP instruction for example Operation BT int d BT disp int disp if d 0x80 0 disp 0x000000FF d else d...

Page 238: ...Rev 1 50 10 04 page 218 of 448 Possible Exceptions Slot illegal instruction exception ...

Page 239: ...6 to 254 bytes from the BT S instruction Notes As this is a delayed branch instruction when the branch condition is satisfied the instruction following this instruction is executed before the branch destination instruction Interrupts are not accepted between this instruction and the following instruction If the following instruction is a branch instruction it is identified as a slot illegal instru...

Page 240: ...le SETT Normally T 1 BF S TRGET_F T 1 so branch is not taken NOP BT S TRGET_T T 1 so branch to TRGET_T ADD R0 R1 Executed before branch NOP TRGET_T BT S instruction branch destination Possible Exceptions Slot illegal instruction exception ...

Page 241: ...Operation Instruction Code Cycle T Bit CLRMAC 0 MACH MACL 0000000000101000 1 Description This instruction clears the MACH and MACL registers Notes None Operation CLRMAC CLRMAC MACH 0 MACL 0 PC 2 Example CLRMAC Clear MAC register to initialize MAC W R0 R1 Multiply and accumulate operation MAC W R0 R1 ...

Page 242: ...S Bit System Control Instruction Format Operation Instruction Code Cycle T Bit CLRS 0 S 0000000001001000 1 Description This instruction clears the S bit to 0 Notes None Operation CLRS CLRS S 0 PC 2 Example CLRS Before execution S 1 After execution S 0 ...

Page 243: ...r T Bit System Control Instruction Format Operation Instruction Code Cycle T Bit CLRT 0 T 0000000000001000 1 0 Description This instruction clears the T bit Notes None Operation CLRT CLRT T 0 PC 2 Example CLRT Before execution T 1 After execution T 0 ...

Page 244: ...lt of comparison CMP PL Rn If Rn 0 1 T Otherwise 0 T 0100nnnn00010101 1 Result of comparison CMP PZ Rn If Rn 0 1 T Otherwise 0 T 0100nnnn00010001 1 Result of comparison CMP STR Rm Rn If any bytes are equal 1 T Otherwise 0 T 0010nnnnmmmm1100 1 Result of comparison CMP EQ imm R0 If R0 imm 1 T Otherwise 0 T 10001000iiiiiiii 1 Result of comparison Description This instruction compares general register...

Page 245: ...d values T 1 CMP HS Rm Rn If Rn Rm as unsigned values T 1 CMP PL Rn If Rn 0 T 1 CMP PZ Rn If Rn 0 T 1 CMP STR Rm Rn If any bytes are equal T 1 CMP EQ imm R0 If R0 imm T 1 Notes None Operation CMPEQ long m long n CMP_EQ Rm Rn if R n R m T 1 else T 0 PC 2 CMPGE long m long n CMP_GE Rm Rn if long R n long R m T 1 else T 0 PC 2 CMPGT long m long n CMP_GT Rm Rn if long R n long R m T 1 else T 0 PC 2 ...

Page 246: ...ong R m T 1 else T 0 PC 2 CMPHS long m long n CMP_HS Rm Rn if unsigned long R n unsigned long R m T 1 else T 0 PC 2 CMPPL long n CMP_PL Rn if long R n 0 T 1 else T 0 PC 2 CMPPZ long n CMP_PZ Rn if long R n 0 T 1 else T 0 PC 2 CMPSTR long m long n CMP_STR Rm Rn unsigned long temp long HH HL LH LL ...

Page 247: ... T 0 PC 2 CMPIM long i CMP_EQ imm R0 long imm if i 0x80 0 imm 0x000000FF long i else imm 0xFFFFFF00 long i if R 0 imm T 1 else T 0 PC 2 Example CMP GE R0 R1 R0 H 7FFFFFFF R1 H 80000000 BT TRGET_T T 0 so branch is not taken CMP HS R0 R1 R0 H 7FFFFFFF R1 H 80000000 BT TRGET_T T 1 so branch is taken CMP STR R2 R3 R2 ABCD R3 XYCZ BT TRGET_T T 1 so branch is taken ...

Page 248: ...struction performs initial settings for signed division This instruction is followed by a DIV1 instruction that executes 1 digit division for example and repeated divisions are executed to find the quotient See the description of the DIV1 instruction for details Notes None Operation DIV0S long m long n DIV0S Rm Rn if R n 0x80000000 0 Q 0 else Q 1 if R m 0x80000000 0 M 0 else M 1 T M Q PC 2 Example...

Page 249: ...escription This instruction performs initial settings for unsigned division This instruction is followed by a DIV1 instruction that executes 1 digit division for example and repeated divisions are executed to find the quotient See the description of the DIV1 instruction for details Notes None Operation DIV0U DIV0U M Q T 0 PC 2 Example See the examples for the DIV1 instruction ...

Page 250: ...ether the result is positive or negative The remainder can be found as follows after first finding the quotient using the DIV1 instruction Remainder dividend divisor quotient Detection of division by zero or overflow is not provided Check for division by zero and overflow division before executing the division A remainder operation is not provided Find the remainder by finding the product of the d...

Page 251: ...0 Q tmp1 break case 1 Q unsigned char tmp1 0 break break case 1 tmp0 R n R n tmp2 tmp1 R n tmp0 switch Q case 0 Q unsigned char tmp1 0 break case 1 Q tmp1 break break break case 1 switch M case 0 tmp0 R n R n tmp2 tmp1 R n tmp0 switch Q case 0 Q tmp1 break case 1 Q unsigned char tmp1 0 break break case 1 tmp0 R n ...

Page 252: ...reak T Q M PC 2 Example 1 R1 32 bits R0 16 bits R1 16 bits unsigned SHLL16 R0 Set divisor in upper 16 bits clear lower 16 bits to 0 TST R0 R0 Check for division by zero BT ZERO_DIV CMP HS R0 R1 Check for overflow BT OVER_DIV DIV0U Flag initialization arepeat 16 DIV1 R0 R1 Repeat 16 times aendr ROTCL R1 EXTU W R1 R1 R1 quotient ...

Page 253: ...6 bits R0 16 bits R1 16 bits signed SHLL16 R0 Set divisor in upper 16 bits clear lower 16 bits to 0 EXTS W R1 R1 Dividend sign extended to 32 bits XOR R2 R2 R2 0 MOV R1 R3 ROTCL R3 SUBC R2 R1 If dividend is negative subtract 1 DIV0S R0 R1 Flag initialization arepeat 16 DIV1 R0 R1 Repeat 16 times aendr EXTS W R1 R1 ROTCL R1 R1 quotient one s complement notation ADDC R2 R1 If MSB of quotient is 1 ad...

Page 254: ... XOR R3 R3 R3 0 SUBC R3 R2 If dividend is negative subtract 1 to convert to one s complement notation DIV0S R0 R1 Flag initialization arepeat 32 ROTCL R2 Repeat 32 times DIV1 R0 R1 aendr ROTCL R2 R2 quotient one s complement notation ADDC R3 R2 If MSB of quotient is 1 add 1 to convert to two s complement notation R2 quotient two s complement notation ...

Page 255: ...he 64 bit result in the MACH and MACL registers The multiplication is performed as a signed arithmetic operation Notes None Operation DMULS long m long n DMULS L Rm Rn unsigned long RnL RnH RmL RmH Res0 Res1 Res2 unsigned long temp0 temp1 temp2 temp3 long tempm tempn fnLmL tempn long R n tempm long R m if tempn 0 tempn 0 tempn if tempm 0 tempm 0 tempm if long R n R m 0 fnLmL 1 else fnLmL 0 temp1 u...

Page 256: ...6 0xFFFF0000 Res0 temp0 temp1 if Res0 temp0 Res2 Res2 Res2 Res1 16 0x0000FFFF temp3 if fnLmL 0 Res2 Res2 if Res0 0 Res2 else Res0 Res0 1 MACH Res2 MACL Res0 PC 2 Example DMULS L R0 R1 Before execution R0 H FFFFFFFE R1 H 00005555 After execution MACH H FFFFFFFF MACL H FFFF5556 STS MACH R0 Get operation result upper STS MACL R1 Get operation result lower ...

Page 257: ... Rm and stores the 64 bit result in the MACH and MACL registers The multiplication is performed as an unsigned arithmetic operation Notes None Operation DMULU long m long n DMULU L Rm Rn unsigned long RnL RnH RmL RmH Res0 Res1 Res2 unsigned long temp0 temp1 temp2 temp3 RnL R n 0x0000FFFF RnH R n 16 0x0000FFFF RmL R m 0x0000FFFF RmH R m 16 0x0000FFFF temp0 RmL RnL temp1 RmH RnL temp2 RmL RnH temp3 ...

Page 258: ...Res1 16 0x0000FFFF temp3 MACH Res2 MACL Res0 PC 2 Example DMULU L R0 R1 Before execution R0 H FFFFFFFE R1 H 00005555 After execution MACH H 00005554 MACL H FFFF5556 STS MACH R0 Get operation result upper STS MACL R1 Get operation result lower ...

Page 259: ... This instruction decrements the contents of general register Rn by 1 and compares the result with zero If the result is zero the T bit is set to 1 If the result is nonzero the T bit is cleared to 0 Notes None Operation DT long n DT Rn R n if R n 0 T 1 else T 0 PC 2 Example MOV 4 R5 Set loop count LOOP ADD R0 R1 DT R5 Decrement R5 value and check for 0 BF LOOP If T 0 branch to LOOP in this example...

Page 260: ...nstruction sign extends the contents of general register Rm and stores the result in Rn For a byte specification the value of Rm bit 7 is transferred to Rn bits 8 to 31 For a word specification the value of Rm bit 15 is transferred to Rn bits 16 to 31 Notes None Operation EXTSB long m long n EXTS B Rm Rn R n R m if R m 0x00000080 0 R n 0x000000FF else R n 0xFFFFFF00 PC 2 EXTSW long m long n EXTS W...

Page 261: ...Rev 1 50 10 04 page 241 of 448 Example EXTS B R0 R1 Before execution R0 H 00000080 After execution R1 H FFFFFF80 EXTS W R0 R1 Before execution R0 H 00008000 After execution R1 H FFFF8000 ...

Page 262: ...xtends the contents of general register Rm and stores the result in Rn For a byte specification 0 is transferred to Rn bits 8 to 31 For a word specification 0 is transferred to Rn bits 16 to 31 Notes None Operation EXTUB long m long n EXTU B Rm Rn R n R m R n 0x000000FF PC 2 EXTUW long m long n EXTU W Rm Rn R n R m R n 0x0000FFFF PC 2 Example EXTU B R0 R1 Before execution R0 H FFFFFF80 After execu...

Page 263: ... No operation is performed in the case of a cache miss or access to a non cache area Notes None Operation ICBI int n ICBI Rn invalidate_instruction_cache_block R n PC 2 Example When a program is overwriting RAM to modify its own execution the corresponding block of the instruction cache should be invalidated by the ICBI instruction This prevents execution of the program from the instruction cache ...

Page 264: ...re the branch destination instruction Interrupts are not accepted between this instruction and the following instruction If the following instruction is a branch instruction it is identified as a slot illegal instruction Operation JMP int n JMP Rn unsigned int temp temp PC PC R n Delay_Slot temp 2 Example MOV L JMP_TABLE R0 R0 TRGET address JMP R0 Branch to TRGET MOV R0 R1 MOV executed before bran...

Page 265: ... R7_BANK Rm R7_BANK 0100mmmm11111110 1 LDC L Rm GBR Rm GBR Rm 4 Rm 0100mmmm00010111 1 LDC L Rm VBR Rm VBR Rm 4 Rm 0100mmmm00100111 1 LDC L Rm SGR Rm SGR Rm 4 Rm 0100mmmm00110110 4 LDC L Rm SSR Rm SSR Rm 4 Rm 0100mmmm00110111 1 LDC L Rm SPC Rm SPC Rm 4 Rm 0100mmmm01000111 1 LDC L Rm DBR Rm DBR Rm 4 Rm 0100mmmm11110110 4 LDC L Rm R0_BANK Rm R0_BANK Rm 4 Rm 0100mmmm10000111 1 LDC L Rm R1_BANK Rm R1_B...

Page 266: ... Rm GBR and LDC L Rm GBR can also be used in user mode With the LDC Rm Rn_BANK and LDC L Rm Rn_BANK instructions Rn_BANK0 is accessed when the RB bit in the SR register is 1 and Rn_BANK1 is accessed when this bit is 0 Operation LDCGBR int m LDC Rm GBR GBR R m PC 2 LDCVBR int m LDC Rm VBR Privileged VBR R m PC 2 LDCSGR int m LDC Rm SGR Privileged SGR R m PC 2 LDCSSR int m LDC Rm SSR Privileged SSR ...

Page 267: ...DBR R m PC 2 LDCRn_BANK int m LDC Rm Rn_BANK Privileged n 0 7 Rn_BANK R m PC 2 LDCMGBR int m LDC L Rm GBR GBR Read_Long R m R m 4 PC 2 LDCMVBR int m LDC L Rm VBR Privileged VBR Read_Long R m R m 4 PC 2 LDCMSGR int m LDC L Rm SGR Privileged SGR Read_Long R m R m 4 PC 2 ...

Page 268: ... 2 LDCMDBR int m LDC L Rm DBR Privileged DBR Read_Long R m R m 4 PC 2 LDCMRn_BANK Long m LDC L Rm Rn_BANK Privileged n 0 7 Rn_BANK Read_Long R m R m 4 PC 2 Possible Exceptions Data TLB multiple hit exception General illegal instruction exception Slot illegal instruction exception Data TLB miss exception Data TLB protection violation exception Data address error ...

Page 269: ...m00011010 1 LDS Rm PR Rm PR 0100mmmm00101010 1 LDS L Rm MACH Rm MACH Rm 4 Rm 0100mmmm00000110 1 LDS L Rm MACL Rm MACL Rm 4 Rm 0100mmmm00010110 1 LDS L Rm PR Rm PR Rm 4 Rm 0100mmmm00100110 1 Description Stores the source operand into the system registers MACH MACL or PR Notes None Operation LDSMACH long m LDS Rm MACH MACH R m PC 2 LDSMACL long m LDS Rm MACL MACL R m PC 2 LDSPR long m LDS Rm PR PR R...

Page 270: ...R m R m 4 PC 2 Example LDS R0 PR Before execution R0 H 12345678 PR H 00000000 After execution PR H 12345678 LDS L R15 MACL Before execution R15 H 10000000 After execution R15 H 10000004 MACL H 10000000 Possible Exceptions Exception may occur when LDS L instruction is executed Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Data address error ...

Page 271: ... the PTEH PTEL registers into a TLB it should be used either with the MMU disabled or in the P1 or P2 virtual space with the MMU enabled see section 7 Memory Management Unit MMU for details After this instruction is issued there must be at least one instruction between the LDTLB instruction and issuance of an instruction relating to address to the P0 U0 and P3 areas i e BRAF BSRF JMP JSR RTS or RT...

Page 272: ...e MOV R0 R1 Load page table entry upper into R1 MOV R1 R2 Load R1 into PTEH R2 is PTEH address H FF000000 LDTLB Load PTEH PTEL registers into TLB Possible Exceptions General illegal instruction exception Slot illegal instruction exception ...

Page 273: ...they are read If the S bit is 0 the 64 bit result is stored in the linked MACH and MACL registers If the S bit is 1 the addition to the MAC register contents is a saturation operation at the 48th bit from the LSB In a saturation operation only the lower 48 bits of the MAC register are valid and the result range is limited to H FFFF800000000000 minimum value to H 00007FFFFFFFFFFF maximum value Note...

Page 274: ...FFFF temp0 RmL RnL temp1 RmH RnL temp2 RmL RnH temp3 RmH RnH Res2 0 Res1 temp1 temp2 if Res1 temp1 Res2 0x00010000 temp1 Res1 16 0xFFFF0000 Res0 temp0 temp1 if Res0 temp0 Res2 Res2 Res2 Res1 16 0x0000FFFF temp3 if fnLmL 0 Res2 Res2 if Res0 0 Res2 else Res0 Res0 1 if S 1 Res0 MACL Res0 if MACL Res0 Res2 if MACH 0x00008000 else Res2 MACH 0xFFFF0000 Res2 MACH 0x00007FFF ...

Page 275: ...g Res2 0 Res2 0xFFFF8000 Res2 0xFFFF8000 Res0 0x00000000 if long Res2 0 Res2 0x00007FFF Res2 0x00007FFF Res0 0xFFFFFFFF MACH Res2 0x0000FFFF MACH 0xFFFF0000 MACL Res0 else Res0 MACL Res0 if MACL Res0 Res2 Res2 MACH MACH Res2 MACL Res0 PC 2 ...

Page 276: ...CLRMAC MAC register initialization MAC L R0 R1 MAC L R0 R1 STS MACL R0 Get result in R0 align 2 TBLM data l H 1234ABCD data l H 5678EF01 TBLN data l H 0123ABCD data l H 4567DEF0 Possible Exceptions Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Data address error ...

Page 277: ...s If the S bit is 1 a 16 16 32 32 bit multiply and accumulate operation is performed and the addition to the MAC register contents is a saturation operation In a saturation operation only the MACL register is valid and the result range is limited to H 80000000 minimum value to H 7FFFFFFF maximum value If overflow occurs the LSB of the MACH register is set to 1 H 80000000 minimum value is stored in...

Page 278: ...48 if long tempm 0 src 0 tempn 0 else src 1 tempn 0xFFFFFFFF src dest MACL tempm if long MACL 0 ans 0 else ans 1 ans dest if S 1 if ans 1 if src 0 MACL 0x7FFFFFFF if src 2 MACL 0x80000000 else MACH tempn if templ MACL MACH 1 PC 2 ...

Page 279: ...address CLRMAC MAC register initialization MAC W R0 R1 MAC W R0 R1 STS MACL R0 Get result in R0 align 2 TBLM data w H 1234 data w H 5678 TBLN data w H 0123 data w H 4567 Possible Exceptions Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Data address error ...

Page 280: ...110 1 MOV B Rm Rn Rm sign extension Rn Rm 1 Rm 0110nnnnmmmm0100 1 MOV W Rm Rn Rm sign extension Rn Rm 2 Rm 0110nnnnmmmm0101 1 MOV L Rm Rn Rm Rn Rm 4 Rm 0110nnnnmmmm0110 1 MOV B Rm R0 Rn Rm R0 Rn 0000nnnnmmmm0100 1 MOV W Rm R0 Rn Rm R0 Rn 0000nnnnmmmm0101 1 MOV L Rm R0 Rn Rm R0 Rn 0000nnnnmmmm0110 1 MOV B R0 Rm Rn R0 Rm sign extension Rn 0000nnnnmmmm1100 1 MOV W R0 Rm Rn R0 Rm sign extension Rn 000...

Page 281: ...C 2 MOVBS long m long n MOV B Rm Rn Write_Byte R n R m PC 2 MOVWS long m long n MOV W Rm Rn Write_Word R n R m PC 2 MOVLS long m long n MOV L Rm Rn Write_Long R n R m PC 2 MOVBL long m long n MOV B Rm Rn R n long Read_Byte R m if R n 0x80 0 R n 0x000000FF else R n 0xFFFFFF00 PC 2 ...

Page 282: ...0x8000 0 R n 0x0000FFFF else R n 0xFFFF0000 PC 2 MOVLL long m long n MOV L Rm Rn R n Read_Long R m PC 2 MOVBM long m long n MOV B Rm Rn Write_Byte R n 1 R m R n 1 PC 2 MOVWM long m long n MOV W Rm Rn Write_Word R n 2 R m R n 2 PC 2 MOVLM long m long n MOV L Rm Rn Write_Long R n 4 R m R n 4 PC 2 ...

Page 283: ...if n m R m 1 PC 2 MOVWP long m long n MOV W Rm Rn R n long Read_Word R m if R n 0x8000 0 R n 0x0000FFFF else R n 0xFFFF0000 if n m R m 2 PC 2 MOVLP long m long n MOV L Rm Rn R n Read_Long R m if n m R m 4 PC 2 MOVBS0 long m long n MOV B Rm R0 Rn Write_Byte R n R 0 R m PC 2 MOVWS0 long m long n MOV W Rm R0 Rn Write_Word R n R 0 R m PC 2 ...

Page 284: ...OVBL0 long m long n MOV B R0 Rm Rn R n long Read_Byte R m R 0 if R n 0x80 0 R n 0x000000FF else R n 0xFFFFFF00 PC 2 MOVWL0 long m long n MOV W R0 Rm Rn R n long Read_Word R m R 0 if R n 0x8000 0 R n 0x0000FFFF else R n 0xFFFF0000 PC 2 MOVLL0 long m long n MOV L R0 Rm Rn R n Read_Long R m R 0 PC 2 ...

Page 285: ...R1 H FFFF7F7E R1 H AAAA MOV L R0 R1 Before execution R0 H 12345670 After execution R0 H 12345674 R1 H 12345670 MOV B R1 R0 R2 Before execution R2 H 00000004 R0 H 10000000 After execution R1 H 10000004 MOV W R0 R2 R1 Before execution R2 H 00000004 R0 H 10000000 After execution R1 H 10000004 Possible Exceptions Exceptions may occur when MOV instructions without MOV Rm Rn are executed Data TLB multip...

Page 286: ...of word or longword data the data is stored from memory address PC 4 displacement 2 or PC 4 displacement 4 With word data the 8 bit displacement is multiplied by two after zero extension and so the relative distance from the table is in the range up to PC 4 510 bytes The PC value is the address of this instruction With longword data the 8 bit displacement is multiplied by four after zero extension...

Page 287: ...0xFFFFFF00 i PC 2 MOVWI d n MOV W disp PC Rn unsigned int disp disp unsigned int 0x000000FF d R n int Read_Word PC 4 disp 1 if R n 0x8000 0 R n 0x0000FFFF else R n 0xFFFF0000 PC 2 MOVLI int d int n MOV L disp PC Rn unsigned int disp disp unsigned int 0x000000FF int d R n Read_Long PC 0xFFFFFFFC 4 disp 2 PC 2 ...

Page 288: ... w H 1234 1012 NEXT JMP R3 Distination of BRA branch instruction 1014 CMP EQ 0 R0 align 4 1018 data l H 12345678 101C data l H 9ABCDEF0 Note The assembler of Renesas Technology uses the value after scaling 1 2 or 4 as the displacement disp Possible Exceptions Exceptions may occur when PC relative load instruction is executed Data TLB multiple hit exception Slot illegal instruction exception Data T...

Page 289: ...n Byte word or longword can be specified as the data size but the register is always R0 If the transfer data is byte size the 8 bit displacement is only zero extended so a range up to 255 bytes can be specified If the transfer data is word size the 8 bit displacement is multiplied by two after zero extension enabling a range up to 510 bytes to be specified With longword transfer data the 8 bit dis...

Page 290: ...FF d R 0 int Read_Word GBR disp 1 if R 0 0x8000 0 R 0 0x0000FFFF else R 0 0xFFFF0000 PC 2 MOVLLG int d MOV L disp GBR R0 unsigned int disp disp unsigned int 0x000000FF d R 0 Read_Long GBR disp 2 PC 2 MOVBSG int d MOV B R0 disp GBR unsigned int disp disp unsigned int 0x000000FF d Write_Byte GBR disp R 0 PC 2 ...

Page 291: ...L 2 GBR R0 Before execution GBR 8 H 12345670 After execution R0 H 12345670 MOV B R0 1 GBR Before execution R0 H FFFF7F80 After execution GBR 1 H 80 Note The assembler of Renesas Technology uses the value after scaling 1 2 or 4 as the displacement disp Possible Exceptions Data TLB multiple hit exception Slot illegal instruction exception Data TLB miss exception Data TLB protection violation excepti...

Page 292: ... byte or word data the register is always R0 If the data is byte size the 4 bit displacement is only zero extended so a range up to 15 bytes can be specified If the data is word size the 4 bit displacement is multiplied by two after zero extension enabling a range up to 30 bytes to be specified With longword data the 4 bit displacement is multiplied by four after zero extension enabling a range up...

Page 293: ...ong d long n MOV W R0 disp Rn long disp disp 0x0000000F long d Write_Word R n disp 1 R 0 PC 2 MOVLS4 long m long d long n MOV L Rm disp Rn long disp disp 0x0000000F long d Write_Long R n disp 2 R m PC 2 MOVBL4 long m long d MOV B disp Rm R0 long disp disp 0x0000000F long d R 0 Read_Byte R m disp if R 0 0x80 0 R 0 0x000000FF else R 0 0xFFFFFF00 PC 2 ...

Page 294: ...2 Example MOV L 2 R0 R1 Before execution R0 8 H 12345670 After execution R1 H 12345670 MOV L R0 H F R1 Before execution R0 H FFFF7F80 After execution R1 60 H FFFF7F80 Note The assembler of Renesas Technology uses the value after scaling 1 2 or 4 as the displacement disp Possible Exceptions Data TLB multiple hit exception Slot illegal instruction exception Data TLB miss exception Data TLB protectio...

Page 295: ...e is the address of this instruction but a value with the lower 2 bits adjusted to B 00 is used in address calculation Notes If this instruction is executed in a delay slot a slot illegal instruction exception will be generated Operation MOVA int d MOVA disp PC R0 unsigned int disp disp unsigned int 0x000000FF d R 0 PC 0xFFFFFFFC 4 disp 2 PC 2 Example Address org H 1006 1006 MOVA STR R0 STR addres...

Page 296: ...nstructions as follows If write back is selected for the accessed memory and a cache miss occurs the cache block will be allocated but an R0 data write will be performed to that cache block without performing a block read Other cache block contents are undefined Notes None Operation MOVCAL int n MOVCA L R0 Rn if is_write_back_memory R n look_up_in_operand_cache R n MISS allocate_operand_cache_bloc...

Page 297: ...on copies the value of the LDST flag to the T bit When the T bit is set to 1 the value of R0 is stored at the address in Rm If the T bit is cleared to 0 the value is not stored at the address in Rm Finally the LDST flag is cleared to 0 Since the LDST flag is cleared by an instruction or exception storage by the MOVCO instruction only proceeds when no interrupt or exception has occurred between the...

Page 298: ... R0 MOVCO L R0 Rn BF Retry Reexecute if an interrupt or other exception occurs between the MOVLI and MOVCO instructions NOP Possible Exceptions Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Initial page write exception Data address error ...

Page 299: ...y Rm into R0 If however an interrupt or exception occurs LDST is cleared to 0 Storage by the MOVCO instruction only proceeds when the instruction is executed after the LDST bit has been set by the MOVLI instruction and not cleared by an interrupt or other exception When LDST has been cleared to 0 the MOVCO instruction clears the T bit and does not proceed with storage Notes None Operation MOVLINK ...

Page 300: ...on Instruction Code Cycle T Bit MOVT Rn T Rn 0000nnnn00101001 1 Description This instruction stores the T bit in general register Rn When T 1 Rn 1 when T 0 Rn 0 Notes None Operation MOVT long n MOVT Rn R n 0x00000001 SR PC 2 Example XOR R2 R2 R2 0 CMP PZ R2 T 1 MOVT R0 R0 1 CLRT T 0 MOVT R1 R1 0 ...

Page 301: ...s the longword of data from the effective address indicated by the contents of Rm in memory to R0 The address is not restricted to longword boundaries address 4n this instruction allows loading from non longword boundary addresses 4n 1 4n 2 and 4n 3 Data address error exceptions do not occur when access is to non longword boundary addresses 4n 1 4n 2 and 4n 3 Notes None Operation MOVUAL int m MOVU...

Page 302: ...1 H 0000100B R0 H 00001007 Special case in which the source operand is R0 MOVUA L R0 R0 Before execution R0 H 00001001 After execution R0 H 00001001 MOVUA L R0 R0 Before execution R0 H 00001001 After execution R0 H 00001001 Possible Exceptions Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Data address error when the privileged area is accessed from...

Page 303: ...nstruction performs 32 bit multiplication of the contents of general registers Rn and Rm and stores the lower 32 bits of the result in the MACL register The contents of MACH are not changed Notes None Operation MULL long m long n MUL L Rm Rn MACL R n R m PC 2 Example MUL L R0 R1 Before execution R0 H FFFFFFFE R1 H 00005555 After execution MACL H FFFF5556 STS MACL R0 Get operation result ...

Page 304: ...multiplication of the contents of general registers Rn and Rm and stores the 32 bit result in the MACL register The multiplication is performed as a signed arithmetic operation The contents of MACH are not changed Notes None Operation MULS long m long n MULS Rm Rn MACL long short R n long short R m PC 2 Example MULS W R0 R1 Before execution R0 H FFFFFFFE R1 H 00005555 After execution MACL H FFFF55...

Page 305: ... the contents of general registers Rn and Rm and stores the 32 bit result in the MACL register The multiplication is performed as an unsigned arithmetic operation The contents of MACH are not changed Notes None Operation MULU long m long n MULU Rm Rn MACL unsigned long unsigned short R n unsigned long unsigned short R m PC 2 Example MULU W R0 R1 Before execution R0 H 00000002 R1 H FFFFAAAA After e...

Page 306: ...10nnnnmmmm1011 1 Description This instruction finds the two s complement of the contents of general register Rm and stores the result in Rn That is it subtracts Rm from 0 and stores the result in Rn Notes None Operation NEG long m long n NEG Rm Rn R n 0 R m PC 2 Example NEG R0 R1 Before execution R0 H 00000001 After execution R1 H FFFFFFFF ...

Page 307: ...he result in Rn A borrow resulting from the operation is reflected in the T bit The NEGC instruction is used for sign inversion of a value exceeding 32 bits Notes None Operation NEGC long m long n NEGC Rm Rn unsigned long temp temp 0 R m R n temp T if 0 temp T 1 else T 0 if temp R n T 1 PC 2 Example CLRT Sign inversion of R0 R1 64 bits NEGC R1 R1 Before execution R1 H 00000001 T 0 After execution ...

Page 308: ...ion Instruction Code Cycle T Bit NOP No operation 0000000000001001 1 Description This instruction simply increments the program counter PC advancing the processing flow to execution of the next instruction Notes None Operation NOP NOP PC 2 Example NOP Time equivalent to one execution state elapses ...

Page 309: ... Rn 0110nnnnmmmm0111 1 Description This instruction finds the one s complement of the contents of general register Rm and stores the result in Rn That is it inverts the Rm bits and stores the result in Rn Notes None Operation NOT long m long n NOT Rm Rn R n R m PC 2 Example NOT R0 R1 Before execution R0 H AAAAAAAA After execution R1 H 55555555 ...

Page 310: ...e block is invalidated the V bit is cleared to 0 If there is unwritten information U bit 1 write back is not performed even if write back mode is selected No operation is performed in the case of a cache miss or an access to a non cache area Notes None Operation OCBI int n OCBI Rn invalidate_operand_cache_block R n PC 2 Possible Exceptions Data TLB multiple hit exception Data TLB miss exception Da...

Page 311: ... cache block is written back to external memory and that block is invalidated the V bit is cleared to 0 If there is no unwritten information U bit 0 the block is simply invalidated No operation is performed in the case of a cache miss or an access to a non cache area Notes None Operation OCBP int n OCBP Rn if is_dirty_block R n write_back R n invalidate_operand_cache_block R n PC 2 Possible Except...

Page 312: ... U bit 1 the corresponding cache block is written back to external memory and that block is cleaned the U bit is cleared to 0 In other cases i e in the case of a cache miss or an access to a non cache area or if the block is already clean no operation is performed Notes None Operation OCBWB int n OCBWB Rn if is_dirty_block R n write_back R n PC 2 Possible Exceptions Data TLB multiple hit exception...

Page 313: ...1001011iiiiiiii 1 OR B imm R0 GBR R0 GBR imm R0 GBR 11001111iiiiiiii 3 Description This instruction ORs the contents of general registers Rn and Rm and stores the result in Rn This instruction can be used to OR general register R0 contents with zero extended 8 bit immediate data or in indexed GBR indirect addressing mode to OR 8 bit memory with 8 bit immediate data Notes None ...

Page 314: ...R B imm R0 GBR long temp temp long Read_Byte GBR R 0 temp 0x000000FF long i Write_Byte GBR R 0 temp PC 2 Example OR R0 R1 Before execution R0 H AAAA5555 R1 H 55550000 After execution R1 H FFFF5555 OR H F0 R0 Before execution R0 H 00000008 After execution R0 H 000000F8 OR B H 50 R0 GBR Before execution R0 GBR H A5 After execution R0 GBR H F5 ...

Page 315: ...when OR B instruction is executed Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Initial page write exception Data address error Exceptions are checked taking a data access by this instruction as a byte load and a byte store ...

Page 316: ...ero This instruction does not generate data address error and MMU exceptions except data TLB multiple hit exception In the event of an error the PREF instruction is treated as an NOP no operation instruction Notes None Operation PREF int n PREF Rn PC 2 Example MOV L SOFT_PF R1 R1 address is SOFT_PF PREF R1 Load SOFT_PF data into on chip cache align 32 SOFT_PF data l H 12345678 data l H 9ABCDEF0 da...

Page 317: ...or and MMU exceptions In the event of an error the PREFI instruction is treated as an NOP no operation instruction When the address to be prefetched is missing from UTLB or is protected the PREFI instruction is treated as an NOP instruction and a TLB exception does not occur Notes None Operation PREFI int n PREFI Rn prefetch_instruction_cache_block R n PC 2 Example MOVA WakeUp R0 Wakeup address PR...

Page 318: ... of general register Rn one bit to the left through the T bit and stores the result in Rn The bit rotated out of the operand is transferred to the T bit MSB LSB ROTCL T Notes None Operation ROTCL long n ROTCL Rn long temp if R n 0x80000000 0 temp 0 else temp 1 R n 1 if T 1 R n 0x00000001 else R n 0xFFFFFFFE if temp 1 T 1 else T 0 PC 2 Example ROTCL R0 Before execution R0 H 80000000 T 0 After execu...

Page 319: ... of general register Rn one bit to the right through the T bit and stores the result in Rn The bit rotated out of the operand is transferred to the T bit T MSB LSB ROTCR Notes None Operation ROTCR long n ROTCR Rn long temp if R n 0x00000001 0 temp 0 else temp 1 R n 1 if T 1 R n 0x80000000 else R n 0x7FFFFFFF if temp 1 T 1 else T 0 PC 2 Example ROTCR R0 Before execution R0 H 00000001 T 1 After exec...

Page 320: ...tion rotates the contents of general register Rn one bit to the left and stores the result in Rn The bit rotated out of the operand is transferred to the T bit MSB LSB ROTL T Notes None Operation ROTL long n ROTL Rn if R n 0x80000000 0 T 0 else T 1 R n 1 if T 1 R n 0x00000001 else R n 0xFFFFFFFE PC 2 Example ROTL R0 Before execution R0 H 80000000 T 0 After execution R0 H 00000001 T 1 ...

Page 321: ...tion rotates the contents of general register Rn one bit to the right and stores the result in Rn The bit rotated out of the operand is transferred to the T bit MSB LSB ROTR T Notes None Operation ROTR long n ROTR Rn if R n 0x00000001 0 T 0 else T 1 R n 1 if T 1 R n 0x80000000 else R n 0x7FFFFFFF PC 2 Example ROTR R0 Before execution R0 H 00000001 T 0 After execution R0 H 80000000 T 1 ...

Page 322: ...executed before the branch destination instruction Interrupts are not accepted between this instruction and the following instruction An exception must not be generated by the instruction in this instruction s delay slot If the following instruction is a branch instruction it is identified as a slot illegal instruction If this instruction is located in the delay slot immediately following a delaye...

Page 323: ...ng etc is in fact performed in delayed branch instruction delay slot instruction order For example even if the register holding the branch destination address is modified in the delay slot the branch destination address will still be the register contents prior to the modification Possible Exceptions General illegal instruction exception Slot illegal instruction exception ...

Page 324: ...re called by a BSR or JSR instruction to the source of the call Notes As this is a delayed branch instruction the instruction following this instruction is executed before the branch destination instruction Interrupts are not accepted between this instruction and the following instruction If the following instruction is a branch instruction it is identified as a slot illegal instruction The instru...

Page 325: ...anch to TRGET NOP NOP executed before branch ADD R0 R1 Subroutine procedure return destination PR contents TABLE data l TRGET Jump table TRGET MOV R1 R0 Entry to procedure RTS PR contents PC MOV 12 R0 MOV executed before branch Possible Exceptions Slot illegal instruction exception ...

Page 326: ...S Bit System Control Instruction Format Operation Instruction Code Cycle T Bit SETS 1 S 0000000001011000 1 Description This instruction sets the S bit to 1 Notes None Operation SETS SETS S 1 PC 2 Example SETS Before execution S 0 After execution S 1 ...

Page 327: ... Bit System Control Instruction Format Operation Instruction Code Cycle T Bit SETT 1 T 0000000000011000 1 1 Description This instruction sets the T bit to 1 Notes None Operation SETT SETT T 1 PC 2 Example SETT Before execution T 0 After execution T 1 ...

Page 328: ...ifies the shift direction and the number of bits to be shifted Rn register contents are shifted to the left if the Rm register value is positive and to the right if negative In a shift to the right the MSB is added at the upper end The number of bits to be shifted is specified by the lower 5 bits bits 4 to 0 of the Rm register If the value is negative MSB 1 the Rm register is represented as a two ...

Page 329: ...1F else if R m 0x1F 0 if R n 0x80000000 0 R n 0 else R n 0xFFFFFFFF else R n long R n R m 0x1F 1 PC 2 Example SHAD R1 R2 Before execution R1 H FFFFFFEC R2 H 80180000 After execution R1 H FFFFFFEC R2 H FFFFF801 SHAD R3 R4 Before execution R3 H 00000014 R4 H FFFFF801 After execution R3 H 00000014 R4 H 80100000 ...

Page 330: ...is instruction arithmetically shifts the contents of general register Rn one bit to the left and stores the result in Rn The bit shifted out of the operand is transferred to the T bit MSB LSB SHAL T 0 Notes None Operation SHAL long n SHAL Rn Same as SHLL if R n 0x80000000 0 T 0 else T 1 R n 1 PC 2 Example SHAL R0 Before execution R0 H 80000001 T 0 After execution R0 H 00000002 T 1 ...

Page 331: ...he contents of general register Rn one bit to the right and stores the result in Rn The bit shifted out of the operand is transferred to the T bit MSB LSB SHAR T Notes None Operation SHAR long n SHAR Rn long temp if R n 0x00000001 0 T 0 else T 1 if R n 0x80000000 0 temp 0 else temp 1 R n 1 if temp 1 R n 0x80000000 else R n 0x7FFFFFFF PC 2 Example SHAR R0 Before execution R0 H 80000001 T 0 After ex...

Page 332: ...ies the shift direction and the number of bits to be shifted Rn register contents are shifted to the left if the Rm register value is positive and to the right if negative In a shift to the right 0s are added at the upper end The number of bits to be shifted is specified by the lower 5 bits bits 4 to 0 of the Rm register If the value is negative MSB 1 the Rm register is represented as a two s comp...

Page 333: ...f sgn 0 R n R m 0x1F else if R m 0x1F 0 R n 0 else R n unsigned R n R m 0x1F 1 PC 2 Example SHLD R1 R2 Before execution R1 H FFFFFFEC R2 H 80180000 After execution R1 H FFFFFFEC R2 H 00000801 SHLD R3 R4 Before execution R3 H 00000014 R4 H FFFFF801 After execution R3 H 00000014 R4 H 80100000 ...

Page 334: ...his instruction logically shifts the contents of general register Rn one bit to the left and stores the result in Rn The bit shifted out of the operand is transferred to the T bit MSB LSB 0 SHLL T Notes None Operation SHLL long n SHLL Rn Same as SHAL if R n 0x80000000 0 T 0 else T 1 R n 1 PC 2 Example SHLL R0 Before execution R0 H 80000001 T 0 After execution R0 H 00000002 T 1 ...

Page 335: ...n 2 Rn 0100nnnn00001000 1 SHLL8 Rn Rn 8 Rn 0100nnnn00011000 1 SHLL16 Rn Rn 16 Rn 0100nnnn00101000 1 Description This instruction logically shifts the contents of general register Rn 2 8 or 16 bits to the left and stores the result in Rn The bits shifted out of the operand are discarded MSB LSB 0 SHLL8 SHLL16 MSB LSB 0 MSB LSB 0 SHLL2 Notes None ...

Page 336: ...long n SHLL8 Rn R n 8 PC 2 SHLL16 long n SHLL16 Rn R n 16 PC 2 Example SHLL2 R0 Before execution R0 H 12345678 After execution R0 H 48D159E0 SHLL8 R0 Before execution R0 H 12345678 After execution R0 H 34567800 SHLL16 R0 Before execution R0 H 12345678 After execution R0 H 56780000 ...

Page 337: ...is instruction logically shifts the contents of general register Rn one bit to the right and stores the result in Rn The bit shifted out of the operand is transferred to the T bit MSB LSB SHLR T 0 Notes None Operation SHLR long n SHLR Rn if R n 0x00000001 0 T 0 else T 1 R n 1 R n 0x7FFFFFFF PC 2 Example SHLR R0 Before execution R0 H 80000001 T 0 After execution R0 H 40000000 T 1 ...

Page 338: ...n 2 Rn 0100nnnn00001001 1 SHLR8 Rn Rn 8 Rn 0100nnnn00011001 1 SHLR16 Rn Rn 16 Rn 0100nnnn00101001 1 Description This instruction logically shifts the contents of general register Rn 2 8 or 16 bits to the right and stores the result in Rn The bits shifted out of the operand are discarded MSB LSB 0 SHLR8 SHLR16 MSB LSB 0 MSB LSB 0 SHLR2 Notes None ...

Page 339: ...SHLR8 Rn R n 8 R n 0x00FFFFFF PC 2 SHLR16 long n SHLR16 Rn R n 16 R n 0x0000FFFF PC 2 Example SHLR2 R0 Before execution R0 H 12345678 After execution R0 H 048D159E SHLR8 R0 Before execution R0 H 12345678 After execution R0 H 00123456 SHLR16 R0 Before execution R0 H 12345678 After execution R0 H 00001234 ...

Page 340: ...its for an interrupt request When it receives an interrupt request the CPU exits the power down state SLEEP is a privileged instruction and can only be used in privileged mode Use of this instruction in user mode will cause an illegal instruction exception Notes SLEEP performance depends on the standby control register STBCR See Power Down Modes in the target product s hardware manual for details ...

Page 341: ...Rn GBR Rn 0100nnnn00010011 1 STC L VBR Rn Rn 4 Rn VBR Rn 0100nnnn00100011 1 STC L SSR Rn Rn 4 Rn SSR Rn 0100nnnn00110011 1 STC L SPC Rn Rn 4 Rn SPC Rn 0100nnnn01000011 1 STC L SGR Rn Rn 4 Rn SGR Rn 0100nnnn00110010 1 STC L DBR Rn Rn 4 Rn DBR Rn 0100nnnn11110010 1 STC L R0_BANK Rn Rn 4 Rn R0_BANK Rn 0100nnnn10000011 1 STC L R1_BANK Rn Rn 4 Rn R1_BANK Rn 0100nnnn10010011 1 STC L R2_BANK Rn Rn 4 Rn R...

Page 342: ...s in user mode will cause illegal instruction exceptions Operation STCGBR int n STC GBR Rn R n GBR PC 2 STCVBR int n STC VBR Rn Privileged R n VBR PC 2 STCSSR int n STC SSR Rn Privileged R n SSR PC 2 STCSPC int n STC SPC Rn Privileged R n SPC PC 2 STCSGR int n STC SGR Rn Privileged R n SGR PC 2 STCDBR int n STC DBR Rn Privileged R n DBR PC 2 ...

Page 343: ...7 R n Rm_BANK PC 2 STCMGBR int n STC L GBR Rn R n 4 Write_Long R n GBR PC 2 STCMVBR int n STC L VBR Rn Privileged R n 4 Write_Long R n VBR PC 2 STCMSSR int n STC L SSR Rn Privileged R n 4 Write_Long R n SSR PC 2 STCMSPC int n STC L SPC Rn Privileged R n 4 Write_Long R n SPC PC 2 ...

Page 344: ...rite_Long R n DBR PC 2 STCMRm_BANK int n STC L Rm_BANK Rn Privileged m 0 7 R n 4 Write_Long R n Rm_BANK PC 2 Possible Exceptions Data TLB multiple hit exception General illegal instruction exception Slot illegal instruction exception Data TLB miss exception Data TLB protection violation exception Initial page write exception Data address error ...

Page 345: ...011010 1 STS PR Rn PR Rn 0000nnnn00101010 1 STS L MACH Rn Rn 4 Rn MACH Rn 0100nnnn00000010 1 STS L MACL Rn Rn 4 Rn MACL Rn 0100nnnn00010010 1 STS L PR Rn Rn 4 Rn PR Rn 0100nnnn00100010 1 Description This instruction stores system register MACH MACL or PR in the destination Notes None Operation STSMACH int n STS MACH Rn R n MACH PC 2 STSMACL int n STS MACL Rn R n MACL PC 2 STSPR int n STS PR Rn R n...

Page 346: ...Rn R n 4 Write_Long R n PR PC 2 Example STS MACH R0 Before execution R0 H FFFFFFFF MACH H 00000000 After execution R0 H 00000000 STS L PR R15 Before execution R15 H 10000004 After execution R15 H 10000000 R15 PR Possible Exceptions Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Initial page write exception Data address error ...

Page 347: ...000 1 Description This instruction subtracts the contents of general register Rm from the contents of general register Rn and stores the result in Rn For immediate data subtraction ADD imm Rn should be used Notes None Operation SUB long m long n SUB Rm Rn R n R m PC 2 Example SUB R0 R1 Before execution R0 H 00000001 R1 H 80000000 After execution R1 H 7FFFFFFF ...

Page 348: ... result in Rn A borrow resulting from the operation is reflected in the T bit This instruction is used for subtractions exceeding 32 bits Notes None Operation SUBC long m long n SUBC Rm Rn unsigned long tmp0 tmp1 tmp1 R n R m tmp0 R n R n tmp1 T if tmp0 tmp1 T 1 else T 0 if tmp1 R n T 1 PC 2 Example CLRT R0 R1 64 bits R2 R3 64 bits R0 R1 64 bits SUBC R3 R1 Before execution T 0 R1 H 00000000 R3 H 0...

Page 349: ...escription This instruction subtracts the contents of general register Rm from the contents of general register Rn and stores the result in Rn If underflow occurs the T bit is set Notes None Operation SUBV long m long n SUBV Rm Rn long dest src ans if long R n 0 dest 0 else dest 1 if long R m 0 src 0 else src 1 src dest R n R m if long R n 0 ans 0 else ans 1 ans dest if src 1 if ans 1 T 1 else T 0...

Page 350: ... 10 04 page 330 of 448 Example SUBV R0 R1 Before execution R0 H 00000002 R1 H 80000001 After execution R1 H 7FFFFFFF T 1 SUBV R2 R3 Before execution R2 H FFFFFFFE R3 H 7FFFFFFE After execution R3 H 80000000 T 1 ...

Page 351: ...nd stores the result in Rn In the case of a byte specification the 8 bits from bit 15 to bit 8 of Rm are swapped with the 8 bits from bit 7 to bit 0 The upper 16 bits of Rm are transferred directly to the upper 16 bits of Rn In the case of a word specification the 16 bits from bit 31 to bit 16 of Rm are swapped with the 16 bits from bit 15 to bit 0 Notes None Operation SWAPB long m long n SWAP B R...

Page 352: ...age 332 of 448 temp R m 16 0x0000FFFF R n R m 16 R n temp PC 2 Example SWAP B R0 R1 Before execution R0 H 12345678 After execution R1 H 12347856 SWAP W R0 R1 Before execution R0 H 12345678 After execution R1 H 56781234 ...

Page 353: ... not executed until the execution of all preceding bus accesses has been completed Notes The SYNCO instruction can not guarantee the ordering of receipt timing which is notified by the memory mapped peripheral resources through the method except bus when the register is changed by bus accesses Refer to the description of each registers to guarantee this ordering Operation SYNCO SYNCO synchronize_d...

Page 354: ...e operation data is accessed using the contents of general register Rn as the effective address If there is a cache hit and the corresponding cache block is dirty U bit 1 the contents of that cache block are written back to external memory and the cache block is then invalidated by clearing the V bit to 0 If there is a cache hit and the corresponding cache block is clean U bit 0 the cache block is...

Page 355: ...ptions Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Initial page write exception Data address error Exceptions are checked taking a data access by this instruction as a byte load and a byte store ...

Page 356: ...witched to privileged mode the MD bit in SR is set to 1 and the BL bit and RB bit in SR are set to 1 As a result exception and interrupt requests are masked not accepted and the BANK1 registers R0_BANK1 to R7_BANK1 are selected Exception code H 160 is written to the EXPEVT register bits 11 to 0 The program branches to address VBR H 00000100 indicated by the sum of the VBR register contents and off...

Page 357: ...tion ANDs the contents of general registers Rn and Rm and sets the T bit if the result is zero If the result is nonzero the T bit is cleared The contents of Rn are not changed This instruction can be used to AND general register R0 contents with zero extended 8 bit immediate data or in indexed GBR indirect addressing mode to AND 8 bit memory with 8 bit immediate data The contents of R0 or the memo...

Page 358: ...efore execution R0 H FFFFFF7F After execution T 1 TST B H A5 R0 GBR Before execution R0 GBR H A5 After execution T 0 Possible Exceptions Exceptions may occur when TST B instruction is executed Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Initial page write exception Data address error Exceptions are checked taking a data access by this instruction...

Page 359: ...the contents of general registers Rn and Rm and stores the result in Rn This instruction can be used to exclusively OR register R0 contents with zero extended 8 bit immediate data or in indexed GBR indirect addressing mode to exclusively OR 8 bit memory with 8 bit immediate data Notes None Operation XOR long m long n XOR Rm Rn R n R m PC 2 XORI long i XOR imm R0 R 0 0x000000FF long i PC 2 XORM lon...

Page 360: ...F0F XOR B H A5 R0 GBR Before execution R0 GBR H A5 After execution R0 GBR H 00 Possible Exceptions Exceptions may occur when XOR B instruction is executed Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Initial page write exception Data address error Exceptions are checked taking a data access by this instruction as a byte load and a byte store ...

Page 361: ...tion This instruction extracts the middle 32 bits from the 64 bit contents of linked general registers Rm and Rn and stores the result in Rn MSB Rn Rm Rn LSB MSB LSB Notes None Operation XTRCT long m long n XTRCT Rm Rn unsigned long temp temp R m 16 0xFFFF0000 R n R n 16 0x0000FFFF R n temp PC 2 Example XTRCT R0 R1 Before execution R0 H 01234567 R1 H 89ABCDEF After execution R1 H 456789AB ...

Page 362: ... As the 12 bit displacement is multiplied by two after sign extension the branch destination can be located in the range from 4096 to 4094 bytes from the BSR instruction If the branch destination cannot be reached this branch can be performed with a JSR instruction Notes As this is a delayed branch instruction the instruction following this instruction is executed before the branch destination ins...

Page 363: ...T MOV R3 R4 MOV executed before branch ADD R0 R1 Subroutine procedure return destination contents of PR TRGET Entry to procedure MOV R2 R3 RTS Return to above ADD instruction MOV 1 R0 MOV executed before branch Possible Exceptions Slot illegal instruction exception ...

Page 364: ...on address The branch destination address is the result of adding the 32 bit contents of general register Rn to PC 4 Notes As this is a delayed branch instruction the instruction following this instruction is executed before the branch destination instruction Interrupts are not accepted between this instruction and the following instruction If the following instruction is a branch instruction it i...

Page 365: ...R0 Set displacement BSRF R0 Branch to TRGET MOV R3 R4 MOV executed before branch BSRF_PC ADD R0 R1 TRGET Entry to procedure MOV R2 R3 RTS Return to above ADD instruction MOV 1 R0 MOV executed before branch Possible Exceptions Slot illegal instruction exception ...

Page 366: ... is saved in PR and a branch is made to the address indicated by general register Rn JSR is used in combination with RTS for subroutine procedure calls Notes As this is a delayed branch instruction the instruction following this instruction is executed before the branch destination instruction Interrupts are not accepted between this instruction and the following instruction If the following instr...

Page 367: ...ET XOR R1 R1 XOR executed before branch ADD R0 R1 Procedure return destination PR contents align 4 JSR_TABLE data l TRGET Jump table TRGET NOP Entry to procedure MOV R2 R3 RTS Return to above ADD instruction MOV 70 R1 MOV executed before RTS Possible Exceptions Slot illegal instruction exception ...

Page 368: ...the control register SR Notes This instruction is only usable in privileged mode Issuing this instruction in user mode will cause an illegal instruction exception Operation LDCSR int m LDC Rm SR Privileged SR R m 0x700083F3 PC 2 LDCMSR int m LDC L Rm SR Privileged SR Read_Long R m 0x700083F3 R m 4 PC 2 Possible exception Data TLB multiple hit exception General illegal instruction exception Slot il...

Page 369: ...mm01010110 1 LDS Rm FPSCR Rm FPSCR 0100mmmm01101010 1 LDS L Rm FPSCR Rm FPSCR Rm 4 Rm 0100mmmm01100110 1 Description This instruction loads the source operand into FPU system registers FPUL and FPSCR Notes None Operation define FPSCR_MASK 0x003FFFFF LDSFPUL int m int FPUL LDS Rm FPUL FPUL R m PC 2 LDSMFPUL int m int FPUL LDS L Rm FPUL FPUL Read_Long R m R m 4 PC 2 LDSFPSCR int m LDS Rm FPSCR FPSCR...

Page 370: ...e 350 of 448 LDSMFPSCR int m LDS L Rm FPSCR FPSCR Read_Long R m FPSCR_MASK R m 4 PC 2 Possible Exceptions Data TLB multiple hit exception Data TLB miss exception Data TLB protection violation exception Data address error ...

Page 371: ...R in the destination Notes STC can only be used in privileged mode Use of this instruction in user mode will cause illegal instruction exception Operation STCSR int n STC SR Rn Privileged R n SR PC 2 STCMSR int n STC L SR Rn Privileged R n 4 Write_Long R n SR PC 2 Possible exceptions Data TLB multiple hit exception General illegal instruction exception Slot illegal instruction exception Data TLB m...

Page 372: ...Rn 4 Rn FPUL Rn 0100nnnn01010010 1 STS L FPSCR Rn Rn 4 Rn FPSCR Rn 0100nnnn01100010 1 Description This instruction stores FPU system register FPUL or FPSCR in the destination Notes None Operation STSFPUL int n int FPUL STS FPUL Rn R n FPUL PC 2 STSMFPUL int n int FPUL STS L FPUL Rn R n 4 Write_Long R n FPUL PC 2 STSFPSCR int n STS FPSCR Rn R n FPSCR 0x003FFFFF PC 2 STSMFPSCR int n STS L FPSCR Rn R...

Page 373: ...700148 R7 STS L FPUL R7 Before executing the STS L instruction R7 0C700148 After executing the STS L instruction R7 0C700144 and the content of FPUL is saved at memory location 0C700144 Example 2 MOV L H 0C700154 R8 STS L FPSCR R8 After executing the STS L instruction The content of FPSCR is saved at memory location 0C700150 Possible Exceptions Data TLB multiple hit exception Data TLB miss excepti...

Page 374: ...N 6 define sNaN 7 define EQ 0 define GT 1 define LT 2 define UO 3 define INVALID 4 define FADD 0 define FSUB 1 define CAUSE 0x0003f000 FPSCR bit17 12 define SET_E 0x00020000 FPSCR bit17 define SET_V 0x00010040 FPSCR bit16 6 define SET_Z 0x00008020 FPSCR bit15 5 define SET_O 0x00004010 FPSCR bit14 4 define SET_U 0x00002008 FPSCR bit13 3 define SET_I 0x00001004 FPSCR bit12 2 define ENABLE_VOUI 0x000...

Page 375: ...X frf l FPSCR_FR define DR frf d FPSCR_FR define XF_HEX frf l FPSCR_FR define XF frf f FPSCR_FR define XD frf d FPSCR_FR union int l 2 16 float f 2 16 double d 2 8 frf int FPSCR int sign_of int n return FR_HEX n 31 int data_type_of int n int abs abs FR_HEX n 0x7fffffff if FPSCR_PR 0 Single precision if abs 0x00800000 if FPSCR_DN 1 abs 0x00000000 if sign_of n 0 zero n 0 return PZERO else zero n 1 r...

Page 376: ...x00100000 if FPSCR_DN 1 abs 0x00000000 FR_HEX n 1 0x00000000 if sign_of n 0 zero n 0 return PZERO else zero n 1 return NZERO else return DENORM else if abs 0x7ff00000 return NORM else if abs 0x7ff00000 FR_HEX n 1 0x00000000 if sign_of n 0 return PINF else return NINF else if abs 0x7ff80000 return qNaN else return sNaN void register_copy int m n FR n FR m if FPSCR_PR 1 FR n 1 FR m 1 void normal_fad...

Page 377: ...f type FADD srcf f FR m else srcf f FR m dstd d FR n Conversion from single precision to double precision dstd d srcf f if dstd d FR n srcf f 0 0 dstd d srcf f FR n 0 0 set_I if sign_of m sign_of n dstd l 1 1 if dstd l 1 0xffffffff dstd l 0 1 if dstd l 1 0x1fffffff set_I dstf f srcf f Round to nearest if FPSCR_RM 1 dstd l 1 0xe0000000 Round to zero dstf f dstd d check_single_exception FR n dstf f ...

Page 378: ... n 1 0 0 set_I if sign_of m sign_of n dstx l 3 1 if dstx l 3 0xffffffff dstx l 2 1 if dstx l 2 0xffffffff dstx l 1 1 if dstx l 1 0xffffffff dstx l 0 1 if dstx l 2 0x0fffffff dstx l 3 set_I dst d srcd d Round to nearest if FPSCR_RM 1 dstx l 2 0xf0000000 Round to zero dstx l 3 0x00000000 dst d dstx x check_double_exception DR n 1 dst d void normal_fmul int m n union float f int l tmpf union double d...

Page 379: ...set_I if tmpf f tmpd d FPSCR_RM 1 tmpf l 1 Round to zero check_single_exception FR n tmpf f else tmpx x DR n 1 Single precision to double precision tmpx x DR m 1 Precise creation tmpd d DR m 1 Round to nearest if tmpd d tmpx x set_I if tmpd d tmpx x FPSCR_RM 1 tmpd l 1 1 Round to zero if tmpd l 1 0xffffffff tmpd l 0 1 check_double_exception DR n 1 tmpd d void fipr int m n union double d int l 2 ml...

Page 380: ...N data_type_of m 3 qNaN data_type_of n 3 qNaN qnan n 3 else if check_ positive_infinity check_ negative_infinity invalid n 3 else if check_ positive_infinity inf n 3 0 else if check_ negative_infinity inf n 3 1 else for i 0 i 4 i If FPSCR_DN 1 zeroize if data_type_of m i PZERO FR m i 0 0 else if data_type_of m i NZERO FR m i 0 0 if data_type_of n i PZERO FR n i 0 0 else if data_type_of n i NZERO F...

Page 381: ...l 0x7f800000 infinity if result tmp f set_O set_I if FPSCR_RM 1 tmp l 1 Maximum value of normalized number result tmp f if result 0 0 abs result else abs result tmp l 0x00800000 Minimum value of normalized number if abs tmp f if FPSCR_DN 1 abs 0 0 set_I if result 0 0 result 0 0 Zeroize denormalized number else result 0 0 if FPSCR_I 1 set_U if FPSCR ENABLE_OUI fpu_exception_trap else dst result ...

Page 382: ...result tmp d set_O set_I if FPSCR_RM 1 tmp l 0 1 tmp l 1 0xffffffff result tmp d Maximum value of normalized number if result 0 0 abs result else abs result tmp l 0 0x00100000 Minimum value of normalized number tmp l 1 0x00000000 if abs tmp d if FPSCR_DN 1 abs 0 0 set_I if result 0 0 result 0 0 Zeroize denormalized number else result 0 0 if FPSCR_I 1 set_U if FPSCR ENABLE_OUI fpu_exception_trap el...

Page 383: ...product_infinity m 1 n 1 sign_of m 1 sign_of n 1 check_ product_infinity m 2 n 2 sign_of m 2 sign_of n 2 check_ product_infinity m 3 n 3 sign_of m 3 sign_of n 3 int check_ negative_infinity int m n return check_ product_infinity m n sign_of m sign_of n check_ product_infinity m 1 n 1 sign_of m 1 sign_of n 1 check_ product_infinity m 2 n 2 sign_of m 2 sign_of n 2 check_ product_infinity m 3 n 3 sig...

Page 384: ...ption_trap void zero int n sign if sign 0 FR_HEX n 0x00000000 else FR_HEX n 0x80000000 if FPSCR_PR 1 FR_HEX n 1 0x00000000 void inf int n sign if FPSCR_PR 0 if sign 0 FR_HEX n 0x7f800000 else FR_HEX n 0xff800000 else if sign 0 FR_HEX n 0x7ff00000 else FR_HEX n 0xfff00000 FR_HEX n 1 0x00000000 void qnan int n if FPSCR_PR 0 FR n 0x7fbfffff else FR n 0x7ff7ffff FR n 1 0xffffffff ...

Page 385: ... 1 FABS DRn DRn H 7FFFFFFFFFFFFFFF DRn 1111nnn001011101 1 Description This instruction clears the most significant bit of the contents of floating point register FRn DRn to 0 and stores the result in FRn DRn The cause and flag fields in FPSCR are not updated Notes None Operation void FABS int n FR n FR n 0x7fffffff pc 2 Same operation is performed regardless of precision Possible Exceptions None ...

Page 386: ... O U is set FPU exception traps are generated on actual generation by the FPU exception source and on the satisfaction of certain special conditions that apply to this the instruction These special conditions are described in the remaining parts of this section When an exception occurs correct exception information is reflected in FPSCR cause and FPSCR flag and FRn or DRn is not updated Appropriat...

Page 387: ... break break case NINF switch data_type_of n case PINF invalid n break default inf n 1 break break FADD Special Cases FADD FRn DRm FRm DRm NORM NORM 0 0 inf inf qNaN sNaN NORM FADD NORM 0 0 0 0 inf inf inf invalid inf inf invalid inf qNaN qNaN sNaN invalid Note When DN 1 the value of a denormalized number is treated as 0 When DN 0 calculation for denormalized numbers is the same as for normalized ...

Page 388: ... and FRm have the same sign and the exponent of at least one value is H FE FPSCR PR 1 DRn and DRm have the same sign and the exponent of at least one value is H 7FE Underflow Generation of underflow exception traps FPSCR PR 0 FRn and FRm have different signs and neither has an exponent greater than H 18 FPSCR PR 1 DRn and DRm have different signs and neither has an exponent greater than H 035 Inex...

Page 389: ... 1 When FPSCR PR 0 Arithmetically compares the two single precision floating point numbers in FRn and FRm and stores 1 in the T bit if they are equal or 0 otherwise 2 When FPSCR PR 1 Arithmetically compares the two double precision floating point numbers in DRn and DRm and stores 1 in the T bit if they are equal or 0 otherwise 3 When FPSCR PR 0 Arithmetically compares the two single precision floa...

Page 390: ...NVALID fcmp_chk m n UO fcmp_invalid else if fcmp_chk m n GT T 1 else T 0 int fcmp_chk int m n if data_type_of m sNaN data_type_of n sNaN return INVALID else if data_type_of m qNaN data_type_of n qNaN return UO else switch data_type_of m case NORM switch data_type_of n case PINF return GT break case NINF return LT break default break break case PZERO case NZERO switch data_type_of n case PZERO case...

Page 391: ... case NINF switch data_type_of n case NINF return EQ break default return GT break break if FPSCR_PR 0 if FR n FR m return EQ else if FR n FR m return GT else return LT else if DR n 1 DR m 1 return EQ else if DR n 1 DR m 1 return GT else return LT void fcmp_invalid set_V if FPSCR ENABLE_V 0 T 0 else fpu_exception_trap ...

Page 392: ...Invalid Note When DN 1 the value of a denormalized number is treated as 0 FCMP GT FRn DRn FRm DRm NORM DENORM 0 0 INF INF qNaN sNaN NORM CMP GT GT DENORM 0 GT 0 INF GT GT INF GT GT qNaN UO sNaN Invalid Note When DN 1 the value of a denormalized number is treated as 0 UO means unordered Unordered is treated as false GT Possible Exceptions Invalid operation ...

Page 393: ...s set FPU exception traps are generated on actual generation by the FPU exception source and on the satisfaction of certain special conditions that apply to this the instruction These special conditions are described in the remaining parts of this section When an exception occurs correct exception information is reflected in FPSCR cause and FPSCR flag and FPUL is not updated Appropriate processing...

Page 394: ...t abs union float f int l dstf tmpf union double d int l 2 dstd dstd d DR m 1 if dstd l 1 0x1fffffff set_I if FPSCR_RM 1 dstd l 1 0xe0000000 round toward zero dstf f dstd d check_single_exception FPUL dstf f FCNVDS Special Cases DRn NORM NORM 0 0 INF INF qNaN sNaN FCNVDS DRn FPUL FCNVDS FCNVDS 0 0 INF INF qNaN Invalid Note When DN 1 the value of a denormalized number is treated as 0 ...

Page 395: ...Underflow Exception Trap Generating Conditions FPU error Invalid operation Overflow Generation of overflow exception traps The exponent of DRn is not less than H 47E Underflow Generation of underflow exception traps The exponent of DRn is not more than H 380 Inexact ...

Page 396: ...nstruction converts the single precision floating point number in FPUL to a double precision floating point number and stores the result in DRn Notes None Operation void FCNVSD int n float FPUL pc 2 clear_cause case FPSCR_PR 0 undefined_operation reserved 1 fcnvsd n FPUL break FCNVSD void fcnvsd int n float FPUL case fpul_type FPUL PZERO NZERO PINF NINF DR n 1 FPUL break DENORM set_E break qNaN qn...

Page 397: ...if abs 0x7f800000 return NORM else if abs 0x7f800000 if sign_of src 0 return PINF else return NINF else if abs 0x7fc00000 return qNaN else return sNaN FCNVSD Special Cases FRn NORM NORM 0 0 INF INF qNaN sNaN FCNVSD FPUL FRn NORM NORM 0 0 INF INF qNaN Invalid Note When DN 1 the value of a denormalized number is treated as 0 Possible Exceptions FPU error Invalid operation ...

Page 398: ...eption has occurred When FPSCR enable O U is set FPU exception traps are generated on actual generation by the FPU exception source and on the satisfaction of certain special conditions that apply to this the instruction These special conditions are described in the remaining parts of this section When an exception occurs correct exception information is reflected in FPSCR cause and FPSCR flag and...

Page 399: ...case PZERO case NZERO invalid n break case PINF inf n 1 break case NINF inf n 0 break default dz FR n sign_of m sign_of n break break case DENORM set_E break case PINF case NINF switch data_type_of n case DENORM set_E break case PINF case NINF invalid n break default zero n sign_of m sign_of n break break void normal_fdiv int m n union float f int l dstf tmpf union double d int l 2 dstd tmpd union...

Page 400: ... tmpd d set_I if tmpf f tmpd d FPSCR_RM 1 dstf l 1 round toward zero check_single_exception FR n dstf f else tmpd d DR n 1 save destination value dstd d DR m 1 round toward nearest or even tmpx x dstd d convert double to int double tmpx x DR m 1 if tmpd d tmpx x set_I if tmpd d tmpx x FPSCR_RM 1 dstd l 1 1 round toward zero if dstd l 1 0xffffffff dstd l 0 1 check_double_exception DR n 1 dstd d ...

Page 401: ...ed number is treated as 0 Possible Exceptions and Overflow Underflow Exception Trap Generating Conditions FPU error Invalid operation Divide by zero Overflow Generation of overflow exception traps FPSCR PR 0 exponent of FRn exponent of FRm H 7F is not less than H FF FPSCR PR 1 exponent of DRn exponent of DRm H 3FF is not less than H 7FF Underflow Generation of underflow exception traps FPSCR PR 0 ...

Page 402: ...rmed in the following cases 1 If an input value is an sNaN an invalid exception is generated 2 If the input values to be multiplied include a combination of 0 and infinity an invalid exception is generated 3 In cases other than the above if the input values include a qNaN the result will be a qNaN 4 In cases other than the above if the input values include infinity a If multiplication results in t...

Page 403: ...c 2 clear_cause fipr m n else undefined_operation Possible Exceptions and Overflow Exception Trap Generating Conditions Invalid operation Overflow Generation of overflow exception traps At least one of following results is not less than H FC exponent of FRn exponent of FRm exponent of FR n 1 exponent of FR m 1 exponent of FR n 2 exponent of FR m 2 exponent of FR n 3 exponent of FR m 3 Underflow In...

Page 404: ...Point Instruction PR Format Operation Instruction Code Cycle T Bit 0 FLDI0 FRn 0x00000000 FRn 1111nnnn10001101 1 1 Description When FPSCR PR 0 this instruction loads floating point 0 0 0x00000000 into FRn Notes None Operation void FLDI0 int n FR n 0x00000000 pc 2 Possible Exceptions None ...

Page 405: ...ing Point Instruction Format Operation Instruction Code Cycle T Bit FLDI1 FRn 0x3F800000 FRn 1111nnnn10011101 1 Description When FPSCR PR 0 this instruction loads floating point 1 0 0x3F800000 into FRn Notes None Operation void FLDI1 int n FR n 0x3F800000 pc 2 Possible Exceptions None ...

Page 406: ...int Instruction Format Operation Instruction Code Cycle T Bit FLDS FRm FPUL FRm FPUL 1111mmmm00011101 1 Description This instruction loads the contents of floating point register FRm into system register FPUL Notes None Operation void FLDS int m float FPUL FPUL FR m pc 2 Possible Exceptions None ...

Page 407: ...f FPUL as a 32 bit integer converts this integer to a double precision floating point number and stores the result in DRn When FPSCR enable I 1 and FPSCR PR 0 an FPU exception trap is generated regardless of whether or not an exception has occurred When an exception occurs correct exception information is reflected in FPSCR cause and FPSCR flag and FRn is not updated Appropriate processing should ...

Page 408: ...Rev 1 50 10 04 page 388 of 448 Possible Exceptions Inexact Not generated when FPSCR PR 1 ...

Page 409: ...tion by the FPU exception source and on the satisfaction of certain special conditions that apply to this the instruction These special conditions are described in the remaining parts of this section When an exception occurs correct exception information is reflected in FPSCR cause and FPSCR flag and FRn is not updated Appropriate processing should therefore be performed by software Notes None Ope...

Page 410: ...efault inf n sign_of 0 sign_of m break case NORM switch data_type_of n case DENORM set_E break case qNaN qnan n break case PINF case NINF inf n sign_of n break case PZERO case NZERO case NORM normal_fmac m n break break case PZERO case NZERO switch data_type_of m case PINF case NINF invalid n break case PZERO case NZERO case NORM switch data_type_of n case DENORM set_E break case qNaN qnan n break...

Page 411: ...tx tmpx float dstf srcf if data_type_of n PZERO data_type_of n NZERO srcf 0 0 flush denormalized value else srcf FR n tmpx x FR 0 convert single to int double tmpx x FR m exact product dstx x tmpx x srcf if dstx x srcf tmpx x 0 0 dstx x tmpx x srcf 0 0 set_I if sign_of 0 sign_of m sign_of n dstx l 3 1 correct result if dstx l 3 0xffffffff dstx l 2 1 if dstx l 2 0xffffffff dstx l 1 1 if dstx l 1 0x...

Page 412: ...Rev 1 50 10 04 page 392 of 448 dstx l 1 0xfe000000 round toward zero dstx l 2 0x00000000 dstx l 3 0x00000000 dstf dstx x check_single_exception FR n dstf ...

Page 413: ... 0 0 invalid inf inf inf inf inf 0 inf inf inf invalid inf inf NORM FMAC 0 0 inf inf NORM 0 0 inf inf 0 0 0 0 0 0 0 0 0 0 invalid inf inf inf inf inf 0 inf inf inf invalid inf inf NORM inf invalid NORM invalid inf 0 0 inf invalid inf inf invalid inf invalid inf inf invalid inf invalid invalid inf NORM invalid inf NORM inf invalid 0 0 inf invalid inf invalid inf invalid inf inf inf inf invalid inva...

Page 414: ...rmalized numbers is the same as for normalized numbers Possible Exceptions and Overflow Underflow Exception Trap Generating Conditions FPU error Invalid operation Overflow Generation of overflow exception traps At least one of following results is not less than H FD exponent of FR0 exponent of FRm exponent of FRn Underflow Generation of underflow exception traps At least one of following results i...

Page 415: ...Rm R0 Rn 1111nnnnmmm00111 1 Description 1 This instruction transfers FRm contents to FRn 2 This instruction transfers DRm contents to DRn 3 This instruction transfers FRm contents to memory at address indicated by Rn 4 This instruction transfers DRm contents to memory at address indicated by Rn 5 This instruction transfers contents of memory at address indicated by Rm to FRn 6 This instruction tra...

Page 416: ...memory at address indicated by R0 Rn Notes None Operation void FMOV int m n FMOV FRm FRn FR n FR m pc 2 void FMOV_DR int m n FMOV DRm DRn DR n 1 DR m 1 pc 2 void FMOV_STORE int m n FMOV S FRm Rn store_int FR m R n pc 2 void FMOV_STORE_DR int m n FMOV DRm Rn store_quad DR m 1 R n pc 2 void FMOV_LOAD int m n FMOV S Rm FRn load_int R m FR n pc 2 void FMOV_LOAD_DR int m n FMOV Rm DRn load_quad R m DR ...

Page 417: ...nt m n FMOV S FRm Rn store_int FR m R n 4 R n 4 pc 2 void FMOV_SAVE_DR int m n FMOV DRm Rn store_quad DR m 1 R n 8 R n 8 pc 2 void FMOV_INDEX_LOAD int m n FMOV S R0 Rm FRn load_int R 0 R m FR n pc 2 void FMOV_INDEX_LOAD_DR int m n FMOV R0 Rm DRn load_quad R 0 R m DR n 1 pc 2 void FMOV_INDEX_STORE int m n FMOV S FRm R0 Rn store_int FR m R 0 R n pc 2 ...

Page 418: ...e 398 of 448 void FMOV_INDEX_STORE_DR int m n FMOV DRm R0 Rn store_quad DR m 1 R 0 R n pc 2 Possible Exceptions Data TLB miss exception Data protection violation exception Initial page write exception Data address error ...

Page 419: ...XDn DRm XDn 1111nnn1mmm01100 1 Description 1 This instruction transfers XDm contents to memory at address indicated by Rn 2 This instruction transfers contents of memory at address indicated by Rm to XDn 3 This instruction transfers contents of memory at address indicated by Rm to XDn and adds 8 to Rm 4 This instruction subtracts 8 from Rn and transfers XDm contents to memory at address indicated ...

Page 420: ... 1 pc 2 void FMOV_RESTORE_XD int m n FMOV Rm XDn load_quad R m XD n 1 R m 8 pc 2 void FMOV_SAVE_XD int m n FMOV XDm Rn store_quad XD m 1 R n 8 R n 8 pc 2 void FMOV_INDEX_LOAD_XD int m n FMOV R0 Rm XDn load_quad R 0 R m XD n 1 pc 2 void FMOV_INDEX_STORE_XD int m n FMOV XDm R0 Rn store_quad XD m 1 R 0 R n pc 2 void FMOV_XDXD int m n FMOV XDm XDn XD n 1 XD m 1 pc 2 ...

Page 421: ...id FMOV_XDDR int m n FMOV XDm DRn DR n 1 XD m 1 pc 2 void FMOV_DRXD int m n FMOV DRm XDn XD n 1 DR m 1 pc 2 Possible Exceptions Data TLB miss exception Data protection violation exception Initial page write exception Data address error ...

Page 422: ...nable O U is set FPU exception traps are generated on actual generation by the FPU exception source and on the satisfaction of certain special conditions that apply to this the instruction These special conditions are described in the remaining parts of this section When an exception occurs correct exception information is reflected in FPSCR cause and FPSCR flag and FRn or DRn is not updated Appro...

Page 423: ...INF switch data_type_of n case PZERO case NZERO invalid n break default inf n sign_of m sign_of n break break FMUL Special Cases FPSCR PR 0 FMUL FRn FRm NORM NORM 0 0 inf inf qNaN sNaN NORM FMUL 0 0 inf inf NORM 0 0 inf inf 0 0 0 0 0 0 0 0 0 0 invalid inf inf inf inf inf inf inf inf invalid inf inf qNaN qNaN sNaN invalid Note When DN 0 calculation for denormalized numbers is the same as for normal...

Page 424: ...ow Underflow Exception Trap Generating Conditions FPU error Invalid operation Overflow Generation of overflow exception traps FPSCR PR 0 exponent of FRn exponent of FRm H 7F is not less than H FE FPSCR PR 1 exponent of DRn exponent of DRm H 3FF is not less than H 7FE Underflow Generation of underflow exception traps FPSCR PR 0 When both FRn and FRm are normalized numbers exponent of FRn exponent o...

Page 425: ...1 1 1 FNEG DRn DRn H 8000000000000000 DRn 1111nnn001001101 1 Description This instruction inverts the most significant bit sign bit of the contents of floating point register FRn DRn and stores the result in FRn DRn The cause and flag fields in FPSCR are not updated Notes None Operation void FNEG int n FR n FR n pc 2 Same operation is performed regardless of precision Possible Exceptions None ...

Page 426: ...de Cycle T Bit FPCHG FPSCR PR FPSCR PR 1111011111111101 1 Description This instruction inverts the PR bit of the floating point status register FPSCR The value of this bit selects single precision or double precision operation Notes None Operation void FPCHG FPCHG FPSCR 0x00080000 bit 19 PC 2 Possible Exceptions None ...

Page 427: ...R0 to FR15 in FPR0_BANK0 to FPR15_BANK0 and FPR0_BANK1 to FPR15_BANK1 become XR0 to XR15 and XR0 to XR15 become FR0 to FR15 When FPSCR FR 0 FPR0_BANK0 to FPR15_BANK0 correspond to FR0 to FR15 and FPR0_BANK1 to FPR15_BANK1 correspond to XR0 to XR15 When FPSCR FR 1 FPR0_BANK1 to FPR15_BANK1 correspond to FR0 to FR15 and FPR0_BANK0 to FPR15_BANK0 correspond to XR0 to XR15 Notes None Operation void FR...

Page 428: ...struction is an approximate operation instruction an imprecision exception is always required even if the input is a 0 the result is imprecise When FPSCR enable I is set an FPU exception trap is generated When an exception occurs correct exception information is reflected in FPSCR cause and FPSCR flag and FRn and FR n 1 is not updated Appropriate processing should therefore be performed by softwar...

Page 429: ... is specified as shown below i e as a signed fraction in twos complement The result of sin cos is a single precision floating point number 0x7FFFFFFF to 0x00000001 360 215 360 216 to 360 216 degrees 0x00000000 0 degree 0xffffffff to 0x80000000 360 216 to 360 215 degrees Possible Exceptions Inexact ...

Page 430: ...FPSCR Changing the value of the SZ bit in FPSCR switches the amount of data for transfer by the FMOV instruction between one single precision data and a pair of single precision data When FPSCR SZ 0 an FMOV instruction transfers a single precision number When FPSCR SZ 1 the FMOV instruction transfers a pair of single precision numbers Notes None Operation void FSCHG FSCHG if FPSCR_PR 0 FPSCR 0x001...

Page 431: ...e root of the double precision floating point number in DRn and stores the result in DRn When FPSCR enable I is set an FPU exception trap is generated regardless of whether or not an exception has occurred When an exception occurs correct exception information is reflected in FPSCR cause and FPSCR flag and FRn or DRn is not updated Appropriate processing should therefore be performed by software N...

Page 432: ...e to double tmpd d dstf f if tmpf f tmpd d set_I if tmpf f tmpd d FPSCR_RM 1 dstf l 1 round toward zero if FPSCR ENABLE_I fpu_exception_trap else FR n dstf f else tmpd d DR n 1 save destination value dstd d sqrt DR n 1 round toward nearest or even tmpx x dstd d convert double to int double tmpx x dstd d if tmpd d tmpx x set_I if tmpd d tmpx x FPSCR_RM 1 dstd l 1 1 round toward zero if dstd l 1 0xf...

Page 433: ...al Cases FRn NORM NORM DENORM DENORM 0 0 INF INF qNaN sNaN FSQRT FRn SQRT Invalid Error Error 0 0 INF Invalid qNaN Invalid Note When DN 1 the value of a denormalized number is treated as 0 Possible Exceptions FPU error Invalid operation Inexact ...

Page 434: ...operates by approximation an imprecision exception is required when the input is a normalized value In other cases the instruction does not require an imprecision exception When FPSCR enable I is set an FPU exception trap is generated When an exception occurs correct exception information is reflected in FPSCR cause and FPSCR flag and FRn is not updated Appropriate processing should therefore be p...

Page 435: ... qnan n break sNAN invalid n break FSRRA Special Cases FRn NORM NORM DENORM DENORM 0 0 INF INF qNaN sNaN FSRRA FRn 1 SQRT Invalid Error Invalid DZ DZ 0 Invalid qNaN Invalid Note When DN 1 the value of denormalized number is treated as 0 Possible Exceptions FPU error Invalid operation Divided by Zero Inexact ...

Page 436: ...t Instruction Format Operation Instruction Code Cycle T Bit FSTS FPUL FRn FPUL FRn 1111nnnn00001101 1 Description This instruction transfers the contents of system register FPUL to floating point register FRn Notes None Operation void FSTS int n float FPUL FR n FPUL pc 2 Possible Exceptions None ...

Page 437: ... or not an exception has occurred When FPSCR enable O U is set FPU exception traps are generated on actual generation by the FPU exception source and on the satisfaction of certain special conditions that apply to this the instruction These special conditions are described in the remaining parts of this section When an exception occurs correct exception information is reflected in FPSCR cause and ...

Page 438: ...eak break case NINF switch data_type_of n case NINF invalid n break default inf n 0 break break FSUB Special Cases FSUB FRn DRn FRm DRm NORM NORM 0 0 inf inf qNaN sNaN NORM FSUB NORM 0 0 0 0 inf inf inf invalid inf inf inf invalid qNaN qNaN sNaN invalid Notes When DN 1 the value of a denormalized number is treated as 0 When DN 0 calculation for denormalized numbers is the same as for normalized nu...

Page 439: ... and FRm have the different signs and the exponent of at least one value is H FE FPSCR PR 1 DRn and DRm have the different signs and the exponent of at least one value is H 7FE Underflow Generation of underflow exception traps FPSCR PR 0 FRn and FRm have same sign and neither has an exponent greater than H 18 FPSCR PR 1 DRn and DRm have same sign and neither has an exponent greater than H 035 Inex...

Page 440: ...result in FPUL When FPSCR PR 1 Converts the double precision floating point number in FRm to a 32 bit integer and stores the result in FPUL The rounding mode is always truncation Notes None Operation define N_INT_SINGLE_RANGE 0xcf000000 0x7fffffff 1 000000 2 31 define P_INT_SINGLE_RANGE 0x4effffff 1 fffffe 2 30 define N_INT_DOUBLE_RANGE 0xc1e0000000200000 0x7fffffffffffffff define P_INT_DOUBLE_RAN...

Page 441: ...eturn PINF out of range INF else return NORM 0 NORM else if FR_HEX m 0x7fffffff N_INT_SINGLE_RANGE return NINF out of range INF NaN else return NORM 0 NORM int ftrc_double_type_of int m if sign_of m 0 if FR_HEX m 0x7ff00000 FR_HEX m 0x7ff00000 FR_HEX m 1 0x00000000 return NINF NaN else if DR_HEX m 1 P_INT_DOUBLE_RANGE return PINF out of range INF else return NORM 0 NORM else if DR_HEX m 1 0x7fffff...

Page 442: ... 0x80000000 else fpu_exception_trap FTRC Special Cases FRn DRn NORM 0 0 Positive Out of Range Negative Out of Range INF INF qNaN sNaN FTRC FRn DRn TRC 0 0 Invalid MAX Invalid MAX Invalid MAX Invalid MAX Invalid MAX Invalid MAX Note When DN 1 the value of a denormalized number is treated as 0 Possible Exceptions Invalid operation ...

Page 443: ...lts will differ from those obtained by using a combination of FADD and FMUL instructions The FTRV execution sequence is as follows 1 Multiplies all terms The results are 28 bits long 2 Aligns these results rounding them to fit within 30 bits 3 Adds the aligned values 4 Performs normalization and rounding Special processing is performed in the following cases 1 If an input value is an sNaN an inval...

Page 444: ...software Notes None Operation void FTRV int n FTRV FVn float saved_vec 4 result_vec 4 int saved_fpscr int dst i if FPSCR_PR 0 PC 2 clear_cause saved_fpscr FPSCR FPSCR ENABLE_VOUI mask VOUI enable dst 12 n select other vector than FVn for i 0 i 4 i saved_vec i FR dst i for i 0 i 4 i for j 0 j 4 j FR dst j XF i 4j fipr n dst saved_fpscr FPSCR CAUSE FLAG result_vec i FR dst 3 for i 0 i 4 i FR dst i s...

Page 445: ...Rev 1 50 10 04 page 425 of 448 Possible Exceptions Invalid operation Overflow Underflow Inexact ...

Page 446: ...Rev 1 50 10 04 page 426 of 448 ...

Page 447: ...ers Access to reserved addresses which are not described in this list is disabled Register States in Each Operating Mode Register states are described in the same order as the Register Addresses by functional module in order of the corresponding section numbers For the initial state of each bit refer to the description of the register in the corresponding section The register states described are ...

Page 448: ...T R W H FF00 0028 H 1F00 0028 32 MMU Page table entry high register PTEH R W H FF00 0000 H 1F00 0000 32 Page table entry low register PTEL R W H FF00 0004 H 1F00 0004 32 Translation table base register TTB R W H FF00 0008 H 1F00 0008 32 TLB exception address register TEA R W H FF00 000C H 1F00 000C 32 MMU control register MMUCR R W H FF00 0010 H 1F00 0010 32 Physical address space control register...

Page 449: ...ess register 1 LSA1 R W H FF00 0054 H 1F00 0054 32 L memory transfer destination address register 0 LDA0 R W H FF00 0058 H 1F00 0058 32 L memory transfer destination address register 1 LDA1 R W H FF00 005C H FF00 005C 32 Note The P4 address is the address used when using P4 area in the virtual address space The area 7 address is the address used when accessing from area 7 in the physical address s...

Page 450: ... 0000 0000 H 0000 0000 Retained Retained Physical address space control register PASCR H 0000 0000 H 0000 0000 Retained Retained Instruction re fetch inhibit control register IRMCR H 0000 0000 H 0000 0000 Retained Retained Cache Cache control register CCR H 0000 0000 H 0000 0000 Retained Retained Queue address control register 0 QACR0 Undefined Undefined Retained Retained Queue address control reg...

Page 451: ...ruction not the access from SuperHyway bus master except CPU After the CPUOPM is updated read CPUOPM once and execute one of the following two methods 1 Execute a branch using the RTE instruction 2 Execute the ICBI instruction for any address including non cacheable area After one of these methods are executed it is guaranteed that the CPU runs under the updated CPUOPM value Bit Initial value R W ...

Page 452: ...issued speculatively When this bit is set to 0 refer to Appendix C Speculative Execution for Subroutine Return 1 Instruction fetch for subroutine return is not issued speculatively 4 0 R Reserved The write value must be the initial value 3 INTMU 0 R W Interrupt mode switch bit 0 SR IMASK is not changed when an interrupt is accepted 1 SR IMASK is changed to the accepted interrupt level 2 to 0 All 0...

Page 453: ...ase in which the instruction ADD indicated by the program counter PC and the address H 04000002 instruction prefetch are executed simultaneously It is also assumed that the program branches to an area other than area 1 after executing the following JMP instruction and delay slot instruction In this case a bus access instruction prefetch to area 1 may unintentionally occur from the programming flow...

Page 454: ...culative instruction fetch may issue the access to the address that should not be accessed from the program Therefore a bus access to an unexpected area or an internal instruction address error may cause a problem As for the effect of this bus access to unexpected memory area refer to Appendix B Instruction Prefetching and Its Side Effects Usage Condition When the speculative execution for subrout...

Page 455: ... Processor version register PVR R H FF000030 H 1F000030 32 Product register PRR R H FF000044 H 1F000044 32 Processor Version Register PVR R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 R R R R R R R R R R R R R R R R 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 0 0 0 1 0 0 0 0 R R R R R R R CHIP VER CUT Bit Initial value R W Bit Initial value R W Bit Bit Name Initial Value R W Descript...

Page 456: ... 16 All 0 R Reserved For details on reading from or writing to these bits see description in General Precautions on Handling of Product 15 to 8 Product R Major Version This value is changed when performing major enhancement of the product It differs from one product to another 7 to 4 CUT R Minor Version This value is changed when performing minor enhancement of the product It differs from one prod...

Page 457: ...able 1 1 Features CPU 1 Amended RISC type instruction set upward compatible with the SH 1 SH 2 SH 3 and SH 4 microcomputers Table 1 1 Features L memory 3 Amended Two independent read write ports 8 16 32 64 bit access from the CPU 8 16 32 64 bit and 16 32 byte access from the external devices Note For the size of L memory see the hardware manual of the target product Table 1 2 Changes from SH 4 to ...

Page 458: ...ay bits are modified according to the size modification and changed into 4 way set associative cache 8 8 Notes on Using 32 Bit Address Extended Mode Newly added 9 L Memory Newly added 9 instructions are added as CPU instructions 10 Instruction Descriptions 3 instructions are added as FPU instructions 2 2 4 Control Registers Status Register SR 15 Amended Bit Bit Name Initial Value R W Description 1...

Page 459: ...le Z 1 and division with a zero divisor or the input of FSRRA is zero Figure 7 4 P4 Area 118 Amended Operand cache data array Unified TLB and PMB address array Unified TLB and PMB data array H F800 0000 H F700 0000 H F600 0000 7 1 1 Address Spaces P4 Area 119 Added The area from H F610 0000 to H F61F FFFF is used for direct access to the PMB address array For details see section 7 7 5 Memory Mappe...

Page 460: ...e next bus access 1 The CPU waits for the end of writing bus access and starts the next bus access 7 2 7 Instruction Re Fetch Inhibit Control Register IRMCR 129 130 Amended Bit Bit Name Initial Value R W 4 R2 0 R W 3 R1 0 R W 2 LT 0 R W 7 7 32 Bit Address Extended Mode 151 to 158 Added Section 8 Caches 159 Note added 8 5 1 Coherency between Cache and External Memory 175 Deleted 1Kbyte page size ca...

Page 461: ...CR AT 0 or RAMCR RP 0 The transfer source physical address in block transfer to page 0 in the L memory is set in the L0SADR bits of the LSA0 register And the L0SSZ bits in the LSA0 register choose either the virtual addresses specified through the PRFF instruction or the L0SADR values as bits 15 to 10 of the transfer source physical address In other words the transfer source area can be specified ...

Page 462: ...not generate data address error and MMU exceptions In the event of an error the PREFI instruction is treated as an NOP no operation instruction 10 1 76 SYNCO Synchronize Data Operation 333 Amended Format Operation SYNCO Data accesses invoked by the following instruction are not executed until execution of data accesses which precede this instruction has been completed 10 1 76 SYNCO Synchronize Dat...

Page 463: ...e store 10 1 80 XOR Exclusive OR Logical Possible Exceptions 340 Added Exceptions are checked taking a data access by this instruction as a byte load and a byte store 10 3 19 FSCA Floating Point Sine And Cosine Approximate Description 408 Amended absolute error is within 2 21 10 3 22 FSRRA Floating Point Square Reciprocal Approximate Description 414 Added This instruction takes the approximate inv...

Page 464: ...the updated CPUOPM value Appendix A 432 Amended Bit Bit Name Initial Value R W Description 31 to 6 H 000000F R Reserved The write value must be the initial value 5 RABD 1 R W Speculative execution bit for subroutine return 0 Instruction fetch for subroutine return is issued speculatively When this bit is set to 0 refer to Appendix C Speculative Execution for Subroutine Return 1 Instruction fetch f...

Page 465: ...ng point control instructions 41 Floating point double precision instructions 41 Floating point graphics acceleration instructions 42 Floating point registers 9 12 Floating point single precision instructions 40 FPU error 109 FPU exception 90 FPU exception handling 110 FPU Exception sources 109 General FPU disable exception 87 General FPU disable exceptions and slot FPU disable exceptions 109 Gene...

Page 466: ... 430 LDA0 193 429 430 LDA1 195 429 430 LSA0 190 429 430 LSA1 191 429 430 MACH 16 MACL 16 MMUCR 125 428 430 PASCR 128 428 430 PC 16 PR 16 PRR 436 PTEH 122 428 430 PTEL 123 428 430 PVR 435 QACR0 165 428 430 QACR1 166 428 430 RAMCR 167 189 428 430 SGR 16 SPC 15 SR 14 SSR 15 TEA 124 428 430 TRA 66 428 430 TTB 124 428 430 VBR 16 Relative priorities 70 Reset state 21 Rounding 108 Share status bit 132 Sh...

Page 467: ... 04 page 447 of 448 Unconditional trap 84 Underflow 109 User mode 8 UTLB 131 UTLB address array 149 UTLB data array 150 Validity bit 132 Vector addresses 70 Virtual address space 115 VPN 131 Write through bit 133 ...

Page 468: ...Rev 1 50 10 04 page 448 of 448 ...

Page 469: ...ate Rev 1 00 Nov 27 2003 Rev 1 50 Oct 29 2004 Published by Sales Strategic Planning Div Renesas Technology Corp Edited by Technical Documentation Information Department Renesas Kodaira Semiconductor Co Ltd 2004 Renesas Technology Corp All rights reserved Printed in Japan ...

Page 470: ... Fax 44 1628 585 900 Renesas Technology Hong Kong Ltd 7th Floor North Tower World Finance Centre Harbour City 1 Canton Road Tsimshatsui Kowloon Hong Kong Tel 852 2265 6688 Fax 852 2730 6071 Renesas Technology Taiwan Co Ltd 10th Floor No 99 Fushing North Road Taipei Taiwan Tel 886 2 2715 2888 Fax 886 2 2713 2999 Renesas Technology Shanghai Co Ltd Unit2607 Ruijing Building No 205 Maoming Road S Shan...

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Page 472: ...SH 4A Software Manual ...

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