Renesas SuperH SH-4A, Software Manual

Page: 143 / 472

Rev. 1.50, 10/04, page 123 of 448
7.2.2 Page Table Entry Low Register (PTEL)
PTEL is used to hold the physical page number and page management information to be recorded
in the UTLB by means of the LDTLB instruction. The contents of this register are not changed
unless a software directive is issued.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Bit:
0 0 0
0
Initial value:
R R R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
R/W R/W R/W
PPN
PPN V SZ1 PR1 PR0 SZ0 C D SH WT
R/W R/W R/W R/W R/W
R/W:
Bit:
Initial value:
R/W:
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R R/W R/W R/W R/W R/W R/W R/W
Bit Bit Name
Initial
Value R/W
Description
31 to 29

All 0 R Reserved
For details on reading from or writing to these bits, see
description in General Precautions on Handling of
Product.
28 to 10 PPN

R/W Physical Page Number
9

0 R Reserved
For details on reading from or writing to this bit, see
description in General Precautions on Handling of
Product.
8 V

R/W
7 SZ1

R/W
6 PR1

R/W
5 PR0

R/W
4 SZ0

R/W
3 C

R/W
2 D

R/W
1 SH

R/W
0 WT

R/W
Page Management Information
The meaning of each bit is same as that of
corresponding bit in Common TLB (UTLB).
For details, see section 7.3, TLB Functions.