Renesas SuperH SH-4A, Software Manual

Page: 263 / 472

Rev. 1.50, 10/04, page 243 of 448
10.1.23 ICBI (Instruction Cache Block Invalidate): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
ICBI @Rn
Invalidates the instruction
cache block indicated by
logical address Rn
0000nnnn11100011
13 —
Description: This instruction accesses the instruction cache at the effective address indicated by
the contents of Rn. When the cache is hit, the corresponding cache block is invalidated (the V bit
is cleared to 0). At this time, write-back is not performed. No operation is performed in the case of
a cache miss or access to a non-cache area.
Notes: None
Operation:
ICBI(int n) /* ICBI @Rn */
{
invalidate_instruction_cache_block(R[n]);
PC += 2;
}
Example: When a program is overwriting RAM to modify its own execution, the corresponding
block of the instruction cache should be invalidated by the ICBI instruction. This prevents
execution of the program from the instruction cache, where the non-overwritten instructions are
stored.
Possible Exceptions: Exceptions may occur when invalidation is not performed.
•
Instruction TLB multiple-hit exception
•
Instruction TLB miss exception
•
Instruction TLB protection violation exception
•
Instruction address error
•
Slot illegal instruction exception