Renesas SuperH SH-4A, Software Manual

Page: 310 / 472

Rev. 1.50, 10/04, page 290 of 448
10.1.47 OCBI (Operand Cache Block Invalidate): Data Transfer Instruction
Format Operation Instruction Code Cycle T Bit
OCBI @Rn
Operand cache block
invalidation
0000nnnn10010011
1 —
Description: This instruction accesses data using the contents indicated by effective address Rn.
In the case of a hit in the cache, the corresponding cache block is invalidated (the V bit is cleared
to 0). If there is unwritten information (U bit = 1), write-back is not performed even if write-back
mode is selected. No operation is performed in the case of a cache miss or an access to a non-
cache area.
Notes: None
Operation:
OCBI(int n) /* OCBI @Rn */
{
invalidate_operand_cache_block(R[n]);
PC += 2;
}
Possible Exceptions:
•
Data TLB multiple-hit exception
•
Data TLB miss exception
•
Data TLB protection violation exception
•
Initial page write exception
•
Data address error
Note that the above exceptions are generated even if OCBI does not operate.