Renesas SuperH SH-4A, Software Manual

Page: 182 / 472

Rev. 1.50, 10/04, page 162 of 448
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Data array
The data field holds 32 bytes (256 bits) of data per cache line. The data array is not initialized
by a power-on or manual reset.
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LRU
In a 4-way set-associative method, up to 4 items of data can be registered in the cache at each
entry address. When an entry is registered, the LRU bit indicates which of the 4 ways it is to be
registered in. The LRU mechanism uses 6 bits of each entry, and its usage is controlled by
hardware. The LRU (least-recently-used) algorithm is used for way selection, and selects the
less recently accessed way. The LRU bits are initialized to 0 by a power-on reset but not by a
manual reset. The LRU bits cannot be read from or written to by software.
8.2 Register Descriptions
The following registers are related to cache.
Table 8.3 Register Configuration
Register Name Abbreviation R/W P4 Address * Area 7 Address * Size
Cache control register CCR R/W H
'
FF00 001C H
'
1F00 001C 32
Queue address control register 0 QACR0 R/W H
'
FF00 0038 H
'
1F00 0038 32
Queue address control register 1 QACR1 R/W H
'
FF00 003C H
'
1F00 003C 32
On-chip memory control register RAMCR R/W H
'
FF00 0074 H
'
1F00 0074 32
Note: * These P4 addresses are for the P4 area in the virtual address space. These area 7
addresses are accessed from area 7 in the physical address space by means of the
TLB.
Table 8.4 Register States in Each Processing State
Register Name Abbreviation Power-on Reset Manual Reset Sleep Standby
Cache control register CCR H
'
0000 0000 H
'
0000 0000 Retained Retained
Queue address control register 0 QACR0 Undefined Undefined Retained Retained
Queue address control register 1 QACR1 Undefined Undefined Retained Retained
On-chip memory control register RAMCR H
'
0000 0000 H
'
0000 0000 Retained Retained