Renesas F-ZTAT H8/3642A Series, Hardware Manual, Page: 366 / 551

Section 11 14-Bit PWM
Rev. 6.00 Sep 12, 2006 page 344 of 526
REJ09B0326-0600
Upon reset, PWDRU and PWDRL are initialized to H'C000.
11.3 Operation
When using the 14-bit PWM, set the registers in the following sequence.
1. Set bit PWM in port mode register 1 (PMR1) to 1 so that pin P1
4
/PWM is designated for PWM
output.
2. Set bit PWCR0 in the PWM control register (PWCR) to select a conversion period of either
32,768/
φ
(PWCR0 = 1) or 16,384/
φ
(PWCR0 = 0).
3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in
the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data
in these registers will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 11.2. The total of the high-
level pulse widths during this period (T
H
) corresponds to the data in PWDRU and PWDRL.
This relation can be represented as follows.
T
H
= (data value in PWDRU and PWDRL + 64)
×
t
φ
/2
where t
φ
is the PWM input clock period, either 2/
φ
(bit PWCR0 = 0) or 4/
φ
(bit PWCR0 = 1).
Example: Settings in order to obtain a conversion period of 8,192 µs:
When bit PWCR0 = 0, the conversion period is 16,384/
φ
, so
φ
must be 2 MHz. In
this case t
fn
= 128 µs, with 1/
φ
(resolution) = 0.5 µs.
When bit PWCR0 = 1, the conversion period is 32,768/
φ
, so
φ
must be 4 MHz. In
this case t
fn
= 128 µs, with 2/
φ
(resolution) = 0.5 µs.
Accordingly, for a conversion period of 8,192 µs, the system clock frequency (
φ
)
must be 2 MHz or 4 MHz.
1 conversion period
t
f1
t
f2
t
f63
t
f64
t
H1
t
H2
t
H3
t
H63
t
H64
T = t + t + t +
t = t = t
H H1 H2 H3 H64
..... t
f1 f2 f3
..... = t
f64
Figure 11.2 PWM Output Waveform