Renesas F-ZTAT H8/3642A Series, Hardware Manual, Page: 272 / 551

Section 9 Timers
Rev. 6.00 Sep 12, 2006 page 250 of 526
REJ09B0326-0600
Timer Control Register X (TCRX)
Bit 7 6 5 4 3 2 1 0
IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
Initial value 0 0 0 0 0 0 0 0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W
TCRX is an 8-bit read/write register that selects the valid edges of the input capture signals,
enables buffering, and selects the FRC clock source.
TCRX is initialized to H'00 upon reset and in standby mode, watch mode, subsleep mode, and
subactive mode.
Bit 7
   
Input Edge Select A (IEDGA): Bit 7 selects the rising or falling edge of the input capture
A input signal (FTIA).
Bit 7: IEDGA Description
0 Falling edge of input capture A is captured (initial value)
1 Rising edge of input capture A is captured
Bit 6

 

Input Edge Select B (IEDGB): Bit 6 selects the rising or falling edge of the input capture
B input signal (FTIB).
Bit 6: IEDGB Description
0 Falling edge of input capture B is captured (initial value)
1 Rising edge of input capture B is captured
Bit 5
   
Input Edge Select C (IEDGC): Bit 5 selects the rising or falling edge of the input capture
C input signal (FTIC).
Bit 5: IEDGC Description
0 Falling edge of input capture C is captured (initial value)
1 Rising edge of input capture C is captured