Renesas F-ZTAT H8/3642A Series, Hardware Manual, Page: 281 / 551

Section 9 Timers
Rev. 6.00 Sep 12, 2006 page 259 of 526
REJ09B0326-0600
Input Capture Timing
•
Input capture timing
The rising or falling edge is selected for input capture by bits IEDGA to IEDGD in TCRX.
Figure 9.24 shows the timing when the rising edge is selected (IEDGA/B/C/D = 1).
Input capture
signal
φ
Input capture
pin
Figure 9.24 Input Capture Signal Timing (Normal Case)
If the input at the input capture pin occurs while the upper byte of the corresponding input
capture register (ICRA to ICRD) is being read, the internal input capture signal is delayed by
one system clock (
φ
). Figure 9.25 shows the timing.
Input capture
signal
φ
Input capture
pin
T
1
T
2
T
3
ICRA to ICRD upper byte read cycle
Figure 9.25 Input Capture Signal Timing (during ICRA to ICRD Read)