R&S EM510, Manual

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EM510 Remote Control via LAN
4065.7763.32-01.00 5.132
5.5.3 Description of the Status Registers
5.5.3.1 Status Byte (STB) and Service Request Enable Register (SRE)
The STB is already defined in IEEE 488.2. It provides an overview of the device status by collecting the
pieces of information of the lower registers. It can thus be compared with the CONDition section of an
SCPI register and assumes the highest level within the SCPI hierarchy. A special feature is that bit 6
acts as the summary bit of the remaining bits of the status byte.
The STATUS BYTE is read out using the command "
*STB?
" or a "serial poll".
The STB implies the SRE. As to its function, it corresponds to the ENABle section of the SCPI register.
A bit in the SRE is assigned to each bit of the STB. Bit 6 of the SRE is ignored. If a bit is set in the SRE
and the associated bit in the STB changes from 0 to 1, a Service Request (SRQ) is generated, which
triggers an interrupt in the controller if this is appropriately configured.
The SRE can be set using command "
*SRE
" and read using "
*SRE?
".
Table 5-1:
Bit allocation of status byte
Bit no. Meaning
0
EXTended status register summary bit
The bit is set if an EVENt bit is set in the EXTended status register and if the corresponding ENABle bit is set to 1.
The states of the hardware functions and change bits are combined in the EXTended status register.
1
TRACe status register summary bit
The bit is set if an EVENt bit is set in the TRACe status register and if the corresponding ENABle bit is set to 1.
The states of the TRACes MTRACE, ITRACE, SSTART and SSTOP are represented in the TRACe status
register.
2
Error Queue not empty
The bit is set when the error queue contains an entry.
If this bit is enabled by the SRE, an entry into the empty error queue generates a service request.
Thus, an error can be recognized and specified in greater detail by polling the error queue. The poll provides an
informative error message. This procedure is recommended since it considerably reduces the problems involved
with the control.
3
QUEStionable status register summary bit
The bit is set if an EVENt bit is set in the QUEStionable status register and the corresponding ENABle bit is set to
1. A set bit indicates a questionable device status which can be specified in greater detail by polling the
QUEStionable status register.
4
MAV bit (message available)
No meaning
5
ESB bit
Summary bit of the EVENt status register. It is set if one of the bits in the EVENt status register is set and enabled
in the EVENt status enable register.
Setting this bit implies a serious error which can be specified in greater detail by polling the EVENt status register.