User Manual 3162A/B
Maintenance and Performance Checks 5-31
S t e p
Test Point
Expected Result
1
J4 pin 6
Positive going TTL level pulses, 312.5 kHz, pulse width 800 ns
2
U81 pin 9
Negative going TTL level pulses, 312.5 kHz, pulse width 800 ns
3
U63, U73 pins 5 and 6
Positive going TTL level pulses, 104.2 kHz, pulse width 3.2
µ
s
The next check is done on the Model 3162B configured to operate in sequence
mode as before, however each segment has a different clock divider number.
Use the following commands to configure the Model 3162B:
Remote Commands:
:FUNC:MODE SEQ
:SEQ:DEF 1,1,1
:SEQ:DEF 2,2,2
:SEQ:DEF 3,3,4
:OUTP ON
Proceed with the checks given in Table 5-8.
Table 5-8 Sequence Generator & Clock Divider Checks
S t e p
Test Point
Expected Result
1
U59 pin 24
Negative going ECL level pulses. Each sequence cycle is 22.4
µ
s. Three
pulses in each cycle: 800 ns, 1.6
µ
s, and 3.2
µ
s
2
U78 pin 13,
U87 pin 13
Positive going ECL level pulses. Each sequence cycle is comprised of 12
cycles. Cycle 1 through 4, period = 800 ns, pulse width 100 ns. Cycle 5
through 8, period = 1600 ns, pulse width 200 ns. Cycle 9 through 12, period
= 3.2
µ
s, pulse width 400 ns
3
U95 pin 7
ECL level pulses, 3.2
µ
s low level, 32 each 5 MHz clocks (6.4
µ
s duration),
and 32 each 2.5 MHz clocks (12.8
µ
s duration)
Summary of Contents for 3162A/B
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Page 10: ...3162A B User Manual vi Support Offices 6 2...
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Page 17: ...User Manual 3162A B Getting Started 1 5 Figure 1 2 The Front Panel...
Page 23: ...User Manual 3162A B Getting Started 1 11 Figure 1 7 WaveCAD Example...
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