Racal Instruments 3162A/B, User Manual

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Specifications A-1
Appendix A
SPECIFICATIONS
VXIbus General Information
Module Form Single slot VXIbus C-size module
Connectors P1, P2
Protocol A16/A24/D16 Slave, Message-Based
VXIbus Revision 1.4
SCPI Revision 1993.0
Logical Address Settings 1 - 255, configured via DIP switches
Interrupt Level Settings 1 - 7, configured dynamically (no DIP switch)
Shared Memory A32, D16, 1Meg
Sample Clock
Range: Internal, from internal synthesizer, 100mHz to 500MHz
Internal Synthesizer Reference Sources:
Standard
≥
0.0001% (1ppm) initial tolerance over a 19
°
C to 29
°
C
temperature range; 1ppm/
°
C below 19
°
C and above 29
°
C;
1ppm/year aging rate
External From Front Panel BNC, 10 MHz Nominal
Other Synthesizer Specifications
Range 100mHz to 500MHz,
Resolution 7 digits
Accuracy Same as reference
Stability Same as reference
Internal Synthesizer Agility
Frequency hopping
Operation Permits the selection of sample clock (carrier sample clock)
dividing ratio. Sample clock hops between 256 pre-
determined steps
Hop Control Source 1) Front panel 9 pin D-Sub connector;
2) Front panel TRIG IN connector;
3) VXIbus TTLTrg0-3, ECLTrg0
Sample Clock Selection D-Sub - binary combination of 8 lines determines the next
division ratio; Trigger - determines the next division ratio.
Carrier Sample Clock Range 100mHz to 300MHz
Ratio Between Carrier and
Hop Frequencies
1 through 65536
Hop Table 256 hop frequencies
Hop Delay Next frequency delayed until last cycle is com 100ns.