Panasonic AJ-YA120AG, Service Manual

Page: 98 / 647

OVERALL BLOCK DIAGRAM
HD SDI IN
(W/AUDIO)
HD SDI OUT1
(W/AUDIO)
HD SDI OUT2
(W/AUDIO)
Vide
o
AUDIO
P/S
W/T
DRIVE
AUDIO
ENC.
SD SYSH
(FPGA)
AUDIO
DLY
MUX
FPGA
SEARCH
DV
MICROPROCESSOR
PREPRO
100
PREPRO
50
COMP
100
A B
COMP
100
C D
ECC
200
RF CTRL
PLD
(PB)
DRAM
SDRAM SDRAM
A BUS
B BUS
C BUS
D BUS
A,B
C,D
A
B
C
D
A
B
C
D
DRAM
SDRAM
HD PB
PB
REC/EE
FPGA
SDRAM
COMP
100
BUS MUX
DUEL
(LINK)
SDRAM
1394
MICROPROCESSOR
PHY
X’TAL
IEEE1394
CONNECTOR
SD
FPGA
PB
PR
AUX
SD SDI OUT1
(W/AUDIO)
SDRAM
IF
FPGA
SDRAM
HEAD PHONES VR
CYL/CAP
MICROPROCESSOR
SYS/IF/AV
MICROPROCESSOR
BACK UP
MEMORY
A/D
VCA
TC IN
TC OUT
REMOTE
D/A
AUDIO IN
(ANALOG)
AUDIO OUT
(ANALOG)
INT
SG.
VIDEO OUT1/
YG OUT
VIDEO OUT2
INT SG
ANA IN
DIG IN
CYL
DRIVE
CAP
DRIVE
CAP
MOTOR
CYL
MOTOR
CTL REC/PB
REEL
MICROPROCESSOR
REEL
DRIVE
T REEL
MOTOR
S REEL
MOTOR
MOTOR
DRIVE
LOAD.
MOTOR
SOL
DRIVE
ERASE
DRIVE
ERASE
DRIVE
PB EQ A/D
REC EQ D/A
CUE ERASE
CTL ERASE
CUE REC
OR PB
VR S/P P/S
DLY
SRC
S/P MUTE P/S
HP
SEL
RAM
HEAD
AMP
EQ
REC
AMP
HD
SD
ACTIVE THRU
CHANNEL
LINK
AV
TIMING
ADJ
V LOCK
PLL
LC & UC
PAVCAL LSI
IP
LC PLD
HD
Y,C
CHARA
GEN
SDI (AJ-YA120AG)
Line Conv (AJ-YA120AG)
REC PB
APROC
RF/CUE
RF/
EQ
IEEE1394 (AJ-YAD120AG)
SERVO
SYS-CON
SDRAM SDRAM SDRAM
V OUT
KEY I/F DISPLAY VAR
FRONT
FILTER
HD
FPGA
VIDEO
VIDEO HEADS
SOLENOIDS
BIAS
OSC
SD SDI OUT1
(W/AUDIO)
E
Q
S/P
AUDIO
DEC.
ROUNDING
AUDIO
VIDEO CHANNEL
LINK
(TX)
VCO
DRIVE
AUDIO
ENC.
HD MUTE HD SYSH
(FPGA)
EE/
THRU
VIDEO
AUDIO
EE/VV
P/S
VCO
CHANNEL
LINK
(RX)
SD
MUTE
CHARA.
ADD
SD SDI OUT1
(W/AUDIO)
BUFFER
BUFFER
AUDIO
ENC.
AUDIO
ENC.
AUDIO
ENC.
AUDIO
ENC.
AUDIO
ENC.
PB/B OUT
PR/R OUT
BUFF
BUFF
BUFF
BUFF
BUFF
BUFF
BUFF
BUFF AMP
LPF
VIDEO
DAC,
RGB
CONV.
&
CMPST
ENC.
CHANNEL
LINK
(RX)
YG
IF
LSI
HD
SD
M/S MIX
OR
M THRU
SD
TBC
ROUNDING
HD
TBC
CHANNEL
LINK
(TX)
CMPST
SDI
INT SG
REC/EE
FILTER
FILTER
FILTER
FILTE
R
AMP
AMP
AMP
AMP