Panasonic AJ-YA120AG, Service Manual

Page: 107 / 647

UDC (AJ-YA120AG) BLOCK DIAGRAM
BLK-11
P100<1>
62A UD_74M
SUB_YE(0)-(9)
P100<1>
45B-54B
P100<1>
P100<1>
P100<1>
P100<1>
P100<1>
P100<1>
P100<1>
P100<1>
P100<1>
P100<1>
P100<1>
P100<1>
UD_27M_CLK
(NOT USED)
32_PULL
66A UD_27M
70B UD_HD_CF
70A UD_SD_CF
23A-27B ADDRESS (8:0)
28A-31B DATA (7:0)
33A SYS_WE_N
33B SYS_RE_N
32A F_CONV_CS
32B SYS_RST_L
SYS_WR_N
SYS_RD_N
UPDOWN_CS_N
PW_RST_N
68B UD_HD_H
68A UD_SD_H
69B UD_HD_FRM
IN INREF FRM
69A UD_SD_FRM
IN OUTREF FRM
71B FILM_REF
IC340<3>
151 IN CLK2
34 OUT CLK2
PROCESS_CLK
INCLK1
INCLK3
INCLK2
INCLK4
OUTCLK4
OUTCLK2
IP PROC
Resister Values
Serializer
System Timing
IC205<2>
(4) (16)
IC206,207<2>
(2-9,2) (11-18,18)
(231-239)
(219-226)
(215)
158 181 546 234
(18) (2)
(M4)
D
A
T
A B (19:0)
4
ADDR B (11:0)
4
CLK
4
IN INREF H
IN INREF FRM
IN OUTREF H
IN OUTREF FRM
32 PULL
(T12)
(T13)
(R13)
(F20)
(F19)
(G20)
(G19)
(G17)
(216)
(217)
(156)
(98)
(100)
(99)
(101)
(102)
61-66
68-71
2-4
7-11
13,16
IC208<2>
(2-9) (11-18)
IC209<2>
(3) (17)
IC209<2>
(2) (18)
IC209<2>
(4) (16)
IC209<2>
(5) (15)
IC205<2>
(2) (18)
IC205<2>
(5) (15)
IC205<2>
(7) (13)
IC205<2>
(3) (17)
IC205<2>
(6) (14)
IC205<2>
IC200-IC204<2>
(8) (12)
IN_Y_EVEN
IN_PB
IC400<4>
IC401<4>
ASIC needs TRS.
Buff
UFC1000
ASIC
BGA
IC600<6>
(V5)
(L6)
(W3) (Y3) (V3) (U4)
V6,W6,Y6
V7,W7,Y7
U8,V8,W8,Y8
HALF_CLK
OUT Y_EVEN (9:0)
/ SD 4:2:2 (9:0) / Y(9:0)
Y mux for HD
FIFO timing
TRS detect
TRS add
SETUP adjust
TRS add
Y/C Mux for HD
Timing Control
(103) (104) (105)
NCE_TX
RESERVE2
RESERVE1
RESERVE0
(213)
15-19
37,39
2-13
40-53
21-26
34-39 (38)
Output Control
IC702,703<7>
IC704<7>(6-9)
IC705<7>(2-7)
IC704<7>(12-14)
IC705<7>(14-19)
IC702<7>(2-9)
IC703<7>(2,3)
IC702<7>(12-19)
IC703<7>(18,19)
11
DFF
1/2 Div.
/ throu.
9
8
10
TP343
<3>
TP345
<3>
TP344
<3>
TP347
<3>
TP346
<3>
C7,D7,E7,F7
C6,D6,E6
C5,D5,E5 (259-337)
ASIC_OUT_Y (9:0)
ASIC_CLK
P100<1>
2A-11A DWN_PB(0)-(9)
P100<1>
IC200<2>(12-19)
IC201<2>(18,19)
IC200<2>(2-9)
IC201<2>(2,3)
IC202<2>(6-9)
IC203<2>(2-7)
IC202<2>(12-15)
IC203<2>(14-19)
DFF
2B-11B DWN_YE(0)-(9)
10
TP701<7>
TP700<7>
10
10
Buff
IC700<7>
(9)
SUB_PB(0)-(9)
P100<1>
35B-44B
T14,U14,V14,W14
Y14,U15,V15,W15
Y15,U16
OUT PB (9:0) / C (9:0)
IC704,705<7>
11
DFF
TP703<7>
10
10
UD_CLK
P100<1>
57A
(V12) UD_CLK
(V20)
OUT_FRM
(Y20)
OUT_H
(U20)
OUT_CF
TP657<6>
TP659<6>
(3)
(2)
(6)
(11)
SUB_UD_CLK
SUB_OUT_FRM
(17)
(18)
(14)
SUB_OUT_FRM
P100<1>
59B
SUB_OUT_H
P100<1>
59A
SUB_OUT_CF
P100<1>
60B
IC500-503
CS(2:0) 4
RAS 4
CAS 4
WE 4
CLKEN 4
DATAEN 4
IC504-507 IC508-511 IC512-515<5>
C8,D8,E8,F8
C9,D9,E9,F9
G9,C10
(364-413)
ASIC_OUT_PB (9:0)
PB (9:0) / C (9:0)
C14,D14,E14
F14,G14,C15
D15,E15,F15
G15
(D11)
(G18)
(F18)
(442-520)
(444)
(445)
(131)
(443)
(105)
(184)
ASIC_OUT_PR (9:0)
PR (9:0)
PROGRAM_CLK
(E17)
PROGRAM_RST_N
(D17)
UFC_RST_N
(C17)
PROGRAM_DATA
(C18)
OUT_FR_RST_N
(D18) FILM_RST
(105)
OUT_FR_RST
(181)
(184)
FILM_RST
(180)
195-198
200-205
(183-262)
ASIC_Y (9:0)
/ SD 4:2:2 (9:0)
(261-339)
ASIC_C (9:0)
TP200
IN CLK1
10
10
10
10
TP365<3>
TP404
TP405
TP369<3>
TP600<6>
TP408<4>
TP409<4>
TP602
TP340
TP601 TP400<4>
IN_SD_N
IC212<2>
(2) (14)
(19)
(19)
OUT_SD_N IN_SD
OUT_SD
IN_OUTREF_CF
IN_INREF_CF
IC213<2>
(2) (17)
74_PROC
27_PROC
OUT_HD
IC214<2>
(2) (16)
IC215<2>
(2) (18)
IC211<2>
IC216<2>
IC216<2>
IC216<2>
IC217<2>
IC217<2>
(2) (18)
(9) (11)
(3) (17)
OUTCLK3
(4) (16)
(5) (15)
(9) (11)
UD_74M_CLK
IN_HD
IC210<2>
(2) (18)
Output signal does not have TRS.
SDRAM (4M 16bit) 4 SDRAM (4M 16bit) 4 SDRAM (4M 16bit) 4 SDRAM (4M 16bit) 4
P150<3>
FROM
VOUT_SYS
CIRCUIT
62A
P150<3>
P150<3>
P150<3>
P150<3>
P150<3>
P150<3>
P150<3>
P150<3>
P150<3>
P150<3>
P150<3>
P150<3>
66A
70B
70A
23A-27B
28A-31B
33A
33B
32A
32B
68B
68A
69B
69A
71B
P150<3>
2A-11A
P150<3>
2B-11B
P150<3>
45B-54B
P150<3>
35B-44B
P150<3>
57A
P150<3>
59B
P150<3>
59A
P150<3>
60B
(V3)
(W4)
(K17)
(N4)
TP705<7>
182-187
189-192
TO
VOUT_SYS
CIRCUIT