SYS CONTROL BLOCK DIAGRAM
A55
IC500<7>
EVR DSR
DSR0
DSR1
DSR2
LTCG IRQ
LTCR IRQ
ADRS[7:0]
DATA[15:0]
BLW
BHW
RD
CS IN
BCLK
OE
EXTCLK
P113 LTCIN
SCLK1
SOUT1
SIN1
SCLK2
SOUT2
SIN2
CLK18
EXTLTCGCK
P008
P009
P010
EVRCLK
EVRDATA
EVRSTB1
SCLK0
SOUT0
TIN19
CS0
BCLK
T012
A[11:30]
DB[0:15]
RD
BHE
BLE
P44
P96
TXD0
RXD0
SCLOCKI0
P62
P63
AD0IN5
T013
T014
TXD2
RXD2
CTX0
CRX0
CTX1
CRX1
MOD1
SCLK1
RXD1
TXD1
FP
MOD0
FLASH ROM
WRITING
CONNECTOR
SYS SV DATA
SV SYS DATA
SV SYS CLK
SYS SV RQ
SV REST L
TC IN
TC OUT
IF FRONT CLK
IF FRONT DATA
FRONT IF DATA
SCLK
SDATA
RF EVR CLK
RF EVR DATA
RF EVR LD
EXT LTC CLK >>
FROM VOUT
CIRCUIT<3>
THERM SENS
DEW ON H
PWR FAN NG
PSW ON H
SCE L
SDE
CHAR CLK
CHAR SIN
IC613<8>
IC601, 606<8>
IC621, 601<8>
IC602, 604<8>
BUFF
RS-422
DRIVER /
RECEIVER
BUFF
9P TXD A
9P TXD B
9P RXD A
9P RXD B
SYS CAN TX0
SYS CAN RX0
SYS CAN TX1
SYS CAN RX1
IC503<7>
IC628<8>
CLK18
PULSE
SHAPER
P114 LTCOUT
A1
PULSE
SHAPER
B1
B15
A15
A16
B72
B73
A73
B23
A23
A24
B24
132
131
6
7
8
140
141
142
144
2
3
IC605<8>
4
5
108
50
17
46
44
48
B17
A18
A17
B18
B39
A40
A39
B40
B21
B20
A20
A19
A21
35,36,37,38,39,40,41,42
14,15,20,21,22,23,24,25,
26,27,28,29,31,32,33,34
88
13
114
115
116
133
134
118
FLASH
ROM
A[17:0]
DQ[15:0]
OE
WE
CE
RY/BY
RESET
IC611<8>
IC660<8>
RESET
12
15
26
11
28
29,30,31,32,33,34,35,36,
38,39,40,41,42,43,44,45
24,23,22,21,20,19,18,17,
16,9,8,7,6,5,4,3,2,1,48,
99
142
73
19
141
140
100
139
32
62
3
4
5
6
10
98,97,96,95,94,93,92,91,90,89,
88,87,86,85,84,83,82,81,80,79
135,134,133,132,131,130,129,128,
127,126,125,124,123,122,121120
111
112
113
103
104
105
P501<7>
TIN23
P132
P131
P130
P126
P103
11
12
31
9
109
110
15
3
2
1
13
14
BUFF
BUFF
BUFF
IC617<8>
IC614<8>
IC619<8>
SW1<7>
64
65
T00
T01
108
107
106
54
53
BUFF
IC614<8>
106
107
QR502<7>
QR501<7>
QR500<7>
B19
A25
A12
A13
A3
T015
36
35
34
45
44
AD0IN6
FAN DET
33
12
BUFF
IC619<8>
129
A55
27
29
B6
A5
A6
20
19
18
B41
A47
A48
B48
B62
8
A12
A13
2
BUFF
IC619<8>
P1
18
17
16
19
A43
B42
15
16
17
14
21
P901
P1
P1
P1
P1
P1
P1
P4102
P1
P403
P1
FROM REC
PB CIRCUIT
TO/FROM
A I/O
CIRCUIT
TO RF/EQ
CIRCUIT
TO/FROM
FRONT
CIRCUIT
TO RF/EQ
CIRCUIT
P1
P901
P111
P4301
FROM RF/EQ
CIRCUIT
FROM SERVO
CIRCUIT
FROM
POWER
CIRCUIT
FROM A I/O
CIRCUIT
TO/FROM
SERVO
CIECUIT
FROM/TO
V JACK
CIRCUIT
B41
A42
FROM/TO
REC PB
CIRCUIT
TO VOUT
CIRCUIT<4>
P1
P1
P1
P1
P1
P1
P1
P1
Summary of Contents for AJ-YA120AG
Page 3: ... 3 ...
Page 4: ... 4 AJ HD1200AE ...
Page 5: ... 5 ...
Page 6: ... 6 AJ YA120AG AJ YAD120AG ...
Page 8: ... 8 AJ HD1200AP ...
Page 9: ... 9 ...
Page 10: ... 10 AJ HD1200AE ...
Page 11: ... 11 ...
Page 12: ... 12 AJ YA120AG AJ YAD120AG ...
Page 13: ...FCD0405NTKK67E494E495 ...
Page 312: ...73 73 73 73 31 95 89 MECHANICAL CHASSIS ASSEMBLY 1 MPL 1 ...
Page 314: ...MECHANICAL CHASSIS ASSEMBLY 2 MPL 3 ...
Page 316: ...58 59 57 36 59 59 E9 SUB CHASSIS ASSEMBLY MPL 5 37 55 38 39 55 55 57 55 55 ...
Page 318: ...FRONT LOADING ASSEMBLY MPL 7 E22 112 109 104 109 104 ...
Page 493: ...E1 2 1 2 3 10 4 5 6 9 1 E2 8 7 PACKING ASSEMBLY AJ YA120AG OPL 3 ...
Page 552: ...MECHANICAL CHASSIS ASSEMBLY 2 MPL 3 ...
Page 554: ...58 59 57 36 59 59 E9 SUB CHASSIS ASSEMBLY MPL 5 37 55 38 39 55 55 57 55 55 ...
Page 556: ...FRONT LOADING ASSEMBLY MPL 7 E22 112 109 104 109 104 ...
Page 634: ...E1 2 1 2 3 10 4 5 6 9 1 E2 8 7 PACKING ASSEMBLY AJ YA120AG OPL 3 ...