![background image](http://html1.mh-extra.com/html/omron/c200hw-srm21-v1-cs1w-srm21/c200hw-srm21-v1-cs1w-srm21_operation-manual_742333389.webp)
368
Checking Operations of CS-series and CJ-series Master Units
Section 6-3
The contents from the first word to the first word +9 cannot be used for any
other purpose. These words can be used, however, if the Slave registration
function and communications stop mode are not enabled.
Checking Operations
Using DM Area Words
The following table shows the functions of the words in the Master Unit’s Spe-
cial I/O Unit DM Area that are used to check operations.
First word
First word + 1
First word + 2
First word + 3
First word + 4
First word + 5
First word + 6
First word + 7
First word + 8
First word + 9
First word + 10
First word + 99
Bits
3
0
2
1
4
6
5
7
8
10
9
11
12
14 13
15
to
First word = (unit number
×
100)
Output Slave Registration Table
(Used only when Slave registration function is enabled.)
Input Slave Registration Table
(Used only when Slave registration function is enabled.)
Registered Slave Participation Monitoring Time
(Used only when Slave registration function is enabled.)
Reserved for system use. (Cannot be used.)
Status Flags
(Used when Slave registration or
communications stop mode are enabled.)
Communications Stopped Node Number and Slave Type
(Used only when communications stop mode is enabled.)
Output Slave Verification Error: Slave Missing
(Used only when Slave registration function is enabled.)
Input Slave Verification Error: Slave Missing
(Used only when Slave registration function is enabled.)
Output Slave Verification Error: Unregistered Slave in Network
(Used only when Slave registration function is enabled.)
Input Slave Verification Error: Unregistered Slave in Network
(Used only when Slave registration function is enabled.)
Not used. (Can be used as work bits/words.)
CPU Unit-to-Master Unit
(The contents of this area is
transferred to the Master Unit
from the CPU Unit when the
power is turned ON. When the
contents has changed, turn ON
the power again.)
Master Unit-to-CPU Unit