Octagon 6000 Series, User Manual

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Counter timer controller 6000 Series user’s manual
15-6
Table 15-5 Read /write bits: RW1 and RW0
RW1 RW0 Description
0 0 Counter latch command
0 1 Read and write least significant byte only
1 0 Read and write most significant byte only
1 1 Read and write least and then most significant byte
Note For additional information on the counter latch command, refer to the
Intel peripheral 82C54 data sheet or the NEC 71054 data sheet.
Counter/timer modes
There are six different modes for the counter/timers.
Table 15-6 Counter timer modes
M2 M1 M0 Description
0 0 0 Mode 0 – Terminal count
0 0 1 Mode 1 – Hardware retriggerable one shot
X 1 0 Mode 2 – Rate generator
X 1 1 Mode 3 – Square wave generator
1 0 0 Mode 4 – Software triggered strobe
1 0 1 Mode 5 – Hardware triggered strobe
Binary coded decimal (BCD) bit
The binary coded decimal enable bit is used to set the counter into BCD
or binary counter decimal modes.
Table 15-7 Binary counter modes
BCD Description
0 Binary counter 16-bits
1 Binary Coded Decimal (BCD) Counter (4 decades)
Definition of CTC modes
To begin counting, several CTC modes require the GATE to toggle.
Modes 1, 4, and 5 require control of the GATE. The GATE address is
always 0xA8, bit 4. The GATE of the 6020 counter 2 is always enabled,
therefore only Modes 0, 2, and 3 are effective for counter 2. The GATEs
for counter 0 and counter 1 are tied together and are either pulled high
or enabled by CTC Gate Enable so all modes can be used for these
counters. Since the primary purpose of the 6020 CTC design is to