Octagon 6000 Series, User Manual

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6000 Series user’s manual Counter timer controller
15-3
The following addresses each access a different function of the CTC:
n
Base+0 = CTC counter 0
n
Base+1 = CTC counter 1
n
Base+2 = CTC counter 2
n
Base+3 = CTC control register
Refer to the Counter/timers section for details on each I/O location and
their functions.
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Interrupts
The outputs of CTC counters 0 and 1 are used to provide periodic inter-
rupts to the 6020 CPU. The output of counter 0 is routed to IRQ 12,
and the output of counter 1 is routed to IRQ11.
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Counter/timers
The CTC has three separate counter/timers included in one package.
Three data registers are associated with the control register. After
powerup, the state of the 82C54 is undefined because the mode and
count value of all counters have not been defined. The operation of each
counter is determined after it is programmed. Each counter must be
programmed before it can be used. Unused counters, however, do not
need to be programmed.
Note Since the CTC mainly functions as an interrupt generating device, it is
important to disable interrupts prior to programming the CTC and then
re-enable the interrupts.
The following define each section of each counter/timer:
CTC CLOCK Any negative transition on the CLOCK input will
inputs decrement the numeric value of the count registers.
CTC GATE The GATE input, when true, allows the CLOCK
inputs signal to decrement the value of the count.
CTC outputs Depending on the mode, the OUT signal will either
toggle or pulse when the count value reaches 0.
Each of the above counter/timer counters can operate in one of six
different modes. For more information on the different modes, refer to
the Counter/timer modes section.
Programming the counter/timers
Each counter must be programmed with the desirable mode and then
with an initial count before it can be used. This is accomplished by
writing a control word and then an initial count. The control word is
written in the form of a formatted byte to the CTC control register
(Base+3).