Octagon 6000 Series, User Manual

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Counter timer controller 6000 Series user’s manual
15-2
Note The 82C54 is an extremely versatile component which has six modes of
operation, a Read Back command, and a Counter Latch command. The
primary intent, however, is to use the 6020 CTC for providing periodic
interrupts to the CPU and not to discuss all functions associated with
the CTC. For further information, refer to the Intel peripheral 82C54
data sheet or the NEC 71054 data sheet.
This section provides an overview of the 6020 CTC. A programming
example, 6020_CTC.CPP, is included on the 6020 utility disk, which
demonstrates using CTC counters 0 and 1 to generate periodic inter-
rupts.
To adequately explain the counter timer controller, the 6020 CTC is
presented in three functional sections:
n
Address mapping
n
Interrupts
n
Counter /timers
≡
Address mapping
The base address of the CTC is jumper selectable. Refer to Table 15-1
for the base address selection.
Table 15-1 CTC base address selection: 6020
IA:
W2[7-8] IB:
W2[9-10] J1: EZ I/O 1
address
J7: EZ I/O 2
address CTC I/O
address
not
jumpered
not
jumpered
320H 328H 330H
jumpered not
jumpered
120H 128H 130H
not
jumpered
jumpered 340H 348H 350h
jumpered* jumpered* 140H* 148H* 150H*
* = default, jumpers on
Note Selecting a different CTC I/O address also selects a different I/O address
for the EZ I/O digital ports. For information on EZ I/O, refer to the
EZ I/O section in the EZ I/O chapter.
It is important that no other devices in the system be set for access at
the same I/O locations as the 6020 CTC or EZ I/O ports. The CTC
mapped locations consist of four separate I/O addresses.