Octagon 6000 Series, User Manual

Page: 120 / 233

6000 Series user’s manual Counter timer controller
15-1
Chapter 15:
Counter timer controller
Note The counter timer controller is only available on the 6020 PC
Microcontroller.
≡
Description
The 6020 has an 82C54 counter timer controller (CTC) to provide peri-
odic interrupts to the CPU for time related I/O events such as data
logging. Two time bases are available: 1.8 MHz and 7.2 MHz. These
time bases are jumper selectable through W2. Refer to Table 15-1.
The CTC chip consists of three counter/timer circuits. Counter 2, which
has either a clock input of 1.843 MHz or 7.159 MHz, acts as a pre-scalar
for counters 0 and 1. The output of counter 2 is routed to the clock
inputs of both counters 0 and 1. Gate inputs to counters 0 and 1 are
tied together and are either pulled high or controlled by the control
signal, CTC Gate Enable. The outputs of counters 0 and 1 then provide
IRQ12 and IRQ11, respectively, to the CPU.
Figure 15-1 Counter timer controller diagram
OUT 0
CLK 0
GATE 0
OUT 1
CLK 1
GATE 1
OUT 2
CLK 2
GATE 2
82C54
1.843 MHz
7.159 MHz
CTC Gate Enable
+5V
10K
IRQ12
IRQ11
1
3
5
7
9 2
4
6
8
10
+5V
10K
NC
+5V
IA
B
W2