NXP Semiconductors Lite5200B User Manual Download Page 47

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Erasing Flash

LITE5200B User’s Manual, Rev. 0

Freescale Semiconductor

5-13

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Summary of Contents for Lite5200B

Page 1: ...Lite5200B User s Manual Devices Supported MPC5200B LITE5200BUM Rev 0 10 2005...

Page 2: ...r sustain life or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur Should Buyer purchase or use F...

Page 3: ...3 Power Connections 4 2 4 3 1 DC Power Jack J35 4 2 4 3 2 ATX Power Connector J36 4 2 4 3 3 Banana Jacks J32 J28 J27 J26 J25 4 2 4 3 4 PCI 12 Volt Supply Jacks J5 J8 4 3 4 4 Memory Configuration 4 3 4...

Page 4: ...Low Power Mode 4 17 Chapter 5 Boot Monitor 5 1 Basic Configuration 5 1 5 2 Memory Map 5 1 5 3 Accessing Memory Using U Boot 5 2 5 3 1 MD 5 2 5 3 2 MW 5 3 5 4 Environmental Variables 5 3 5 4 1 printen...

Page 5: ...BDINFO 7 4 7 4 BootD 7 5 7 5 BootM 7 6 7 6 BootP 7 7 7 7 CMP 7 8 7 8 CONINFO 7 9 7 9 CP 7 10 7 10 CRC32 7 11 7 11 DHCP 7 12 7 12 DISKBOOT 7 13 7 13 ECHO 7 14 7 14 EEPROM 7 15 7 15 ERASE 7 16 7 16 FATI...

Page 6: ...40 7 36 MM 7 41 7 37 MTEST 7 43 7 38 MW 7 44 7 39 NFS 7 45 7 40 NM 7 46 7 41 PING 7 47 7 42 PCI 7 48 7 43 PRINTENV 7 49 7 44 PROTECT 7 51 7 45 RARPBOOT 7 54 7 46 REG INFO 7 55 7 47 RESET 7 56 7 48 RUN...

Page 7: ...tandard Slots CAN 2 DB9 Connectors ATA UDMA4 PowerPC Debug connection COP JTAG AT Power Supply connection Molex Ultra Low Power Mode Circuit Boot Flash Recovery Capability Power Bypass Capability Boar...

Page 8: ...Introduction LITE5200B User s Manual Rev 0 1 2 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK...

Page 9: ...s are included in the MPC5200B development kit MPC5200B Hardrware User Document CD Lite5200B Users Manual Lite5200B Schematic U Boot Command Reference 5v DC Power Supply 9 Pin serial Cable U Boot Apll...

Page 10: ...Development Kit Contents LITE5200B User s Manual Rev 0 2 2 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK...

Page 11: ...to the wall outlet 4 Connect the 5V power supply cable to the J35 Power Connector on the board 5 Start a terminal application such as HyperTerminal on your PC and set the serial settings to Select Com...

Page 12: ...Getting Started LITE5200B User s Manual Rev 0 3 2 Freescale Semiconductor Figure 3 1 Quick Start Connectors...

Page 13: ...2005 16 46 38 CPU MPC5200 v2 1 at 462 MHz Bus 132 MHz IPB 132 MHz PCI 33 MHz Board Freescale MPC5200 Lite5200B I2C 85 kHz ready DRAM 256 MB FLASH 32 MB Warning bad CRC using default environment PCI Bu...

Page 14: ...Getting Started LITE5200B User s Manual Rev 0 3 4 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK...

Page 15: ...ipheral Connection Table 4 1 Pin Configuration Functional MPC5200B Pin Group s ATA ATA EXT_AD 18 0 CAN1 I2 C CAN2 TIMER 1 0 DRAM SDRAM EEPROM I2C J31 I2C J29 I2C 1 Ethernet ETH 17 0 Flash1 LP_CS 1 0 E...

Page 16: ...ial of the shelf power ATX supply Note The connector on the board has pin 1 labeled as pin 4 Please notice that pin 1 on the board has the square pad and is nearest SW4 Ignore the pin label on the con...

Page 17: ...ory 4 4 1 1 Main Flash The Lite5200B is provided with 32 Megabytes of 8 bit flash in a non muxed configuration The memory uses 2 flash devices connected to CS0 CS1 These devices are U12 and U16 with C...

Page 18: ...s hardware configuration allows the board to boot from the back up flash which contains an image of the original boot loader which is then copied to DRAM for later programming into main flash 4 4 2 DR...

Page 19: ..._DD7 4 DD8 ATA_5V_DD8 5 DD6 ATA_5V_DD6 6 DD9 ATA_5V_DD9 7 DD5 ATA_5V_DD5 8 DD10 ATA_5V_DD10 9 DD4 ATA_5V_DD4 10 DD11 ATA_5V_DD11 11 DD3 ATA_5V_DD3 12 DD12 ATA_5V_DD12 13 DD2 ATA_5V_DD2 14 DD13 ATA_5V_...

Page 20: ...JTAG connector 4 5 4 Ethernet J6 An 18 wire 10 100 Base T ethernet connection is provided to the MPC5200B The ethernet port is decoupled through a physical layer ethernet transceiver for a network re...

Page 21: ...C5200 and the ethernet transceiver and cannot be disconnected In this configuration these pins may be accessible through a general purpose header 4 5 4 2 Ethernet JTAG J15 A header is provided on the...

Page 22: ...lopment purposes The LEDs are driven by an inverting buffers connected to the MCU pins described in the following table 4 5 7 General Purpose Headers J16 J17 J18 J19 J20 J21 J22 J23 These headers are...

Page 23: ...MER_2 function to work on pin 2 of J17 Table 4 14 Ethernet Port Header J16 Pin MPC5200B Signal Pin MPC5200B Signal 1 ETH_TXD 2 2 ETH_CRS 3 ETH_TXD 3 4 ETH_TXEN 5 ETH_TXERR 6 ETH_TXD 0 7 ETH_MDC 8 ETH_...

Page 24: ...5 20 GND Table 4 17 Data CS Header J19 PIN NAME PIN NAME 1 D6 2 GND 3 D7 4 GND 5 CS_2 6 GND 7 CS_3 8 GND 9 RWB_CFG_3 10 GND 11 ALE_CFG_4 12 GND 13 TS_CFG_5 14 GND 15 ACK 16 GND 17 CS_1 18 GND 19 GND 2...

Page 25: ..._CHIP 13 PSC3_6 14 NO CONNECT 15 PSC3_7 16 3 3 V 17 PSC3_8 18 GND 19 PSC3_9 20 GND Table 4 20 Address Header J22 PIN NAME PIN NAME 1 A10 2 GND 3 A11 4 GND 5 A12 6 GND 7 A13 8 GND 9 A14 10 GND 11 A15 1...

Page 26: ...J14 PIN PIN NAME PIN PIN NAME A1 TRST B1 12V A2 12 B2 TCK A3 TMS B3 GND0 A4 TDI B4 TDO A5 5 B5 5V_1 A6 INTA B6 5V_2 A7 INTC B7 INTB A8 5V_5 B8 INTD A9 RESERVED3 B9 PRSNT1 A10 3 3V I O B10 RESERVED1 A1...

Page 27: ...5 GND12 B35 IRDY A36 TRDY B36 3 3V_3 A37 GND13 B37 DEVSEL A38 STOP B38 GND4 A39 3 3V I O 10 B39 LOCK A40 RESERVED 5 B40 PERR A41 RESERVED 6 B41 3 3V_4 A42 GND14 B42 SERR A43 PAR B43 3 3V_5 A44 AD15 B4...

Page 28: ...MPC5200B through a transceiver IC Note The case of connector J3 is grounded through an inductor 4 5 10 USB J4 A USB interface is provided on J4 which allows connection of a USB device to the MPC5200B...

Page 29: ...alling a shorting jumper on header J12 The USB pins of the 5200 are available on J17 as described in Section 4 5 7 General Purpose Headers J16 J17 J18 J19 J20 J21 J22 J23 on page 4 8 4 6 Switches Figu...

Page 30: ...Boot Configuration SW1 Figure 4 4 Boot Configuration SW1 XLB CLK SEL SYS PLL CFG 2X FVCO MOST GRAPHICS LARGE FLASH BOOT HIGH WAITSTATES BYTE LANE SWAP WIDE BOOT DATA LANE MUXED BOOT PORCFG 26 PORCFG 2...

Page 31: ...ot enabled Bit 1 Most Graphics boot enabled LARGE FLASHA Bit 0 Large Flash boot not enabled Bit 1 Large Flash boot enabled BOOT HIGH Reset Vector is Bit 0 0x00000100 hex Bit 1 0xFFF00100 hex WAITSTATE...

Page 32: ...control circuit causing low power mode to be entered 3 a pushbutton in the control circuitry to cause return to normal power mode 4 a signal from the control circuit to the MPC5200B indicating when p...

Page 33: ...the pushbutton is released Following the low pulse the QT1 drives the PWR_DN_CTL_STS net high through R208 The MPC5200B port PSC2_4 may be configured as an edge sensitive interrupt with an optional wa...

Page 34: ...onfigure port PSC2_4 as an input with interrupt sense capability so that it can detect any future external power down requests The QT1 will continue to drive the net high through R208 until an externa...

Page 35: ...USB For a complete list of u boot commands see Appendix TBD or alternately the U Boot web site 5 1 Basic Configuration The basic monitor configuration delivered with the Lite5200B is configured with t...

Page 36: ...ax for this command is md b w l address example md 0xF0000000 f0000000 0000f000 0000ff00 0000ffff 0000fe00 f0000010 0000feff 0000ffff 0000ffff 0000ffff md l 0xF0000000 f0000000 0000f000 0000ff00 0000f...

Page 37: ...nfiguration and commands for later usage after power removed or reset occurs 5 4 1 printenv The printenv command may be used to print the currently configured environment variables Unless specifically...

Page 38: ...5 4 2 setenv The setenv command may be used to set an environmental variable in ram Please note that if power is lost currently configured variables in ram will not be saved unless the environment has...

Page 39: ...following environmental variables must be configured for operation To set a static IP the environmental variables in Table 2 must be specified through the command line interface 5 5 2 2 DHCP The Lite...

Page 40: ...tion Value1 1 Values for ethaddr netdev autoload should be set by the user ipaddr local IP address for the Lite5200B Configured by DHCP e g 192 168 1 1 serverip TFTP NFS server address This value Must...

Page 41: ...red in the environmental variable setenv Code will be downloaded to the load address specified at load address The value for load address must conform to a read writable ram location serverip must be...

Page 42: ...srecord ascii formated images Usage loadb address baud ThiswilldownloadabinaryfileovertheUARTusingtheKermitprotocol Specifyingtheaddressandbaudrateareoptional however specifying the addresstobe loade...

Page 43: ...sh region Instructions for erasing a flash region can be found in Section 5 8 Writing an Image to Flash on page 5 9 Usage cp b w l sourcetargetcount This will copy a region of memory from the source t...

Page 44: ...200000 FF210000 FF220000 FF230000 FF240000 FF250000 FF260000 FF270000 FF280000 FF290000 FF2A0000 FF2B0000 FF2C0000 FF2D0000 FF2E0000 FF2F0000 FF300000 FF310000 FF320000 FF330000 FF340000 FF350000 FF36...

Page 45: ...FFB70000 FFB80000 FFB90000 FFBA0000 FFBB0000 FFBC0000 FFBD0000 FFBE0000 FFBF0000 FFC00000 FFC10000 FFC20000 FFC30000 FFC40000 FFC50000 FFC60000 FFC70000 FFC80000 FFC90000 FFCA0000 FFCB0000 FFCC0000 FF...

Page 46: ...FE460000 FE470000 FE480000 FE490000 FE4A0000 FE4B0000 FE4C0000 FE4D0000 FE4E0000 FE4F0000 FE500000 FE510000 FE520000 FE530000 FE540000 FE550000 FE560000 FE570000 FE580000 FE590000 FE5A0000 FE5B0000 F...

Page 47: ...30000 FEC40000 FEC50000 FEC60000 FEC70000 FEC80000 FEC90000 FECA0000 FECB0000 FECC0000 FECD0000 FECE0000 FECF0000 FED00000 FED10000 FED20000 FED30000 FED40000 FED50000 FED60000 FED70000 FED80000 FED90...

Page 48: ...Boot Monitor LITE5200B User s Manual Rev 0 5 14 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK...

Page 49: ...ot This version of U Boot will erase 0xFFF00000 to 0xFFFFFFFF After this is completed the factory version of U Boot will be restored to the main flash and the device will reboot After restoration is c...

Page 50: ...Flash Recovery LITE5200B User s Manual Rev 0 6 2 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK...

Page 51: ...his image For example consider the following text file echo echo Network Configuration echo echo Target printenv ipaddr hostname echo echo Server printenv serverip rootpath echo Convert the text file...

Page 52: ...our IP address is 10 0 0 99 Filename tftpboot TQM860L example img Load address 0x100000 Loading done Bytes transferred 221 dd hex autoscr 100000 Executing script at 00100000 Network Configuration Targ...

Page 53: ...wever when you repeatedly have to access a certain memory region like the internal memory of some embedded PowerPC processors it can be very convenient to set the base address to the start of this are...

Page 54: ...memory addresses and sizes clock frequencies MAC address etc This type of information is generally passed to the Linux kernel bdi memstart 0x00000000 memsize 0x04000000 flashstart 0x40000000 flashsiz...

Page 55: ...reescale Semiconductor 7 5 7 4 BootD bootd Boot default i e run BOOTCMD The bootd short boot executes the default boot command i e what happens when you don t interrupt the initial countdown This is a...

Page 56: ...t can be passed If it is present it is interpreted as the start address of a initrd ramdisk image in RAM ROM or flash memory In this case the bootm command consists of three steps first the Linux kern...

Page 57: ...BootP LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 7 7 6 BootP bootp Boot image via network using BootP TFTP PROTOCOL bootp loadAddress bootfilename...

Page 58: ...203230 3032202d 5 Mar 21 2002 00100020 2031393a 35353a30 34290000 00000000 19 55 04 40000000 27051956 50504342 6f6f7420 312e312e VPPCBoot 1 1 40000010 3520284d 61722032 31203230 3032202d 5 Mar 21 2002...

Page 59: ...I O devices conin List of available devices serial 80000003 SIO stdin stdout stderr The output contains the device name flags and the current usage For example the output serial 80000003 SIO stdin std...

Page 60: ...e memory element to another memory element The source can be RAM ROM FLASH EPROM or any other type of memory The destination or target memory is usually RAM however the target memory can also be FLASH...

Page 61: ...can be used to caculate a CRC32 checksum over a range of memory crc 100004 3FC CRC32 for 00100004 001003ff d433b05b When used with 3 arguments the command stores the calculated checksum at the given a...

Page 62: ...U Boot Commands LITE5200B User s Manual Rev 0 7 12 Freescale Semiconductor 7 11 DHCP dhcp Invoke DHCP client to obtain IP boot params...

Page 63: ...DISKBOOT LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 13 7 12 DISKBOOT diskboot Boot from IDE device diskboot loadAddr dev part...

Page 64: ...v 0 7 14 Freescale Semiconductor 7 13 ECHO echo args Echo args to console c suppresses newline The echo command echoes the arguments to the console echo The quick brown fox jumped over the lazy dog Th...

Page 65: ...EEPROM LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 15 7 14 EEPROM eeprom EEPROM subsystem eeprom read addr off cnt eeprom write addr off cnt Read write cnt bytes at EEPROM offset off...

Page 66: ...r start to addr end erase N SF SL Erase sectors SF SL in FLASH bank N erase bank N Erase FLASH bank N erase all Erase all FLASH banks Erase MON8xx Firmware The MON8xx Firmware is write protected We un...

Page 67: ...FATINFO LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 17 7 16 FATINFO fatinfo interface dev part Print information about filesystem from dev on interface...

Page 68: ...Manual Rev 0 7 18 Freescale Semiconductor 7 17 FATLOAD fatload Load binary file from a dos filesystem fatload interface dev part addr filename bytes Load binary file filename from dev on interface to...

Page 69: ...FATLS LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 19 7 18 FATLS fatls List files in a directory dafault fatls interface dev part directory...

Page 70: ...0A0000 400C0000 400E0000 40100000 40120000 40140000 40160000 40180000 401A0000 401C0000 401E0000 40200000 40220000 40240000 40260000 40280000 402A0000 402C0000 402E0000 40300000 40320000 40340000 4036...

Page 71: ...ing system to run Instead they can be loaded and executed by U Boot directly utilizing U Boot s service functions like console I O or malloc and free This can be used to dynamically load and run speci...

Page 72: ...for a particular configuration of U Boot help command show help information for command The help command short h or prints online help Without any arguments the help command prints a list of all U Boo...

Page 73: ...CRC32 LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 23 7 22 CRC32 crc32 Checksum calculation icrc32 chip address 0 1 2 count Compute CRC32 checksum...

Page 74: ...system ide reset Reset IDE controller ide info Show available IDE devices ide device dev Show or set current device ide part dev Print partition table of one or all IDE devices ide read addr blk cnt...

Page 75: ...ILOOP LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 25 7 24 ILOOP iloop Infinite loop on address range iloop chip address 0 1 2 of objects Loop reading a set of addresses...

Page 76: ...U Boot Commands LITE5200B User s Manual Rev 0 7 26 Freescale Semiconductor 7 25 IMD imd chip address 0 1 2 of objects i2c memory display...

Page 77: ...the header information for images like Linux kernels or ramdisks It prints among other information the image name type and size and verifies that the CRC32 checksums stored within the image are OK imi...

Page 78: ...U Boot Commands LITE5200B User s Manual Rev 0 7 28 Freescale Semiconductor 7 27 IMLS imls List all images found in flash Prints information about all images found at sector boundaries in flash...

Page 79: ...IMM LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 29 7 28 IMM imm i2c memory modify auto incrementing...

Page 80: ...U Boot Commands LITE5200B User s Manual Rev 0 7 30 Freescale Semiconductor 7 29 IMW imw Memory write fill...

Page 81: ...INM LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 31 7 30 INM inm Memory modify constant address iprobe probe to discover valid I2C chip addresses...

Page 82: ...U Boot Commands LITE5200B User s Manual Rev 0 7 32 Freescale Semiconductor 7 31 ITEST itest Return true false on integer compare...

Page 83: ...kermit download Ctrl c Back at denx denx de C Kermit 7 0 197 8 Feb 2000 for Linux Copyright C 1985 2000 Trustees of Columbia University in the City of New York Type or HELP for help Kermit send bin tf...

Page 84: ...U Boot Commands LITE5200B User s Manual Rev 0 7 34 Freescale Semiconductor 7 33 LOADS loads Load S Record file over serial line loads off Load S Record file over serial line with offset off...

Page 85: ...ess number_of_objects loop on a set of addresses The loop command reads in a tight loop from a range of memory This is intended as a special form of a memory test since this command tries to read the...

Page 86: ...35 MD md b w l address of objects Memory display md 100000 10 00100000 48616c6c 6f202020 01234567 312e312e Hallo Eg1 1 00100010 3520284d 61722032 31203230 3032202d 5 Mar 21 2002 00100020 2031393a 3535...

Page 87: ...27051956 0 00100004 50504342 AABBCCDD 00100008 6f6f7420 01234567 0010000c 312e312e md 100000 10 00100000 00000000 aabbccdd 01234567 312e312e Eg1 1 00100010 3520284d 61722032 31203230 3032202d 5 Mar 2...

Page 88: ...U Boot Commands LITE5200B User s Manual Rev 0 7 38 Freescale Semiconductor 00100004 43 6f 00100005 21 20 00100006 87 20 00100007 65 20 00100008 01...

Page 89: ...ting 00100000 00200000 Pattern 0000000F Writing Reading This tests writes to memory thus modifying the memory contents It will fail when applied to ROM or flash memory This command may crash the syste...

Page 90: ...0000010 00000011 00000012 00100010 00000013 00000014 00000015 00000016 00100020 00000017 00000018 00000019 0000001a 00100030 0000001b 0000001c 0000001d 0000001e mw 100000 0 6 md 100000 10 00100000 000...

Page 91: ...NFS LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 41 7 39 NFS nfs Boot image via network using NFS protocol...

Page 92: ...incrementing memory modify can be used to interactively write different data several times to the same address This can be useful for instance to access and modify device registers nm b 100000 001000...

Page 93: ...m to elicit an ICMP ECHO_RESPONSE from a host or gateway ECHO_REQUEST datagrams pings have an IP and ICMP header followed by a struct timeval and then an arbitrary number of pad bytes used to fill out...

Page 94: ...U Boot Commands LITE5200B User s Manual Rev 0 7 44 Freescale Semiconductor 7 42 PCI pci List and access PCI Configuraton Space...

Page 95: ...or the environment printenv baudrate 115200 serial TQM860LDDBA3 P50 203 10226122 4 ethaddr 00 D0 93 00 28 81 bootdelay 5 loads_echo 1 clocks_in_mhz 1 load tftp 100000 tftpboot ppcboot bin update prote...

Page 96: ...Commands LITE5200B User s Manual Rev 0 7 46 Freescale Semiconductor stdin serial stderr serial stdout serial filesize dd netmask 255 0 0 0 ipaddr 10 0 0 99 serverip 10 0 0 2 Environment size 992 16380...

Page 97: ...ed with the erase command Protected areas are marked as RO for read only in the output of the flinfo command fli Bank 1 FUJITSU AM29LV160B 16 Mbit bottom boot sect Size 4 MB in 35 Sectors Sector Start...

Page 98: ...0408000 4040C000 40410000 40420000 40440000 40460000 40480000 404A0000 404C0000 404E0000 40500000 40520000 40540000 40560000 40580000 405A0000 405C0000 405E0000 40600000 40620000 40640000 40660000 406...

Page 99: ...era 1 11 Erase Flash Sectors 11 11 in Bank 1 done The actual level of protection depends on the flash chips used on your hardware and on the implementation of the flash device driver for this board In...

Page 100: ...U Boot Commands LITE5200B User s Manual Rev 0 7 50 Freescale Semiconductor 7 45 RARPBOOT rarpboot Boot image via network using RARP TFTP protocol rarpboot loadAddress bootfilename...

Page 101: ...le reginfo MPC5200 registers MBAR f0000000 Memory map registers CS0 start 0000FF00 stop 0000FFFF config 00047800 en 0 CS1 start 0000FE00 stop 0000FEFF config 00047800 en 1 CS2 start 0000FFFF stop 0000...

Page 102: ...58 40 Initializing CPU XPC860xxZPnnD3 at 50 MHz 4 kB I Cache 4 kB D Cache FEC present Board No HW ID assuming TQM8xxL DRAM 16 MB FLASH 4 MB PCMCIA No Card found In serial Out serial Err serial Hit an...

Page 103: ...in which case these commands will be executed in sequence setenv test2 echo This is another Test printenv serial echo Done printenv test test2 test echo This is a test printenv ipaddr echo Done test2...

Page 104: ...de in RAM only They are lost as soon as you reboot the system If you want to make your changes permanent you have to use the saveenv command to write a copy of the environment settings to persistent s...

Page 105: ...ew variables will be automatically created existing ones overwritten printenv bar Error bar not defined setenv bar This is a new example printenv bar bar This is a new example Remember standard shell...

Page 106: ...be no error message which lets you believe everything went OK but it didn t instead of setting the variable name to the value value you tried to delete a variable with the name name value This is prob...

Page 107: ...SLEEP sleep Delay execution for some time sleep N Delay execution for N seconds N is _decimal_ The sleep command pauses execution for the number of seconds given as the argument date sleep 5 date Date...

Page 108: ...U Boot Commands LITE5200B User s Manual Rev 0 7 58 Freescale Semiconductor 7 52 TFTPBoot tftpboot Boot image via network using TFTP protocol tftpboot loadAddress bootfilename...

Page 109: ...USB LITE5200B User s Manual Rev 0 Freescale Semiconductor 7 59 7 53 USB usb USB sub system...

Page 110: ...U Boot Commands LITE5200B User s Manual Rev 0 7 60 Freescale Semiconductor 7 54 USBBoot usbboot Boot from USB device...

Page 111: ...Freescale Semiconductor 7 61 7 55 VERSION version Print monitor version You can print the version and build date of the U Boot image running on your system using the version command short vers versio...

Page 112: ...U Boot Commands LITE5200B User s Manual Rev 0 7 62 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK...

Page 113: ...80000300 0x00047800 CS0 and CSboot ctrl init boot flash for programming WM32 0x8000000C 0x0000FE00 CS1 start 0xFE000000 WM32 0x80000010 0x0000FEFF CS1 stop 0xFEFF0000 WM32 0x80000304 0x00047800 CS1 ct...

Page 114: ...WM32 0x8000010C 0x45770000 SDRAM Config 2 WM32 0x80000104 0xF14F0F00 SDRAM Control Mode register write enablemode reg 0 clk enable 1 DDR mode auto refresh enabled hi_addr set use A10 for precharge dr...

Page 115: ...ay after power up detected in ms BOOTADDR 0xFFF00100 Boot High STARTUP RESET startup mode reset HOST IP 10 81 111 105 LOAD MANUAL load code MANUAL or AUTO after reset FLASH CHIPTYPE MIRRORX8 Flash typ...

Page 116: ...nual Rev 0 A 4 Freescale Semiconductor ERASE 0xFFF50000 erase sector of flash ERASE 0xFFF60000 erase sector of flash ERASE 0xFFF70000 erase sector of flash ERASE 0xFFF80000 erase sector of flash WORKS...

Page 117: ...ring the I O power supply accordingly on the card A problem arises in that some PCI cards use the Universal PCI card form factor when in fact these cards only support 5 volt I O That is pins A16 A59 B...

Page 118: ...PCI Compatibility LITE5200B User s Manual Rev 0 B 2 Freescale Semiconductor THIS PAGE INTENTIONALLY LEFT BLANK...

Page 119: ...le block address translations on chip Beat A single state on the 603e bus interface that may extend across multiple bus cycles A 603e transaction can be composed of multiple address or data beats Bias...

Page 120: ...s the bus state transitions Bus master The owner of the address or data bus the device that initiates or requests the transaction C Cache High speed memory containing recently accessed data or instruc...

Page 121: ...lue usually the format s minimum and whose explicit or implicit leading significand bit is zero Direct mapped cache A cache in which each main memory address can appear in only one location within the...

Page 122: ...d Fetch Retrieving instructions from either the cache or main memory and placing them into the instruction queue Floating point register FPR Any of the 32 registers in the floating point register file...

Page 123: ...the precise exception model see Precise exception The PowerPC architecture allows only floating point exceptions to be handled imprecisely Instruction queue A holding place for instructions fetched f...

Page 124: ...s translation mechanisms provided by the MMU and that occur externally with the bus protocol defined for memory Memory coherency An aspect of caching in which it is ensured that an accurate view of me...

Page 125: ...ream Overflow An condition that occurs during arithmetic operations when the result cannot be stored accurately in the destination register s For example if two 32 bit numbers are multiplied the resul...

Page 126: ...page a BAT area or a range of unmapped effective addresses It is defined only when the appropriate relocate bit in the MSR IR or DR is 1 Q Quiesce To come to rest The processor is said to quiesce when...

Page 127: ...ffer between the dispatch and execute stages that allows instructions to be dispatched even though the results of instructions on which the dispatched instruction may depend are not available RISC red...

Page 128: ...to occur independently Stage The term stage is used in two different senses depending on whether the pipeline is being discussed as a physical entity or a sequence of events In the latter case a stage...

Page 129: ...and one or more data tenures which may overlap or occur separately from the address tenure A transaction may be minimally comprised of an address tenure only Transfer termination Signal that refers to...

Page 130: ...used in the translation of an effective address to a physical address Virtual memory The address space created using the memory management facilities of the processor Program access to virtual memory...

Page 131: ...3 8 7 bus parking 8 10 Address calculation branch instructions 2 36 effective address 2 20 floating point load and store 2 34 integer load and store 2 30 Address translation see Memory management uni...

Page 132: ...ons 3 4 overview 1 13 3 1 response to bus transactions 3 19 Cache unit memory performance 6 22 operation of the cache 8 2 overview 3 1 Cache inhibited accesses I bit cache interactions 3 10 I bit sett...

Page 133: ...10 reset 4 17 returning from an exception handler 4 14 summary 2 21 system call 4 28 system management interrupt 4 33 trace exception 4 29 Execution synchronization 2 21 Execution units 1 9 External...

Page 134: ...d shift 2 25 A 17 store 2 31 A 20 latency summary 6 26 load and store address generation floating point 2 34 address generation integer 2 30 byte reverse instructions 2 32 A 20 integer load 2 30 integ...

Page 135: ...overview 1 11 1 31 page address translation 5 8 5 11 5 27 page history status 5 11 5 21 5 24 page table search operation 5 27 segment model 5 20 software table search operation 5 31 5 36 5 37 Memory...

Page 136: ...ection 5 12 options available 5 10 protection violations 5 14 PTEGs PTE groups 5 27 PTEs page table entries 5 27 Q QACK signal 7 26 8 37 8 40 QREQ signal 7 26 8 41 Qualified bus grant 8 7 Qualified da...

Page 137: ...7 20 DPn 7 19 DRTRY 7 22 8 24 8 27 GBL 7 14 HRESET 7 25 INT 7 23 8 40 MCP 7 24 PLL_CFGn 7 30 QACK 7 26 8 37 8 40 QREQ 7 26 8 41 reset 8 40 RSRV 7 27 8 41 SMI 4 33 7 23 SRESET 7 25 8 40 TA 7 21 TBEN 7...

Page 138: ...lays 8 34 use of TEA 8 36 using DBWO 8 42 Timing instruction BPU execution timing 6 17 branch timing example 6 20 cache arbitration 6 10 cache hit 6 10 6 12 6 14 FPU execution timing 6 21 instruction...

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