LITE5200B User’s Manual, Rev. 2
Freescale Semiconductor
Index-1
Numerics
603e
features
hardware, 1-6
list of features, 1-3
PID7v-specific, 1-4
instructions, 2-46
overview, 1-1, 1-16
PID7v
features, 1-4
HID0 bits (PID7v-specific), 3-22
processor identification (PID) number
definition, 1-1
603-specific features, 1-6
A
AACK signal, 7-15
ABB signal, 7-4, 8-7
ABE (address broadcast enable) bit, 3-22
Address bus
address tenure, 8-6
address transfer
A
n
, 7-6
APE, 7-8, 8-12
AP
n
, 7-7
address transfer attribute
CI, 7-13
CSE
n
, 7-14
GBL, 7-14
TBST, 7-12, 8-13
TC
n
, 7-13, 8-19
TSIZ
n
, 7-12, 8-13
TT
n
, 7-8, 8-12
WT, 7-14
address transfer start
TS, 7-5, 8-11
XATS (603-specific), 1-6
address transfer termination
AACK, 7-15
ARTRY, 3-20, 7-15
terminating address transfer, 8-19
arbitration signals, 7-2, 8-7
bus arbitration
ABB, 7-4, 8-7
BG, 7-4, 8-7
BR, 7-3, 8-7
bus parking, 8-10
Address calculation
branch instructions, 2-36
effective address, 2-20
floating-point load and store, 2-34
integer load and store, 2-30
Address translation,
see
Memory management unit
Addressing conventions
addressing modes, 2-19
alignment, 2-14
Aligned data transfer, 2-14, 8-14, 8-18
Alignment
data transfers, 2-14, 8-14
exception, 4-24, 5-15
rules, 2-14
A
n
signals, 7-6
APE signal, 7-8, 8-12
AP
n
signals, 7-7
Arbitration, system bus, 8-9, 8-21
ARTRY signal, 3-20, 7-15
Atomic memory references
stwcx.
, 2-38
using
lwarx
/
stwcx.
, 3-19
B
BG signal, 7-4, 8-7
Block address translation
block address translation flow, 5-11
selection of block address translation, 5-9
Boundedly undefined, definition, 2-17
BR signal, 7-3, 8-7
Branch folding, 6-17
Branch instructions
address calculation, 2-36
branch instructions, 2-36, A-22
condition register logical, 2-37, A-22
system linkage, 2-43, A-22
trap, 2-37, A-22
Branch prediction, 6-1, 6-18
Branch processing unit
branch instruction timing, 6-20
execution timing, 6-17
Index