LITE5200B User’s Manual, Rev. 2
Glossary-8
Freescale Semiconductor
Park.
The act of allowing a bus master to maintain bus mastership without having to
arbitrate.
Physical memory.
The actual memory that can be accessed through the system’s memory
bus.
Pipelining.
A technique that breaks operations, such as instruction processing or bus
transactions, into smaller distinct stages or tenures (respectively) so that a
subsequent operation can begin before the previous one has completed.
Precise exceptions.
A category of exception for which the pipeline can be stopped so
instructions that preceded the faulting instruction can complete and subsequent
instructions can be flushed and redispatched after exception handling has
completed. See
Imprecise
exceptions
.
Primary opcode.
The most-significant 6 bits (bits 0–5) of the instruction encoding that
identifies the type of instruction.
Program order.
The order of instructions in an executing program. More specifically, this
term is used to refer to the original order in which program instructions are fetched
into the instruction queue from the cache.
Protection boundary.
A boundary between
protection domains
.
Protection domain.
A protection domain is a segment, a virtual page, a BAT area, or a
range of unmapped effective addresses. It is defined only when the appropriate
relocate bit in the MSR (IR or DR) is 1.
Q
Quiesce.
To come to rest. The processor is said to quiesce when an exception is taken or a
sync
instruction is executed. The instruction stream is stopped at the decode stage
and executing instructions are allowed to complete to create a controlled context
for instructions that may be affected by out-of-order, parallel execution. See
Context
synchronization
.
Quiet NaN.
A type of
NaN
that can propagate through most arithmetic operations without
signaling exceptions. A quiet NaN is used to represent the results of certain invalid
operations, such as invalid arithmetic operations on infinities or on NaNs, when
invalid. See
Signaling
NaN
.
R
rA.
The
r
A instruction field is used to specify a GPR to be used as a source or destination.
rB.
The
r
B instruction field is used to specify a GPR to be used as a source.
rD.
The
r
D instruction field is used to specify a GPR to be used as a destination.
rS.
The
r
S instruction field is used to specify a GPR to be used as a source.
Real address mode.
An MMU mode when no address translation is performed and the
effective address
specified is the same as the physical address. The processor’s
MMU is operating in real address mode if its ability to perform address translation
has been disabled through the MSR registers IR and/or DR bits.