LITE5200B User’s Manual, Rev. 2
Index-4
Freescale Semiconductor
HRESET signal, 7-25
I
IEEE 1149.1-compliant interface, 8-42
IFEM (instruction fetch enable) bit, 1-19
Illegal instruction class, 2-18
ILOCK control bit, 3-4
Instruction address breakpoint exception, 4-31
Instruction cache
cache control bits, 3-4
cache fill operations, 3-4
configuration, 3-1
organization, 3-3
Instruction timing
examples
cache hit, 6-12, 6-14
execution unit, 6-17
instruction flow, 6-8
memory performance considerations, 6-22
overview, 1-32, 6-3
terminology, 6-1
Instruction TLB miss exception, 4-30
Instruction unit, 1-8
Instructions
603e, instructions not implemented, B-1
603e-specific instructions, 2-46
branch address calculation, 2-36
branch instructions, 2-36, A-22
cache management
instructions, 2-41, 2-44, 3-22, A-23
classes, 2-17
condition register logical, 2-37, A-22
defined instructions, 2-17
external control, 2-42, A-24
floating-point
arithmetic, 2-26, A-18
compare, 2-28, A-19
FP load instructions, 2-34, A-21
FP move instructions, 2-29, A-22
FP status and control register, 2-28
FP store instructions, 2-35, A-21
FPSCR isntructions, 2-28, A-19
multiply-add, 2-27, A-18
rounding and conversion, 2-27, A-18
illegal instructions, 2-18
integer
arithmetic, 2-22, A-15
compare, 2-23, A-16
load, A-19
logical, 2-24, A-16
multiple, 2-32, A-20
rotate and shift, 2-25, A-17
store, 2-31, A-20
latency summary, 6-26
load and store
address generation, floating-point, 2-34
address generation, integer, 2-30
byte-reverse instructions, 2-32, A-20
integer load, 2-30
integer multiple instructions, 2-32, A-20
integer store, 2-31
string instructions, 2-33, A-20
memory control, 2-41, 2-44, 3-22, A-23
memory synchronization, 2-38, 2-40, A-21
PowerPC instructions, list
form (format), A-25
function, A-15
legend, A-35
mnemonic, A-1
opcode, A-8
processor control, 2-38, 2-40, 2-43, A-23
reserved instructions, 2-18
segment register manipulation, 2-45, A-23
simplified mnemonics, 2-46
supervisor-level cache management, 2-44
support for
lwarx
/
stwcx.
, 8-41
system linkage, 2-43, A-22
TLB management instructions, 2-45, A-24
trap instructions, 2-37, A-22
INT signal, 7-23, 8-40
Integer arithmetic instructions, 2-22, A-15
Integer compare instructions, 2-23, A-16
Integer load instructions, 2-30, A-19
Integer logical instructions, 2-24, A-16
Integer multiple instructions, 2-32, A-20
Integer rotate and shift instructions, 2-25, A-17
Integer store instructions, 2-31, A-20
Integer unit
execution timing, 6-21
latency, integer instructions, 6-28
overview, 1-9
Interrupt, external, 4-23
Interrupt,
see
Exceptions
K
Kill block operation, 3-19
L
Latency, 6-2, 6-26, 8-24
Load operations
memory coherency actions, 3-18
Load/store
address generation, 2-30, 2-34
byte-reverse instructions, 2-32, A-20
floating-point load instructions, 2-34, A-21
floating-point move instructions, 2-29, A-22
floating-point store instructions, 2-35, A-21