LITE5200B User’s Manual, Rev. 2
Glossary-1
Freescale Semiconductor
Glossary of Terms and Abbreviations
The glossary contains an alphabetical list of terms, phrases, and abbreviations used in this book. Some of
the terms and definitions included in the glossary are reprinted from IEEE Standard 754-1985,
IEEE
Standard for Binary Floating-Point Arithmetic
, copyright ©1985 by the Institute of Electrical and
Electronics Engineers, Inc. with the permission of the IEEE.
A
Architecture.
A detailed specification of requirements for a processor or computer
system. It does not specify details of how the processor or computer system must
be implemented; instead it provides a template for a family of compatible
implementations
.
Asynchronous exception.
Exceptions
that are caused by events external to the
processor’s execution. In this document, the term ‘asynchronous exception’ is
used interchangeably with the word
interrupt
.
Atomic access.
A bus access that attempts to be part of a read-write operation to the same
address uninterrupted by any other access to that address (the term refers to the
fact that the transactions are indivisible). The PowerPC architecture implements
atomic accesses through the
lwarx
/
stwcx.
instruction pair.
B
BAT (block address translation) mechanism.
A software-controlled array that stores the
available block address translations on-chip.
Beat.
A single state on the 603e bus interface that may extend across multiple bus cycles.
A 603e transaction can be composed of multiple address or data
beats
.
Biased exponent.
An
exponent
whose range of values is shifted by a constant (bias).
Typically a bias is provided to allow a range of positive values to express a range
that includes both positive and negative values.
Big-endian.
A byte-ordering method in memory where the address
n
of a word
corresponds to the
most-significant byte
. In an addressed memory word, the bytes
are ordered (left to right) 0, 1, 2, 3, with 0 being the
most-significant byte
. See
Little-endian
.
Block.
An area of memory that ranges from 128 Kbyte to 256 Mbyte whose size,
translation, and protection attributes are controlled by the BAT mechanism.
Boundedly undefined.
A characteristic of certain operation results that are not rigidly
prescribed by the PowerPC architecture. Boundedly- undefined results for a given
operation may vary among implementations and between execution attempts in
the same implementation.
Although the architecture does not prescribe the exact behavior for when results are
allowed to be boundedly undefined, the results of executing instructions in
contexts where results are allowed to be
boundedly undefined
are constrained to
ones that could have been achieved by executing an arbitrary sequence of defined
instructions, in valid form, starting in the state the machine was in before
attempting to execute the given instruction.