Switches
LITE5200B User’s Manual, Rev. 0
Freescale Semiconductor
4-19
a software algorithm. R208 limits the drive on the "PWR_DN_CTL_STS" net between the MPC5200B
and the QT1.
4.6.4.2
Signaling between the MPC5200B and the QT1
The net "PWR_DN_CTL_STS" goes between ports A4 and A5 of the QT1 and port PSC2_4 of the
MPC5200B. Port A5 of the QT1 is used to sense the state of the net. Port A4 is used to provide medium
impedance stimulus to the net through R208. The MPC5200B can drive the net when PSC2_4 is
configured as an output and can sense the state of the net when PSC2_4 is configured as an input. All
signals between the MPC5200B and the QT1 are conducted over this net. These signals are described in
the protocol below.
4.6.4.3
Normal Power Mode
In normal power mode (i.e. following a cold power up) the QT1 allows the 1.5V and 3.3V regulators to
operate and will drive the "PWR_DN_CTL_STS" signal high through R208. The high state of this net may
be sensed by the MPC5200B and indicates a cold power up.
4.6.4.4
Requesting Preparation for Low Power Mode
A request to prepare to enter low power mode may come in two ways. First, the request may come from
the system software or operating system. This may be in response to conditions such as low battery or
system idle. Code to support this must be added to the system software by the user. Second, the request
may come from an external stimulus such as the pushbutton (SW4). In normal power mode the QT1
microcontroller will respond to a pushbutton press by sending a low going 10 uS pulse to the MPC5200B
through R208 when the pushbutton is released. Following the low pulse the QT1 drives the
"PWR_DN_CTL_STS" net high through R208. The MPC5200B port PSC2_4 may be configured as an
edge sensitive interrupt with an optional wake up function. This will allow it to sense the external request
pulse without polling and even if in sleep mode.
4.6.4.5
Low Power Entry
Following a request to enter to low power mode from either a software event or the hardware signal, the
MPC5200B must save its context into the DDR RAM. The MPC5200B should wait 10 uS after
"PWR_DN_CTL_STS" returns to a high state and then signal the QT1 by driving the
"PWR_DN_CTL_STS" net low. This is done by configuring MPC5200B port PSC2_4 as an output with
a data out value of "0". Since the QT1 is driving the net high through R208 the MPC5200B can overdrive
the net pulling it low. When the QT1 senses the net held low it will assert the shutdown pins of the 1.5V
and 3.3V regulators for the board. This causes entry into low power mode. The QT1 will also change the
drive on the "PWR_DN_CTL_STS" from high to low signaling that the board is in low power mode.
Note that it is not necessary to send an external request (such as pressing SW4) before the MOPC5200B
signals the QT1 to effect entry into low power mode.
4.6.4.6
Restart
When in low power mode a restart may be initiated by a subsequent press of the SW4 switch. When the
pushbutton is released the QT1 will re-enable the 1.5V and 3.3V regulators restoring power to the board.
This will appear to the rest of the board as a power on and the power monitor circuit will signal a power
on reset (POR). Since the QT1 drives the "PWR_DN_CTL_STS" net low when entering low power mode
the MPC5200B can determine that the power up reset is the result of a warm power up from power down