LITE5200B User’s Manual, Rev. 2
Glossary-2
Freescale Semiconductor
Branch folding.
The replacement with target instructions of a branch instruction and any
instructions along the not-taken path when a branch is either taken or predicted as
taken.
Branch prediction.
The process of guessing whether a branch will be taken. Such
predictions can be correct or incorrect; the term ‘predicted’ as it is used here does
not imply that the prediction is correct (successful). The PowerPC architecture
defines a means for static branch prediction as part of the instruction encoding.
Branch resolution.
The determination of whether a branch is taken or not taken. A branch
is said to be resolved when the processor can determine which instruction path to
take. If the branch is resolved as predicted, the instructions following the predicted
branch that may have been speculatively executed can complete. If the branch is
not resolved as predicted, instructions on the mispredicted path, and any results of
speculative execution, are purged from the pipeline and fetching continues from
the nonpredicted path.
Burst.
A multiple-beat data transfer whose total size is typically equal to a cache block.
Bus clock.
Clock that causes the bus state transitions.
Bus master.
The owner of the address or data bus; the device that initiates or requests the
transaction.
C
Cache.
High-speed memory containing recently accessed data or instructions (subset of
main memory).
Cache block.
A small region of contiguous memory that is copied from memory into a
cache
. The size of a cache block may vary among processors; the maximum block
size is one
page
. In PowerPC processors,
cache coherency
is maintained on a
cache-block basis. Note that the term ‘cache block’ is often used interchangeably
with ‘cache line.’
Cache coherency.
An attribute wherein an accurate and common view of memory is
provided to all devices that share the same memory system. Caches are coherent
if a processor performing a read from its cache is supplied with data corresponding
to the most recent value written to memory or to another processor’s cache.
Cache flush.
An operation that removes from a cache any data from a specified address
range. This operation ensures that any modified data within the specified address
range is written back to main memory. This operation is generated typically by a
Data Cache Block Flush (
dcbf
) instruction.
Caching-inhibited.
A memory update policy in which the
cache
is bypassed and the load
or store is performed to or from main memory.
Cast out.
A
cache block
that must be written to memory when a cache miss causes a cache
block to be replaced.