LITE5200B User’s Manual, Rev. 2
Index-2
Freescale Semiconductor
latency, branch instructions, 6-26
overview, 1-9
Branch resolution
definition, 6-1
Burst data transfers
32-bit data bus, 8-14
64-bit data bus, 8-13
transfers with data delays, timing, 8-35
Burst transactions, 3-8
Bus arbitration,
see
Data bus
Bus configurations, 8-37, 8-39
Bus interface unit (BIU), 3-2
Byte ordering
default, 2-19
Byte-reverse instructions, 2-32, A-20
C
Cache
cache miss, 6-13
characteristics, 3-1
instructions, 2-41, 2-44, 3-22, A-23
MEI state definition, 3-15
organization, instruction/data, 3-3–3-7
overview, 1-25
Cache arbitration, 6-10
Cache block push operation, 3-8
Cache block, definition, 3-1
Cache cast-out operation, 3-8
Cache coherency
actions on load operations, 3-18
actions on store operations, 3-19
copy-back operation, 3-11
in single-processor systems, 3-18
MEI protocol, 3-15
out-of-order execution, 3-13
overview, 3-2
reaction to bus operations, 3-19
WIMG bits, 3-10, 3-13, 8-29
write-back mode, 3-11
Cache hit, 6-10
Cache management
instructions, 2-41, 2-44, 3-22, A-23
Cache operations
basic data cache operations, 3-8
data cache transactions, 3-8
instruction cache fill operations, 3-4
overview, 1-13, 3-1
response to bus transactions, 3-19
Cache unit
memory performance, 6-22
operation of the cache, 8-2
overview, 3-1
Cache-inhibited accesses (I bit)
cache interactions, 3-10
I-bit setting, 3-11
timing considerations, 6-23
Changed (C) bit maintenance
recording, 5-11, 5-21–5-23
Checkstop
signal, 7-24, 8-40
state, 4-20
CI signal, 7-13
Classes of instructions, 2-17
Clean block operation, 3-19
Clock signals
CLK_OUT, 7-30
PLL_CFG
n
, 7-30
SYSCLK, 7-29
Compare instructions, 2-28, A-16
Completion
definition, 6-1
Completion considerations, 6-15
Context synchronization, 2-20
Conventions, xxxii, xxxvi, 2-13
COP/scan interface, 7-27
Copy-back mode, 6-23
CR logical instructions, 2-37
CSE
n
signals, 7-14, 8-29
D
Data bus
32-bit data bus mode, 8-37
arbitration signals, 7-16, 8-7
bus arbitration, 8-21
data tenure, 8-6
data transfer, 7-18, 8-23
data transfer termination, 7-21, 8-24
Data cache
basic operations, 3-8
broadcasting, 3-7
bus transactions, 3-8
cache control, 3-6
configuration, 3-1
DCFI, DCE, DLOCK bits, 3-6
disabling, 3-6
fill operations, 3-8
locking, 3-7
organization, 3-5
touch load operations, 3-7
touch load support, 3-7
Data storage interrupt (DSI),
see
DSI exception
Data TLB miss on load exception, 4-30
Data TLB miss on store exception, 4-31
Data transfers
alignment, 2-14, 8-14
burst ordering, 8-13
eciwx and ecowx instructions, alignment, 8-18
signals, 8-23