LITE5200B User’s Manual, Rev. 2
Freescale Semiconductor
Glossary-5
Hashing.
An algorithm used in the
page table
search process.
I
IEEE 754.
A standard written by the Institute of Electrical and Electronics Engineers that
defines operations and representations of binary floating-point numbers.
Illegal instructions.
A class of instructions that are not implemented for a particular
PowerPC processor. These include instructions not defined by the PowerPC
architecture. In addition, for 32-bit implementations, instructions that are defined
only for 64-bit implementations are considered to be illegal instructions. For
64-bit implementations instructions that are defined only for 32-bit
implementations are considered to be illegal instructions.
Implementation.
A particular processor that conforms to the PowerPC architecture, but
may differ from other architecture-compliant implementations for example in
design, feature set, and implementation of
optional
features. The PowerPC
architecture has many different implementations.
Imprecise exception.
A type of
synchronous exception
that is allowed not to adhere to the
precise exception model (see
Precise exception
). The PowerPC architecture
allows only floating-point exceptions to be handled imprecisely.
Instruction queue.
A holding place for instructions fetched from the current instruction
stream.
Integer unit.
The functional unit in the 603e responsible for executing all integer
instructions.
In-order.
An aspect of an operation that adheres to a sequential model. An operation is
said to be performed in-order if, at the time that it is performed, it is known to be
required by the sequential execution model. See
Out-of-order
.
Instruction latency.
The total number of clock cycles necessary to execute an instruction
and make ready the results of that instruction.
Interrupt.
An external signal that causes the 603e to suspend current execution and take
a predefined exception.
K
Key bits.
A set of key bits referred to as Ks and Kp in each segment register and each BAT
register. The key bits determine whether supervisor or user programs can access a
page
within that
segment
or
block
.
Kill.
An operation that causes a
cache block
to be invalidated without writing any modified
data to memory.
L
Latency.
The number of clock cycles necessary to execute an instruction and make ready
the results of that execution for a subsequent instruction.
L2 cache.
See
Secondary
cache
.